Intel BX80646E31230V3, BX80646E31240V3 User Manual
Intel® Xeon® Processor E3-1200 v3
Product Family
Datasheet – Volume 1 of 2
June 2013
Order No.: 328907-001
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death.
SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND
ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL
CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF
PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL
OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS.
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or
characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without
notice. Do not finalize a design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling
1-800-548-4725, or go to: http://www.intel.com/design/literature.htm
Any software source code reprinted in this document is furnished for informational purposes only and may only be used or copied and no license,
express or implied, by estoppel or otherwise, to any of the reprinted source code is granted by this document.
Any software source code reprinted in this document is furnished under a software license and may only be used or copied in accordance with the
terms of that license.
This document contains information on products in the design phase of development.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different
processor families: Go to: http://www.intel.com/products/processor_number
Code Names are only for use by Intel to identify products, platforms, programs, services, etc. ("products") in development by Intel that have not been
made commercially available to the public, i.e., announced, launched or shipped. They are never to be used as "commercial" names for products. Also,
they are not intended to function as trademarks.
Intel® Hyper-Threading Technology (Intel® HT Technology) is available on select Intel® Core™ processors. It requires an Intel® HT Technology
enabled system. Consult your PC manufacturer. Performance will vary depending on the specific hardware and software used. Not available on Intel
Core™ i5-750. For more information including details on which processors support Intel® HT Technology, visit http://www.intel.com/info/
hyperthreading.
Intel® 64 architecture requires a system with a 64-bit enabled processor, chipset, BIOS and software. Performance will vary depending on the specific
hardware and software you use. Consult your PC manufacturer for more information. For more information, visit http://www.intel.com/
content/www/us/en/architecture-and-technology/microarchitecture/intel-64-architecture-general.html.
No computer system can provide absolute security under all conditions. Intel® Trusted Execution Technology (Intel® TXT) requires a computer with
Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured
launched environment (MLE). Intel TXT also requires the system to contain a TPM v1.s. For more information, visit http://www.intel.com/technology/
security.
Intel® Virtualization Technology (Intel® VT) requires a computer system with an enabled Intel® processor, BIOS, and virtual machine monitor (VMM).
Functionality, performance or other benefits will vary depending on hardware and software configurations. Software applications may not be
compatible with all operating systems. Consult your PC manufacturer. For more information, visit http://www.intel.com/go/virtualization.
Requires a system with Intel® Turbo Boost Technology. Intel Turbo Boost Technology and Intel Turbo Boost Technology 2.0 are only available on select
Intel® processors. Consult your PC manufacturer. Performance varies depending on hardware, software, and system configuration. For more
information, visit http://www.intel.com/go/turbo.
Requires activation and a system with a corporate network connection, an Intel® AMT-enabled chipset, network hardware and software. For
notebooks, Intel AMT may be unavailable or limited over a host OS-based VPN, when connecting wirelessly, on battery power, sleeping, hibernating or
powered off. Results dependent upon hardware, setup and configuration.
Intel, Intel Xeon, Intel vPro, Ultrabook, vPro Inside, and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2013, Intel Corporation. All rights reserved.
®
®
Xeon® Processor E3-1200 v3 Product Family
Intel
Datasheet – Volume 1 of 2 June 2013
2 Order No.: 328907-001
Contents—Processor
Contents
Revision History..................................................................................................................8
1.0 Introduction................................................................................................................. 9
1.1 Supported Technologies.........................................................................................10
1.2 Interfaces............................................................................................................ 11
1.3 Power Management Support...................................................................................11
1.4 Thermal Management Support................................................................................12
1.5 Package Support...................................................................................................12
1.6 Terminology.........................................................................................................12
1.7 Related Documents............................................................................................... 15
2.0 Interfaces................................................................................................................... 17
2.1 System Memory Interface...................................................................................... 17
2.1.1 System Memory Technology Supported.......................................................18
2.1.2 System Memory Timing Support................................................................. 19
2.1.3 System Memory Organization Modes........................................................... 19
2.1.3.1 System Memory Frequency............................................................ 21
2.1.3.2 Intel® Fast Memory Access (Intel® FMA) Technology Enhancements... 21
2.1.3.3 Data Scrambling.......................................................................... 21
2.2 PCI Express* Interface.......................................................................................... 22
2.2.1 PCI Express* Support................................................................................22
2.2.2 PCI Express* Architecture.......................................................................... 23
2.2.3 PCI Express* Configuration Mechanism........................................................ 23
2.3 Direct Media Interface (DMI).................................................................................. 25
2.4 Processor Graphics................................................................................................27
2.5 Processor Graphics Controller (GT)..........................................................................27
2.5.1 3D and Video Engines for Graphics Processing.............................................. 28
2.5.2 Multi Graphics Controllers Multi-Monitor Support........................................... 30
2.6 Digital Display Interface (DDI)................................................................................30
2.7 Intel® Flexible Display Interface (Intel® FDI)............................................................36
2.8 Platform Environmental Control Interface (PECI)....................................................... 36
2.8.1 PECI Bus Architecture................................................................................36
3.0 Technologies...............................................................................................................38
3.1 Intel® Virtualization Technology (Intel® VT)............................................................. 38
3.2 Intel® Trusted Execution Technology (Intel® TXT).....................................................42
3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)....................................... 43
3.4 Intel® Turbo Boost Technology............................................................................... 44
3.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)................................................44
3.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI).......................45
3.7 Intel® Transactional Synchronization Extensions (Intel® TSX).................................... 45
3.8 Intel® 64 Architecture x2APIC................................................................................ 46
3.9 Power Aware Interrupt Routing (PAIR)....................................................................47
3.10 Execute Disable Bit..............................................................................................47
3.11 Supervisor Mode Execution Protection (SMEP)........................................................47
4.0 Power Management.................................................................................................... 48
4.1 Advanced Configuration and Power Interface (ACPI) States Supported......................... 49
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 3
Intel® Xeon® Processor E3-1200 v3 Product Family
Processor—Contents
4.2 Processor Core Power Management......................................................................... 50
4.2.1 Enhanced Intel® SpeedStep® Technology Key Features..................................50
4.2.2 Low-Power Idle States............................................................................... 51
4.2.3 Requesting Low-Power Idle States...............................................................52
4.2.4 Core C-State Rules....................................................................................53
4.2.5 Package C-States......................................................................................54
4.3 Integrated Memory Controller (IMC) Power Management............................................58
4.3.1 Disabling Unused System Memory Outputs...................................................58
4.3.2 DRAM Power Management and Initialization..................................................58
4.3.2.1 Initialization Role of CKE................................................................ 59
4.3.2.2 Conditional Self-Refresh.................................................................60
4.3.2.3 Dynamic Power-Down....................................................................60
4.3.2.4 DRAM I/O Power Management........................................................ 60
4.3.3 DRAM Running Average Power Limitation (RAPL) .........................................60
4.3.4 DDR Electrical Power Gating (EPG).............................................................. 61
4.4 PCI Express* Power Management............................................................................61
4.5 Direct Media Interface (DMI) Power Management...................................................... 61
4.6 Graphics Power Management..................................................................................61
4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)................................61
4.6.2 Graphics Render C-State............................................................................61
4.6.3 Intel® Graphics Dynamic Frequency............................................................ 61
5.0 Thermal Management................................................................................................. 63
5.1 Thermal Metrology................................................................................................ 64
5.2 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 1.1.............................. 64
5.3 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0.............................. 66
5.4 Intel® Xeon® Processor E3-1200 v3 Product Family Thermal Specifications...................67
5.5 Processor Temperature..........................................................................................69
5.6 Adaptive Thermal Monitor...................................................................................... 69
5.7 THERMTRIP# Signal.............................................................................................. 72
5.8 Digital Thermal Sensor.......................................................................................... 73
5.8.1 Digital Thermal Sensor Accuracy (Taccuracy)................................................73
5.9 Intel® Turbo Boost Technology Thermal Considerations..............................................74
5.9.1 Intel® Turbo Boost Technology Power Control and Reporting.......................... 74
5.9.2 Package Power Control.............................................................................. 75
5.9.3 Turbo Time Parameter............................................................................... 75
6.0 Signal Description....................................................................................................... 77
6.1 System Memory Interface Signals........................................................................... 77
6.2 Memory Reference and Compensation..................................................................... 79
6.3 Reset and Miscellaneous Signals............................................................................. 80
6.4 PCI Express*-Based Interface Signals......................................................................81
6.5 Display Interface Signals....................................................................................... 81
6.6 Direct Media Interface (DMI).................................................................................. 82
6.7 Phase Locked Loop (PLL) Signals.............................................................................82
6.8 Testability Signals.................................................................................................82
6.9 Error and Thermal Protection Signals.......................................................................83
6.10 Power Sequencing...............................................................................................84
6.11 Processor Power Signals.......................................................................................84
6.12 Sense Pins......................................................................................................... 84
6.13 Ground and Non-Critical to Function (NCTF) Signals.................................................85
Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2 June 2013
4 Order No.: 328907-001
Contents—Processor
6.14 Processor Internal Pull-Up / Pull-Down Terminations................................................ 85
7.0 Electrical Specifications.............................................................................................. 86
7.1 Integrated Voltage Regulator..................................................................................86
7.2 Power and Ground Lands ...................................................................................... 86
7.3 VCC Voltage Identification (VID).............................................................................. 86
7.4 Reserved or Unused Signals................................................................................... 91
7.5 Signal Groups.......................................................................................................91
7.6 Test Access Port (TAP) Connection.......................................................................... 93
7.7 DC Specifications................................................................................................. 93
7.8 Voltage and Current Specifications.......................................................................... 94
7.8.1 PECI DC Characteristics............................................................................. 99
7.8.2 Input Device Hysteresis........................................................................... 100
8.0 Package Mechanical Specifications........................................................................... 101
8.1 Processor Component Keep-Out Zone.................................................................... 101
8.2 Package Loading Specifications............................................................................. 101
8.3 Package Handling Guidelines................................................................................ 102
8.4 Package Insertion Specifications............................................................................102
8.5 Processor Mass Specification.................................................................................102
8.6 Processor Materials............................................................................................. 102
8.7 Processor Markings............................................................................................. 103
8.8 Processor Land Coordinates..................................................................................103
8.9 Processor Storage Specifications........................................................................... 104
9.0 Processor Ball and Signal Information...................................................................... 106
Figures
1 Platform Block Diagram ........................................................................................... 10
2 Intel® Flex Memory Technology Operations................................................................. 20
3 PCI Express* Related Register Structures in the Processor............................................ 24
4 PCI Express* Typical Operation 16 Lanes Mapping....................................................... 25
5 Processor Graphics Controller Unit Block Diagram........................................................ 28
6 Processor Display Architecture...................................................................................31
7 DisplayPort* Overview............................................................................................. 32
8 HDMI* Overview..................................................................................................... 33
9 Example for PECI Host-Clients Connection.................................................................. 37
10 Device to Domain Mapping Structures........................................................................ 41
11 Processor Power States............................................................................................ 48
12 Idle Power Management Breakdown of the Processor Cores ..........................................51
13 Thread and Core C-State Entry and Exit......................................................................52
14 Package C-State Entry and Exit................................................................................. 56
15 Thermal Test Vehicle (TTV) Case Temperature (T
16 Digital Thermal Sensor (DTS) 1.1 Definition Points.......................................................65
17 Digital Thermal Sensor (DTS) Thermal Profile Definition................................................67
18 Package Power Control............................................................................................. 75
19 Input Device Hysteresis.......................................................................................... 100
20 Processor Package Assembly Sketch.........................................................................101
21 Processor Top-Side Markings................................................................................... 103
22 Processor Package Land Coordinates........................................................................ 104
) Measurement Location..................64
CASE
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 5
Intel® Xeon® Processor E3-1200 v3 Product Family
Processor—Contents
Tables
1 Terminology........................................................................................................... 12
2 Related Documents..................................................................................................15
3 Processor DIMM Support by Product...........................................................................18
4 Supported UDIMM Module Configurations....................................................................18
5 PCI Express* Supported Configurations in Server / Workstation Products........................ 22
6 Processor Supported Audio Formats over HDMI*and DisplayPort*.................................. 34
7 Valid Three Display Configurations through the Processor..............................................35
8 DisplayPort and Embedded DisplayPort* Resolutions for 1, 2, 4 Lanes – Link Data
Rate of RBR, HBR, and HBR2.....................................................................................35
9 System States.........................................................................................................49
10 Processor Core / Package State Support..................................................................... 49
11 Integrated Memory Controller States..........................................................................49
12 PCI Express* Link States.......................................................................................... 49
13 Direct Media Interface (DMI) States........................................................................... 50
14 G, S, and C Interface State Combinations .................................................................. 50
15 D, S, and C Interface State Combination.....................................................................50
16 Coordination of Thread Power States at the Core Level................................................. 52
17 Coordination of Core Power States at the Package Level............................................... 55
18 Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance Above T
CONTROL
19 Thermal Margin Slope.............................................................................................. 67
20 Boundary Conditions, Performance Targets, and T
Specifications.............................. 68
CASE
21 Intel® Turbo Boost Technology 2.0 Package Power Control Settings............................... 75
22 Signal Description Buffer Types................................................................................. 77
23 Memory Channel A...................................................................................................77
24 Memory Channel B...................................................................................................78
25 Memory Reference and Compensation ....................................................................... 79
26 Reset and Miscellaneous Signals................................................................................ 80
27 PCI Express* Graphics Interface Signals..................................................................... 81
28 Display Interface Signals.......................................................................................... 81
29 Direct Media Interface (DMI) – Processor to PCH Serial Interface................................... 82
30 Phase Locked Loop (PLL) Signals............................................................................... 82
31 Testability Signals....................................................................................................82
32 Error and Thermal Protection Signals..........................................................................83
33 Power Sequencing................................................................................................... 84
34 Processor Power Signals........................................................................................... 84
35 Sense Pins..............................................................................................................84
36 Ground and Non-Critical to Function (NCTF) Signals..................................................... 85
37 Processor Internal Pull-Up / Pull-Down Terminations.................................................... 85
38 VR 12.5 Voltage Identification................................................................................... 87
39 Signal Groups......................................................................................................... 91
40 Processor Core Active and Idle Mode DC Voltage and Current Specifications.................... 94
41 Memory Controller (V
) Supply DC Voltage and Current Specifications.........................95
DDQ
42 VCCIO_OUT, VCOMP_OUT, and VCCIO_TERM ............................................................. 96
43 DDR3/DDR3L Signal Group DC Specifications.............................................................. 96
44 Digital Display Interface Group DC Specifications......................................................... 97
45 Embedded DisplayPort* (eDP) Group DC Specifications.................................................98
46 CMOS Signal Group DC Specifications.........................................................................98
47 GTL Signal Group and Open Drain Signal Group DC Specifications.................................. 98
48 PCI Express* DC Specifications..................................................................................99
49 PECI DC Electrical Limits...........................................................................................99
50 Processor Loading Specifications.............................................................................. 102
51 Package Handling Guidelines................................................................................... 102
52 Processor Materials................................................................................................ 103
............. 66
Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2 June 2013
6 Order No.: 328907-001
Contents—Processor
53 Processor Storage Specifications.............................................................................. 104
54 Processor Ball List by Signal Name........................................................................... 106
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 7
Intel® Xeon® Processor E3-1200 v3 Product Family
Revision History
Revision Description Date
001 • Initial Release June 2013
Processor—Revision History
Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2 June 2013
8 Order No.: 328907-001
Introduction—Processor
1.0 Introduction
The Intel® Xeon® processor E3-1200 v3 product family are 64-bit, multi-core
processors built on 22-nanometer process technology.
The processors are designed for a two-chip platform consisting of a processor and
Platform Controller Hub (PCH). The processors are designed to be used with the Intel
C220 Series chipset. See the following figure for an example platform block diagram.
Note: Throughout this document, the Intel® Xeon® processor E3-1200 v3 product family
may be referred to simply as "processor".
Note: Throughout this document, the Intel® C220 Series chipset may be referred to simply
as "PCH".
Throughout this document, the Intel® Xeon® processor E3-1200 v3 product family
refers to the Intel® Xeon® E3-1285 v3, E3-1285L v3, E3-1280 v3, E3-1275 v3,
E3-1270 v3, E3-1265L v3, E3-1245 v3, E3-1240 v3, E3-1230 v3, E3-1230L v3,
E3-1225 v3, E3-1220 v3, E3-1220L v3 processors.
Note: Some processor features are not available on all platforms. Refer to the processor
Specification Update document for details.
®
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 9
Intel® Xeon® Processor E3-1200 v3 Product Family
Figure 1. Platform Block Diagram
Processor
PCI Express* 3.0
Digital Display
Interface (DDI)
(3 interfaces)
System Memory
1333 / 1600 MT/s
2 DIMMs / CH
CH A
CH B
Intel® Flexible Display
Interface (Intel® FDI)
(x2)
Direct Media Interface 2.0
(DMI 2.0) (x4)
Note: 2 DIMMs / CH is not
supported on all SKUs.
Platform Controller
Hub (PCH)
SATA, 6 GB/s
(up to 6 Ports)
Analog Display
(VGA)
SPI Flash
Super IO / EC
Trusted Platform
Module (TPM) 1.2
LPC
Intel® High
Definition Audio
(Intel® HD Audio)
Integrated LAN
USB 3.0
(up to 6 Ports)
USB 2.0
(8 Ports)
PCI Express* 2.0
(up to 8 Ports)
SPI
SMBus 2.0
GPIOs
Processor—Introduction
1.1 Supported Technologies
• Intel Virtualization Technology (Intel® VT)
• Intel Active Management Technology 9.0 (Intel® AMT 9.0)
• Server Platform Services 3.0 (SPS 3.0)
• Intel® Trusted Execution Technology (Intel® TXT)
• Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
• Intel® Hyper-Threading Technology (Intel® HT Technology)
• Intel® 64 Architecture
• Execute Disable Bit
• Intel® Turbo Boost Technology 2.0
• Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)
Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2 June 2013
10 Order No.: 328907-001
Introduction—Processor
• Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
• PCLMULQDQ Instruction
• Intel® Secure Key
• Intel® Transactional Synchronization Extensions (Intel® TSX)
• PAIR – Power Aware Interrupt Routing
• SMEP – Supervisor Mode Execution Protection
Note: The availability of the features may vary between processor SKUs.
1.2 Interfaces
The processor supports the following interfaces:
• DDR3/DDR3L
• Direct Media Interface (DMI)
• Digital Display Interface (DDI)
• PCI Express*
1.3 Power Management Support
Processor Core
• Full support of ACPI C-states as implemented by the following processor C-states:
— C0, C1, C1E, C3, C6, C7
• Enhanced Intel SpeedStep® Technology
System
• S0, S3, S4, S5
Memory Controller
• Conditional self-refresh
• Dynamic power-down
PCI Express*
• L0s and L1 ASPM power management capability
DMI
• L0s and L1 ASPM power management capability
Processor Graphics Controller
• Intel® Rapid Memory Power Management (Intel® RMPM)
• Intel® Smart 2D Display Technology (Intel® S2DDT)
• Graphics Render C-state (RC6)
• Intel® Seamless Display Refresh Rate Switching with eDP port
• Intel® Display Power Saving Technology (Intel® DPST)
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 11
Intel® Xeon® Processor E3-1200 v3 Product Family
1.4 Thermal Management Support
• Digital Thermal Sensor
• Adaptive Thermal Monitor
• THERMTRIP# and PROCHOT# support
• On-Demand Mode
• Memory Open and Closed Loop Throttling
• Memory Thermal Throttling
• External Thermal Sensor (TS-on-DIMM and TS-on-Board)
• Render Thermal Throttling
• Fan speed control with DTS
1.5 Package Support
The processor socket type is noted as LGA 1150. The package is a 37.5 x 37.5 mm
Flip Chip Land Grid Array (FCLGA 1150). See the appropriate Processor Thermal
Mechanical Design Guidelines and LGA1150 Socket Application Guide for complete
details on the package.
Processor—Introduction
1.6 Terminology
Table 1. Terminology
Term Description
APD Active Power-down
B/D/F Bus/Device/Function
BGA Ball Grid Array
BLC Backlight Compensation
BLT Block Level Transfer
BPP Bits per pixel
CKE Clock Enable
CLTM Closed Loop Thermal Management
DDI Digital Display Interface
DDR3 Third-generation Double Data Rate SDRAM memory technology
DLL Delay-Locked Loop
DMA Direct Memory Access
DP DisplayPort*
DTS Digital Thermal Sensor
EC Embedded Controller
ECC Error Correction Code
continued...
Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2 June 2013
12 Order No.: 328907-001
Introduction—Processor
eDP Embedded Display Port
EPG Electrical Power Gating
EU Execution Unit
FMA Floating-point fused Multiply Add instructions
FSC Fan Speed Control
HDCP High-bandwidth Digital Content Protection
HDMI* High Definition Multimedia Interface
HFM High Frequency Mode
iDCT Inverse Discrete
IHS Integrated Heat Spreader
GFX Graphics
GUI Graphical User Interface
IMC Integrated Memory Controller
Intel® 64
Technology
Intel® DPST Intel Display Power Saving Technology
Intel® TSX Intel Transactional Synchronization Extensions
Intel® TXT Intel Trusted Execution Technology
Intel® VT
Intel® VT-d
IOV I/O Virtualization
ISI Inter-Symbol Interference
ITPM Integrated Trusted Platform Module
LFM
LFP Local Flat Panel
LPDDR3 Low Power Third-generation Double Data Rate SDRAM memory technology
MCP Multi-Chip Package
MFM
MLE Measured Launched Environment
MLC Mid-Level Cache
MSI Message Signaled Interrupt
MSL Moisture Sensitive Labeling
MSR Model Specific Registers
Term Description
64-bit memory extensions to the IA-32 architecture
Intel Virtualization Technology. Processor virtualization, when used in conjunction
with Virtual Machine Monitor software, enables multiple, robust independent software
environments inside a single platform.
Intel Virtualization Technology (Intel VT) for Directed I/O. Intel VT-d is a hardware
assist, under system software (Virtual Machine Manager or OS) control, for enabling
I/O device virtualization. Intel VT-d also brings robust security by providing protection
from errant DMAs by using DMA remapping, a key feature of Intel VT-d.
Low Frequency Mode. LFM is Pn in the P-state table. It can be read at MSR CEh
[47:40].
Minimum Frequency Mode. MFM is the minimum ratio supported by the processor and
can be read from MSR CEh [55:48].
continued...
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 13
Intel® Xeon® Processor E3-1200 v3 Product Family
Processor—Introduction
Term Description
Non-Critical to Function. NCTF locations are typically redundant ground or non-critical
NCTF
reserved, so the loss of the solder joint continuity at end of life conditions will not
affect the overall product functionality.
ODT On-Die Termination
OLTM Open Loop Thermal Management
PCG
Platform Compatibility Guide (PCG) (previously known as FMB) provides a design
target for meeting all planned processor frequency requirements.
Platform Controller Hub. The chipset with centralized platform capabilities including
PCH
the main I/O interfaces along with display connectivity, audio features, power
management, manageability, security, and storage features.
The Platform Environment Control Interface (PECI) is a one-wire interface that
PECI
provides a communication channel between Intel processor and chipset components
to external monitoring devices.
Case-to-ambient thermal characterization parameter (psi). A measure of thermal
Ψ
ca
solution performance using total package power. Defined as (T
Package Power. The heat source should always be specified for Y measurements.
- TLA ) / Total
CASE
PCI Express* Graphics. External Graphics using PCI Express* Architecture. It is a
PEG
high-speed serial interface where configuration is software compatible with the
existing PCI specifications.
PL1, PL2 Power Limit 1 and Power Limit 2
PPD Pre-charge Power-down
Processor The 64-bit multi-core component (package)
The term “processor core” refers to Si die itself, which can contain multiple execution
Processor Core
cores. Each execution core has an instruction cache, data cache, and 256-KB L2
cache. All execution cores share the L3 cache.
Processor Graphics Intel Processor Graphics
Rank A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC.
SCI System Control Interrupt. SCI is used in the ACPI protocol.
SF Strips and Fans
SMM System Management Mode
SMX Safer Mode Extensions
A non-operational state. The processor may be installed in a platform, in a tray, or
loose. Processors may be sealed in packaging or exposed to free air. Under these
conditions, processor landings should not be connected to any supply voltages, have
Storage Conditions
any I/Os biased, or receive any clocks. Upon exposure to “free air” (that is, unsealed
packaging or a device removed from packaging material), the processor must be
handled in accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
SVID Serial Voltage Identification
TAC Thermal Averaging Constant
TAP Test Access Point
T
CASE
The case temperature of the processor, measured at the geometric center of the topside of the TTV IHS.
TCC Thermal Control Circuit
continued...
Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2 June 2013
14 Order No.: 328907-001
Introduction—Processor
T
CONTROL
TDP
TLB Translation Look-aside Buffer
TTV
TM
V
CC
V
DDQ
VF Vertex Fetch
VID Voltage Identification
VS Vertex Shader
VLD Variable Length Decoding
VMM Virtual Machine Monitor
VR Voltage Regulator
V
SS
x1 Refers to a Link or Port with one Physical Lane
x2 Refers to a Link or Port with two Physical Lanes
x4 Refers to a Link or Port with four Physical Lanes
x8 Refers to a Link or Port with eight Physical Lanes
x16 Refers to a Link or Port with sixteen Physical Lanes
Term Description
T
is a static value that is below the TCC activation temperature and used as a
CONTROL
trigger point for fan speed control. When DTS > T
to the TTV thermal profile.
Thermal Design Power: Thermal solution should be designed to dissipate this target
power level. TDP is not the maximum power that the processor can dissipate.
Thermal Test Vehicle. A mechanically equivalent package that contains a resistive
heater in the die to evaluate thermal solutions.
Thermal Monitor. A power reduction feature designed to decrease temperature after
the processor has reached its maximum operating temperature.
Processor core power supply
DDR3L power supply.
Processor ground
, the processor must comply
CONTROL
1.7 Related Documents
Table 2. Related Documents
Document Document
Intel® Xeon® Processor E3-1200 v3 Product Family Datasheet, Volume 2 of 2 329000
Intel® Xeon® Processor E3-1200 v3 Product Family Specification Update 328908
Desktop 4th Generation Intel® Core® Processor Family and Intel® Xeon® Processor
E3-1200 v3 Product Family Thermal Mechanical Design Guidelines
LGA1150 Socket Application Guide 328999
Intel® 8 Series / C220 Series Chipset Family Platform Controller Hub (PCH)
Datasheet
Intel® 8 Series / C220 Series Chipset Family Platform Controller Hub (PCH)
Specification Update
Intel® 8 Series / C220 Series Chipset Family Platform Controller Hub (PCH) Thermal
Mechanical Specifications and Design Guidelines
Intel® Xeon® Processor E3-1200 v3 Product Family
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 15
Number / Location
328900
328904
328905
328906
continued...
Processor—Introduction
Document Document
Advanced Configuration and Power Interface 3.0
PCI Local Bus Specification 3.0
PCI Express Base Specification, Revision 2.0
DDR3 SDRAM Specification
DisplayPort* Specification http://www.vesa.org
Intel® 64 and IA-32 Architectures Software Developer's Manuals
Number / Location
http://
www.acpi.info/
http://
www.pcisig.com/
specifications
http://
www.pcisig.com
http://
www.jedec.org
http://
www.intel.com/
products/processor/
manuals/index.htm
Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2 June 2013
16 Order No.: 328907-001
Interfaces—Processor
2.0 Interfaces
2.1 System Memory Interface
• Two channels of DDR3/DDR3L Unbuffered Dual In-Line Memory Modules (UDIMM)
with a maximum of two DIMMs per channel.
• Single-channel and dual-channel memory organization modes
• Data burst length of eight for all memory organization modes
• Memory data transfer rates of 1333 MT/s and 1600 MT/s
• 64-bit wide channels
• DDR3/DDR3L I/O Voltage of 1.5 V for Intel AMT Server, and Workstation
• DDR3L I/O voltage of 1.35 V for Rack/Micro Server
• The type of the DIMM modules supported by the processor is dependent on the
PCH SKU in the target platform:
— Server PCH platforms support ECC UDIMMs only
— Workstation PCH platforms support ECC and non-ECC UDIMMs
• Theoretical maximum memory bandwidth of:
— 21.3 GB/s in dual-channel mode assuming 1333 MT/s
— 25.6 GB/s in dual-channel mode assuming 1600 MT/s
• 1Gb, 2Gb, and 4Gb DDR3/DDR3L DRAM device technologies are supported
— Using 4Gb DRAM device technologies, the largest system memory capacity
possible is 32 GB, assuming Dual Channel Mode with four x8 dual ranked
DIMM memory configuration
• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank
devices)
• Processor on-die VREF generation for DDR DQ Read and Write as well as
CMD/ADD
• Command launch modes of 1n/2n
• On-Die Termination (ODT)
• Asynchronous ODT
• Intel Fast Memory Access (Intel FMA):
— Just-in-Time Command Scheduling
— Command Overlap
— Out-of-Order Scheduling
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 17
Intel® Xeon® Processor E3-1200 v3 Product Family
Processor—Interfaces
2.1.1 System Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3/DDR3L protocols with two
independent, 64-bit wide channels each accessing one or two DIMMs. The type of
memory supported by the processor is dependent on the PCH SKU in the target
platform.
Note: The IMC supports a maximum of two DDR3/DDR3L DIMMs per channel; thus, allowing
up to four device ranks per channel.
Note: The support of DDR3/DDR3L frequencies and number of DIMMs per channel is SKU
dependent.
Table 3. Processor DIMM Support by Product
Processor Cores Package DIMM per Channel DDR3 / DDR3L
Dual Core uLGA
Quad Core uLGA
1 DPC 1333/1600
2 DPC 1333/1600
1 DPC 1333/1600
2 DPC 1333/1600
DDR3/DDR3L Data Transfer Rates:
• 1333 MT/s (PC3-10600)
• 1600 MT/s (PC3-12800)
• Standard 1Gb, 2Gb, and 4Gb technologies and addressing are supported for x8
devices. There is no support for memory modules with different technologies or
capacities on opposite sides of the same memory module. If one side of a memory
module is populated, the other side is either identical or empty.
Worksation platforms UDIMM Modules:
• Raw Card A – Single Ranked x8 unbuffered non-ECC
• Raw Card B – Dual Ranked x8 unbuffered non-ECC
• Raw Card D – Single Ranked x8 unbuffered ECC
• Raw Card E – Dual Ranked x8 unbuffered ECC
Server platforms UDIMM Modules:
• Raw Card D – Single Ranked x8 unbuffered ECC
• Raw Card E – Dual Ranked x8 unbuffered ECC
Table 4. Supported UDIMM Module Configurations
Raw
Card
Version
DIMM
Capacity
DRAM
Device
Technology
Unbuffered / Non-ECC Supported DIMM Module Configurations
DRAM
Organization
Server / Workstation Platforms
# of
DRAM
Devices
Physical
Devices
# of
Ranks
# of
Row / Col
Address
Bits
# of
Banks
Inside
DRAM
Page Size
continued...
Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2 June 2013
18 Order No.: 328907-001
Interfaces—Processor
Raw
Card
Version
A 1 GB 1 Gb 128 M X 8 8 1 14/10 8 8K
B
D
E
DIMM
Capacity
2 GB 1 Gb 128 M X 8 16 2 14/10 8 8K
4 GB 2 Gb 256 M X 8 16 2 15/10 8 8K
4 GB 4 Gb 512 M X 8 8 1 15/10 8 8K
8 GB 4 Gb 512 M X 8 16 2 16/10 8 8K
1 GB 1 Gb 128 M X 8 9 1 14/10 8 8K
2 GB 2 Gb 256 M X 8 9 1 15/10 8 8K
2 GB 1 Gb 128 M X 8 18 2 14/10 8 8K
4 GB 2 Gb 256 M X 8 18 2 15/10 8 8K
8 GB 4 Gb 512 M X 8 18 2 16/10 8 8K
DRAM
Device
Technology
Unbuffered / ECC Supported DIMM Module Configurations
DRAM
Organization
Server and Workstation Platforms
# of
DRAM
Devices
# of
Physical
Devices
Ranks
# of
Row / Col
Address
Bits
# of
Banks
Inside
DRAM
Page Size
Note: DIMM module support is based on availability and is subject to change.
Note: System memory configurations are based on availability and are subject to change.
2.1.2 System Memory Timing Support
2.1.3
The IMC supports the following DDR3L Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1N indicates a new command may be issued every
clock and 2N indicates a new command may be issued every 2 clocks. Command
launch mode programming depends on the transfer rate and memory
configuration.
System Memory Organization Modes
The Integrated Memory Controller (IMC) supports two memory organization modes –
single-channel and dual-channel. Depending upon how the DIMM Modules are
populated in each memory channel, a number of different configurations can exist.
Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated in any
order, but not both.
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 19
Intel® Xeon® Processor E3-1200 v3 Product Family
CH BCH A
B B
C
B
B
C
Non interleaved
access
Dual channel
interleaved access
TOM
CH A and CH B can be configured to be physical channels 0 or 1
B – The largest physical memory amount of the smaller size memory module
C – The remaining physical memory amount of the larger size memory module
Processor—Interfaces
Dual-Channel Mode – Intel® Flex Memory Technology Mode
The IMC supports Intel Flex Memory Technology Mode. Memory is divided into
symmetric and asymmetric zones. The symmetric zone starts at the lowest address in
each channel and is contiguous until the asymmetric zone begins or until the top
address of the channel with the smaller capacity is reached. In this mode, the system
runs with one zone of dual-channel mode and one zone of single-channel mode,
simultaneously, across the whole memory array.
Note: Channels A and B can be mapped for physical channel 0 and 1 respectively or vice
versa; however, channel A size must be greater or equal to channel B size.
Figure 2. Intel® Flex Memory Technology Operations
Dual-Channel Symmetric Mode
Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum
performance on real world applications. Addresses are ping-ponged between the
channels after each cache line (64-byte boundary). If there are two requests, and the
second request is to an address on the opposite channel from the first, that request
can be sent before data from the first request has returned. If two consecutive cache
lines are requested, both may be retrieved simultaneously, since they are ensured to
be on opposite channels. Use Dual-Channel Symmetric mode when both Channel A
and Channel B DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
When both channels are populated with the same memory capacity and the boundary
between the dual channel zone and the single channel zone is the top of memory, the
IMC operates completely in Dual-Channel Symmetric mode.
Note:
Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2 June 2013
20 Order No.: 328907-001
The DRAM device technology and width may vary from one channel to the other.
Interfaces—Processor
2.1.3.1 System Memory Frequency
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports one or two DIMM
connectors per channel. The usage of DIMM modules with different latencies is
allowed, but in that case, the worst latency (among two channels) will be used. For
dual-channel modes, both channels must have a DIMM connector populated and for
single-channel mode only a single-channel may have one or both DIMM connectors
populated.
2.1.3.2 Intel® Fast Memory Access (Intel® FMA) Technology Enhancements
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel FMA technology enhancements.
Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Pre-charge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back-to-back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the
IMC to further reduce latency and increase bandwidth efficiency.
2.1.3.3 Data Scrambling
The system memory controller incorporates a Data Scrambling feature to minimize the
impact of excessive di/dt on the platform system memory VRs due to successive 1s
and 0s on the data bus. Past experience has demonstrated that traffic on the data bus
is not random and can have energy concentrated at specific spectral harmonics
creating high di/dt which is generally limited by data patterns that excite resonance
between the package inductance and on die capacitances. As a result, the system
memory controller uses a data scrambling feature to create pseudo-random patterns
on the system memory data bus to reduce the impact of any excessive di/dt.
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 21
Intel® Xeon® Processor E3-1200 v3 Product Family
Processor—Interfaces
2.2 PCI Express* Interface
This section describes the PCI Express* interface capabilities of the processor. See the
PCI Express Base* Specification 3.0 for details on PCI Express*.
2.2.1 PCI Express* Support
The PCI Express* lanes (PEG[15:0] TX and RX) are fully-compliant to the PCI Express
Base Specification, Revision 3.0.
The Intel® Xeon® processor with the Server / Workstation PCH supports the
configurations shown in the following table (may vary depending on PCH SKUs).
Table 5. PCI Express* Supported Configurations in Server / Workstation Products
Configuration Essential Server Standard Server Advanced Workstation /
1x8, 2x4 I/O I/O GFX, I/O
2x8 I/O I/O GFX, I/O, Dual x8 GFX
1x16 GFX, I/O GFX, I/O GFX, I/O
Server
• The port may negotiate down to narrower widths.
— Support for x16/x8/x4/x2/x1 widths for a single PCI Express* mode.
• 2.5 GT/s, 5.0 GT/s and 8 GT/s PCI Express* bit rates are supported.
• Gen1 Raw bit-rate on the data pins of 2.5 GT/s, resulting in a real bandwidth per
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
Maximum theoretical bandwidth on the interface of 4 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when x16 Gen 1.
• Gen 2 Raw bit-rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per
pair of 500 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
Maximum theoretical bandwidth on the interface of 8 GB/s in each direction
simultaneously, for an aggregate of 16 GB/s when x16 Gen 2.
• Gen 3 raw bit-rate on the data pins of 8.0 GT/s, resulting in a real bandwidth per
pair of 984 MB/s using 128b/130b encoding to transmit data across this interface.
This also does not account for packet overhead and link maintenance. Maximum
theoretical bandwidth on the interface of 16 GB/s in each direction simultaneously,
for an aggregate of 32 GB/s when x16 Gen 3.
• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express* Enhanced Access Mechanism. Accessing the device configuration
space in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset.
Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2 June 2013
22 Order No.: 328907-001
Interfaces—Processor
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering).
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0: DMI -> PCI Express* Port 0
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status.
• PCI Express* reference clock is 100-MHz differential clock.
• Power Management Event (PME) functions.
• Dynamic width capability.
• Message Signaled Interrupt (MSI and MSI-X) messages.
• Polarity inversion
Note: The processor does not support PCI Express* Hot-Plug.
2.2.2 PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged.
The PCI Express* configuration uses standard mechanisms as defined in the PCI Plugand-Play specification. The processor PCI Express* ports support Gen 3. At 8 GT/s,
Gen 3 operation results in twice as much bandwidth per lane as compared to Gen 2
operation. The 16 lanes PEG can operate at 2.5 GT/s, 5 GT/s, or 8 GT/s.
Gen 3 PCI Express* uses a 128b/130b encoding that is about 23% more efficient than
the 8b/10b encoding used in Gen 1 and Gen 2.
The PCI Express* architecture is specified in three layers – Transaction Layer, Data
Link Layer, and Physical Layer. See the PCI Express Base Specification 3.0 for details
of PCI Express* architecture.
2.2.3
PCI Express* Configuration Mechanism
The PCI Express* (external graphics) link is mapped through a PCI-to-PCI bridge
structure.
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 23
Intel® Xeon® Processor E3-1200 v3 Product Family
Figure 3. PCI Express* Related Register Structures in the Processor
PCI-PCI
Bridge
representing
root PCI
Express ports
(Device 1 and
Device 6)
PCI
Compatible
Host Bridge
Device
(Device 0)
PCI
Express*
Device
PEG0
DMI
PCI Express* extends the configuration space to 4096 bytes per-device/function, as
compared to 256 bytes allowed by the conventional PCI specification. PCI Express*
configuration space is divided into a PCI-compatible region (that consists of the first
256 bytes of a logical device's configuration space) and an extended PCI Express*
region (that consists of the remaining configuration space). The PCI-compatible region
can be accessed using either the mechanisms defined in the PCI specification or using
the enhanced PCI Express* configuration access mechanism described in the PCI
Express* Enhanced Configuration Mechanism section.
Processor—Interfaces
The PCI Express* Host Bridge is required to translate the memory-mapped PCI
Express* configuration space accesses from the host processor to PCI Express*
configuration cycles. To maintain compatibility with PCI configuration addressing
mechanisms, it is recommended that system software access the enhanced
configuration space using 32-bit operations (32-bit aligned) only. See the PCI Express
Base Specification for details of both the PCI-compatible and PCI Express* Enhanced
configuration mechanisms and transaction rules.
PCI Express* Lanes Connection
The following figure demonstrates the PCIe* lane mapping.
Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2 June 2013
24 Order No.: 328907-001
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1 X 16
Co
ntroller
Lane 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8
Lane 9
Lane 10
Lane 11
Lane 12
Lane 13
Lane 14
Lane 15
0
1
2
3
4
5
6
7
1 X 8 Controller
0
1
2
3
1 X 4 Cont
ro
ller
Interfaces—Processor
Figure 4. PCI Express* Typical Operation 16 Lanes Mapping
2.3 Direct Media Interface (DMI)
Direct Media Interface (DMI) connects the processor and the PCH. Next generation
DMI2 is supported.
Note: Only DMI x4 configuration is supported.
• DMI 2.0 support.
• Compliant to Direct Media Interface Second Generation (DMI2).
• Four lanes in each direction.
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 25
Intel® Xeon® Processor E3-1200 v3 Product Family
Processor—Interfaces
• 5 GT/s point-to-point DMI interface to PCH is supported.
• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 2 GB/s in each direction
simultaneously, for an aggregate of 4 GB/s when DMI x4.
• Shares 100-MHz PCI Express* reference clock.
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Supports the following traffic types to or from the PCH:
— DMI -> DRAM
— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs
only)
— Processor core -> DMI
• APIC and MSI interrupt messaging support:
— Message Signaled Interrupt (MSI and MSI-X) messages
• Downstream SMI, SCI and SERR error indication.
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters.
• DC coupling – no capacitors between the processor and the PCH.
• Polarity inversion.
• PCH end-to-end lane reversal across the link.
• Supports Half Swing “low-power/low-voltage”.
DMI Error Flow
DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or
GPE. Any DMI related SERR activity is associated with Device 0.
DMI Link Down
The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to
data link down, after the link was up, then the DMI link hangs the system by not
allowing the link to retrain to prevent data corruption. This link behavior is controlled
by the PCH.
Downstream transactions that had been successfully transmitted across the link prior
to the link going down may be processed as normal. No completions from
downstream, non-posted transactions are returned upstream over the DMI link after a
link down event.
Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2 June 2013
26 Order No.: 328907-001
Interfaces—Processor
2.4 Processor Graphics
The processor graphics contains a generation 7.5 graphics core architecture. This
enables substantial gains in performance and lower power consumption over previous
generations. Up to 20 Execution Units are supported depending on the processor SKU.
• Next Generation Intel Clear Video Technology HD Support is a collection of video
playback and enhancement features that improve the end user’s viewing
experience
— Encode / transcode HD content
— Playback of high definition content including Blu-ray Disc*
— Superior image quality with sharper, more colorful images
— Playback of Blu-ray* disc S3D content using HDMI (1.4a specification
compliant with 3D)
• DirectX* Video Acceleration (DXVA) support for accelerating video processing
— Full AVC/VC1/MPEG2 HW Decode
• Advanced Scheduler 2.0, 1.0, XPDM support
• Windows* 8, Windows* 7, OSX, Linux* operating system support
• DirectX* 11.1, DirectX* 11, DirectX* 10.1, DirectX* 10, DirectX* 9 support.
• OpenGL* 4.0, support
• Switchable Graphics support on AIO platforms with MxM solutions only
2.5
Processor Graphics Controller (GT)
The New Graphics Engine Architecture includes 3D compute elements, Multi-format
HW assisted decode/encode pipeline, and Mid-Level Cache (MLC) for superior high
definition playback, video quality, and improved 3D performance and media.
The Display Engine handles delivering the pixels to the screen. GSA (Graphics in
System Agent) is the primary channel interface for display memory accesses and
“PCI-like” traffic in and out.
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 27
Intel® Xeon® Processor E3-1200 v3 Product Family
Figure 5. Processor Graphics Controller Unit Block Diagram
Processor—Interfaces
2.5.1 3D and Video Engines for Graphics Processing
The Gen 7.5 3D engine provides the following performance and power-management
enhancements.
3D Pipeline
The 3D graphics pipeline architecture simultaneously operates on different primitives
or on different portions of the same primitive. All the cores are fully programmable,
increasing the versatility of the 3D Engine.
3D Engine Execution Units
• Supports up to 20 EUs. The EUs perform 128-bit wide execution per clock.
• Support SIMD8 instructions for vertex processing and SIMD16 instructions for
pixel processing.
Vertex Fetch (VF) Stage
The VF stage executes 3DPRIMITIVE commands. Some enhancements have been
included to better support legacy D3D APIs as well as SGI OpenGL*.
Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2 June 2013
28 Order No.: 328907-001
Interfaces—Processor
Vertex Shader (VS) Stage
The VS stage performs shading of vertices output by the VF function. The VS unit
produces an output vertex reference for every input vertex reference received from
the VF unit, in the order received.
Geometry Shader (GS) Stage
The GS stage receives inputs from the VS stage. Compiled application-provided GS
programs, specifying an algorithm to convert the vertices of an input object into some
output primitives. For example, a GS shader may convert lines of a line strip into
polygons representing a corresponding segment of a blade of grass centered on the
line. Or it could use adjacency information to detect silhouette edges of triangles and
output polygons extruding out from the edges.
Clip Stage
The Clip stage performs general processing on incoming 3D objects. However, it also
includes specialized logic to perform a Clip Test function on incoming objects. The Clip
Test optimizes generalized 3D Clipping. The Clip unit examines the position of
incoming vertices, and accepts/rejects 3D objects based on its Clip algorithm.
Strips and Fans (SF) Stage
The SF stage performs setup operations required to rasterize 3D objects. The outputs
from the SF stage to the Windower stage contain implementation-specific information
required for the rasterization of objects and also supports clipping of primitives to
some extent.
Windower / IZ (WIZ) Stage
The WIZ unit performs an early depth test, which removes failing pixels and
eliminates unnecessary processing overhead.
The Windower uses the parameters provided by the SF unit in the object-specific
rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of
pixels. The Windower is also capable of performing dithering, whereby the illusion of a
higher resolution when using low-bpp channels in color buffers is possible. Color
dithering diffuses the sharp color bands seen on smooth-shaded objects.
Video Engine
The Video Engine handles the non-3D (media/video) applications. It includes support
for VLD and MPEG2 decode in hardware.
2D Engine
The 2D Engine contains BLT (Block Level Transfer) functionality and an extensive set
of 2D instructions. To take advantage of the 3D during engine’s functionality, some
BLT functions make use of the 3D renderer.
Processor Graphics VGA Registers
The 2D registers consists of original VGA registers and others to support graphics
modes that have color depths, resolutions, and hardware acceleration features that go
beyond the original VGA standard.
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 29
Intel® Xeon® Processor E3-1200 v3 Product Family
Processor—Interfaces
Logical 128-Bit Fixed BLT and 256 Fill Engine
This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The
128-bit BLT engine provides hardware acceleration of block transfers of pixel data for
many common Windows operations. The BLT engine can be used for the following:
• Move rectangular blocks of data between memory locations
• Data alignment
• To perform logical operations (raster ops)
The rectangular block of data does not change, as it is transferred between memory
locations. The allowable memory transfers are between: cacheable system memory
and frame buffer memory, frame buffer memory and frame buffer memory, and within
system memory. Data to be transferred can consist of regions of memory, patterns, or
solid color fills. A pattern is always 8 x 8 pixels wide and may be 8, 16, or 32 bits per
pixel.
The BLT engine expands monochrome data into a color depth of 8, 16, or 32 bits.
BLTs can be either opaque or transparent. Opaque transfers move the data specified
to the destination. Transparent transfers compare destination color to source color and
write according to the mode of transparency selected.
Data is horizontally and vertically aligned at the destination. If the destination for the
BLT overlaps with the source memory location, the BLT engine specifies which area in
memory to begin the BLT transfer. Hardware is included for all 256 raster operations
(source, pattern, and destination) defined by Microsoft*, including transparent BLT.
The BLT engine has instructions to invoke BLT and stretch BLT operations, permitting
software to set up instruction buffers and use batch processing. The BLT engine can
perform hardware clipping during BLTs.
2.5.2
Multi Graphics Controllers Multi-Monitor Support
The processor supports simultaneous use of the Processor Graphics Controller (GT)
and a x16 PCI Express* Graphics (PEG) device. The processor supports a maximum of
2 displays connected to the PEG card in parallel with up to 2 displays connected to the
processor and PCH.
Note: When supporting Multi Graphics Multi Monitors, "drag and drop" between monitors and
the 2x8PEG is not supported.
2.6 Digital Display Interface (DDI)
• The processor supports:
— Three Digital Display (x4 DDI) interfaces that can be configured as
DisplayPort*, HDMI*, or DVI. DisplayPort* can be configured to use 1, 2, or 4
lanes depending on the bandwidth requirements and link data rate of RBR
(1.62 GT/s), HBR (2.7 GT/s) and HBR2 (5.4 GT/s). When configured as
HDMI*, DDIx4 port can support 2.97 GT/s. In addition, Digital Port D ( x4
DDI) interface can also be configured to carry embedded DisplayPort*
(eDPx4). Built-in displays are only supported on Digital Port D.
— One dedicated Intel FDI Port for legacy VGA support on the PCH.
Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2 June 2013
30 Order No.: 328907-001
Loading...