Intel BX80638I53320M User Manual

Mobile 3rd Generation Intel® Core™ Processor Family

Specification Update

September 2013 Revision 015

Reference Number: 326770

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Intel

Turbo Boost Technology requires a system with Intel® Turbo Boost Technology. Intel Turbo Boost Technology and Intel Turbo Boost Technology

2.0 are only available on select Intel

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Intel

Hyper-Threading Technology requires an Intel® HT T echnology enabled system, check with your PC manufacturer. Performance will vary depending on the specific hardware and software used. Not available on Intel processors support HT Technology, visit http://www.intel.com/info/hyperthreading.

Intel

64 architecture requires a system with a 64-bit enab led processor, chipset, BIOS and so f tware. Per formance wil l vary depending on the specific

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2 Specification Update

Contents

Revision History...............................................................................................................5

Preface ..............................................................................................................................6

Summary Tables of Changes..........................................................................................8

Identification Information..............................................................................................14

Errata...............................................................................................................................21

Specification Changes...................................................................................................53

Specification Clarifications...........................................................................................54

Documentation Changes...............................................................................................55

§ §

Specification Update 3

Contents

4 Specification Update

Revision History

Revision Description Date

001 • Initial Release. April 2012

002

003

004 • Added Errata BU86-BU90 June 2012

005

006 • Added Errata BU91-BU94 November 2012 007 • Added Errata BU95-BU98 December 2012 008 • Documentation Change January 2013 009 • Added Errata BU99, BU100 March 2013 010 • Added Errata BU101 April 2013 011 • Added Errata BU102, BU103, BU104 May 2013

012

013 • Added Erratum BU109 July 2013 014 • Added Errata BU110, BU111 August 2013 015 • Added Errata BU112 September 2013

• Added Errata BU69–BU85

• Updated Processor Identification Table

• Added L-1 stepping to Component Identification using Programming

• Added L-1 stepping to errata summary table

• Updated Processor Identification Table

• Added Mobile 3rd Generation Intel processors

• Added Errata BU105, BU106, BU107, BU108

• Made changes to Erratum BU101

Core™ i7-3940XM, i7-3840QM, i7-3740QM

May 2012

June 2012

October 2012

June 2013

Specification Update 5

Preface

This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.

This document may also contain information that was not previously published.

Affected Documents

Mobile 3rd Generation Intel Mobile 3rd Generation Intel

Nomenclature

Errata are design defects or errors. These may cause the processor behavior to

deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics such as, core speed, L2 cache size, package type, etc. as described in the processor identification information table. Read all notes associated with each S-Spec number.

Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in any new release of the specification.

Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification.

Note: Errata remain in the specification update throughout the product’s lifecycle, or until a

particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, and so on).

Specification Update 7

Summary Tables of Changes

The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations:

Codes Used in Summary Tables

Stepping

X: Errata exists in the stepping indicated. Specification Change or

(No mark) or (Blank box): This erratum is fixed in listed stepping or specification change

Page

(Page): Page location of item in this document.

Status

Doc: Document change or update will be implemented. Plan Fix: This erratum may be fixed in a future stepping of the product. Fixed: This erratum has been previously fixed. No Fix: There are no plans to fix this erratum.

Row

Change bar to left of a table row indicates this erratum is either new or modified from the previous version of the document.

Errata (Sheet 1 of 5)

Number

BU1

BU2

BU3 BU4 BU5

BU6

Steppings

Status ERRATA

E-1 L-1

XXNo FixThe Processor May Report a #TS Instead of a #GP Fault

XXNo Fix

XXNo FixIO_SMI Indication in SMRAM State Save Area May be Set Incorrectly XXNo FixPerformance Monitor SSE Retired Instructions May Return Incorrect Values XXNo FixIRET under Certain Conditions May Cause an Unexpected Alignment Check Exception

XXNo Fix

Clarification that applies to this stepping.

does not apply to listed stepping.

REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to MemoryOrdering Violations.

Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions

8 Specification Update

Errata (Sheet 2 of 5)

Number

BU7

BU8

BU9

BU10

BU11

BU12 BU13 BU14 BU15 BU16 BU17 BU18 BU19

BU20

BU21

BU22

BU23

BU24

BU25

BU26

BU27

BU28

BU29

BU30

BU31

BU32

BU33

Steppings

E-1 L-1

XXNo Fix

Status ERRATA

General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted

LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode

Incorrect Address Computed For Last Byte of FXSAVE/FXRST OR or XSAVE/XRSTOR Image Leads to Partial Memory Update

XXNo FixValues for LBR/BTS/BTM Will be Incorrect after an Exit from SMM XXNo Fix

EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a T ranslation

Change

XXNo FixB0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set XXNo FixMCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error XXNo FixDebug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints XXNo FixLER MSRs May Be Unreliable XXNo FixStorage of PEBS Record Delayed Following Execution of MOV SS or STI XXNo FixPEBS Record not Updated when in Probe Mode XXNo FixMONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang XXNo FixFaulting MMX Instruction May Incorrectly Update x87 FPU Tag Word

XXNo Fix

An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a

System Hang

#GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not

Provide Correct Exception Error Code

DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is

Followed by a Store or an MMX Instruction

XXNo FixAPIC Error “Received Illegal Vector” May be Lost XXNo Fix

XXNo Fix

Changing the Memory Type for an In-Use Page Translation May Lead to Memory-

Ordering Violations

Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data

Structures

LBR, BTM or BTS Records May have Incorrect Branch From Information After an EIST/

T-state/S-state/C1E Transition or Adaptive Thermal Throttling

Fault Not Reported When Setting Reserved Bits of Intel® VT-d Queued Invalidation

Descriptors

FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which

Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode

VMREAD/VMWRITE Instruction May Not Fail When Accessing an Unsupported Field in

VMCS

XXNo FixSpurious Interrupts May be Generated From the Intel® VT-d Remap Engine XXNo Fix

XXNo Fix

Malformed PCIe Transactions May be Treated as Unsupported Requests Instead of as

Critical Errors

Reception of Certain Malformed Transactions May Cause PCIe Port to Hang Rather

Than Reporting an Error

XXNo FixClock Modulation Duty Cycle Cannot be Programmed to 6.25%

Specification Update 9

Errata (Sheet 3 of 5)

Number

BU34 BU35

BU36

BU37 BU38

BU39

BU40 BU41

BU42

BU43 BU44

BU45

BU46

BU47

BU48

BU49

BU50

BU51 BU52 BU53 BU54

BU55

BU56 BU57

BU58

BU59

BU60

BU61

BU62

Steppings

E-1 L-1

Status ERRATA

XXNo FixProcessor May Fail to Acknowledge a TLP Request XXNo FixAn Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2

XXNo Fix

A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain

Conditions

XXNo FixPCIe* LTR Incorrectly Reported as Being Supported XXNo FixPerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred

XXNo Fix

#GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch

Instructions

XXNo FixInterrupt From Local APIC Timer May Not Be Detectable While Being Delivered XXNo FixPCI Express* Differential Peak-Peak Tx Voltage Swing May Violate the Specification

XXNo Fix

PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate with

32-bit Length Registers

XXNo FixMultiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter 0 XXNo FixIA32_FEATURE_CONTROL MSR May be Uninitialized on a Cold Reset

XXNo Fix

DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is

Followed by a REP MOVSB or STOSB

Setting Hardware Autonomous Speed Disable Configuration Bit Will Block Initial Speed

Upgrade

XXNo FixLTR Message is Not Treated as an Unsupported Request XXNo Fix

XXNo Fix

64-bit REP MOVSB/STOSB May Clear The Upper 32-bits of RCX, RDI And RSI Before

Any Data is Transferred

An Interrupt Recognized Prior to First Iteration of REP MOVSB/STOSB May Result

EFLAGS.RF Being Incorrectly Set

Accessing Physical Memory Space 0-640K through the Graphics Aperture May Cause

Unpredictable System Behavior

XXNo FixPEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full XXNo FixInstructions Retired Event May Over Count Execution of IRET Instructions XXNo FixPCIe* Link May Unexpectedly Exit Loopback State XXNo FixThe RDRAND Instruction Will Not Execute as Expected

XXNo Fix

A PCIe* Device That Initially Transmits Minimal Posted Data Credits May Cause a

System Hang

XXNo FixPCI Express* Gen3 Receiver Return Loss May Exceed Specifications XXNo FixDirect Access Via VT-d to The Processor Graphics Device May Lead to a System Hang

XXNo Fix

An Event May Intervene Before a System Management Interrupt That Results from IN

or INS

PCIe* May Associate Lanes That Are Not Part of Initial Link Training to L0 During

Upconfiguration

The Processor May Not Comply With PCIe* Equalization Preset Reflection

Requirements for 8 GT/s Mode of Operation

XXNo FixProcessor May Issue PCIe* EIEOS at Incorrect Rate XXNo Fix

Reduced Swing Output Mode Needs Zero De-emphasis to be Supported in PCIe* 5GT/

s Speed

10 Specification Update

Errata (Sheet 4 of 5)

Number

BU63

BU64

BU65

BU66 BU67 BU68 BU69

BU70

BU71 BU72 BU73

BU74

BU75

BU76

BU77 BU78 BU79

BU80 X X No Fix BU81 X X No Fix BU82 X X No Fix BU83 X X No Fix

BU84 X X No Fix

Steppings

E-1 L-1

XXNo Fix

Status ERRATA

PCIe* Root-port Initiated Compliance State Transmitter Equalization Settings May be Incorrect

XXNo FixPCIe* Controller May Incorrectly Log Errors on Transition to RxL0s XXNo Fix

Reception of Certain Malformed Transactions May Cause PCIe* Port to Hang Rather

Than Reporting an Error

XXNo FixPCIe* Link Width May Degrade After a Warm Reset XXNo FixMSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate XXNo FixExecution of Package C7 May Result in a Hang XXNo FixPCIe* Link May Not Enter Loopback.Active When Directed

XXNo Fix

Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for VEX.vvvv

May Produce a #NM Exception

XXNo FixUnexpected #UD on VZEROALL/VZEROUPPER XXNo FixPCIe* Root Port May Not Initiate Link Speed Change XXNo FixSuccessive Fixed Counter Overflows May be Discarded

XXNo Fix

Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM

Exception

VM Exits Due to “NMI-Window Exiting” May Not Occur Following a VM Entry to the

Shutdown State

Execution of INVVPID Outside 64-Bit Mode Cannot Invalidate Translations For 64-Bit

Linear Addresses

XXNo FixPCIe* Controller May Not Properly Indicate Link Electrical Idle Condition XXNo FixPCIe* Controller May Not Enter Loopback XXNo FixLink Margin Characterization May Hang Link

Unused PCIe* Lanes May Report Correctable Errors

RDMSR of IA32_PERFEVTSEL{4-7} May Return Erroneous Information

PCIe* Link May Fail Link Width Upconfiguration

Graphics L3 Cache Parity Errors May Not be Detected

A PCIe* Link That is in Link Disable State May Prevent DDR I/O Buffers From Entering

a Power Gated State

BU85 X X No Fix Graphics L3 Cache Redundancy May Not Behave as Expected BU86 X X No Fix REP MOVSB May Incorrectly Update ECX, ESI, and EDI BU87 X X No Fix Performance-Counter Overflow Indication May Cause Undesired Behavior BU88 X X No Fix RDMSR of IA32_PERFEVTSEL4-7 May Return an Incorrect Result BU89 X XX No Fix VEX.L is Not Ignored with VCVT*2SI Instructions

BU90 X X No Fix

Intel® Turbo Boost Technology May be Incorrectly Reported as Supported on Intel®

Core™ i3-3217U

BU91 X X No Fix Concurrently Changing the Memory Type and Page Size May Lead to a System Hang BU92 X X No Fix MCI_ADDR May be Incorrect For Cache Parity Errors

BU93 X X No Fix

During Package Power States Repeated PCIe* and/or DMI L1 T ransitions May Cause a

System Hang

Specification Update 11

Errata (Sheet 5 of 5)

Number

BU94 X X No Fix BU95 X X No Fix The Processor May Not Properly Execute Code Modified Using A Floating-Point Store

BU96 X X No Fix Execution of GETSEC[SEXIT] May Cause a Debug Exception to be Lost BU97 X X No Fix

BU98 X X No Fix

BU99 X X No Fix IA32_MC5_CTL2 is Not Cleared by a Warm Reset BU100 X X No Fix BU101 X X No Fix Performance Monitor Counters May Produce Incorrect Results BU102 X X No Fix BU103 X X No Fix Spurious VT-d Interrupts May Occur When the PFO Bit is Set

BU104 X X No Fix Processor May Livelock During On Demand Clock Modulation BU105 X X No Fix BU106 X X No Fix The Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging

BU107 X X No Fix EPT Violations May Report Bits 11:0 of Guest Linear Address Incorr ectly BU108 X X No Fix

BU109 X X No Fix

BU110 X X No Fix Intel® Trusted Execution Technology ACM Authentication Failure BU111 X X No Fix Virtual-APIC Page Accesses With 32-Bit PAE Paging May Cause a System Crash

BU112 X X No Fix

Steppings

Status ERRATA

E-1 L-1

Instruction Fetches Page-Table Walks May be Made Speculatively to Uncacheable Memory

VM Exits Due to GETSEC May Save an Incorrect Value for “Blocking by STI” in the Context of Probe-Mode Redirection

Specific Graphics Blitter Instructions May Result in Unpredictable Graphics Controller Behavior

CPUID Instruction May Not Report the Processor Number in the Brand String for Intel® Core™ i3-3227U and i5-3337U Processors.

The Corrected Error Count Overflow Bit in IA32_ MC0_STA TUS is Not Updated After a UC Error is Logged

IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report The Highest Index Value Used For VMCS Encoding

DMA Remapping Faults for the Graphics VT-d Unit May Not Properly Report Type of Faulted Request

Address Translation Faults for Intel® VT-d May Not be Reported for Display Engine Memory Accesses

Specification Changes

Number SPECIFICATION CHANGES

None for this revision of this specification update.

Specification Clarifications

Number SPECIFICATION CLARIFICATIO NS

None for this revision of this specification update.

Documentation Changes

Number DOCUMENTATION CHANGES

BU1

12 Specification Update

On-Demand Clock Modulation Feature Clarification

§ §

Specification Update 13

Identification Information

Component Identification using Programming Interface

The processor stepping can be identified by the following register contents:

Extended

Model

Reserved

31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0

Notes:

1. The Extended F amily , bits [27:20] are used in con junction with the F amily Code, specif ied in bits [11:8],

2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are

3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM

4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX

5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX

6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Table 1 for the processor

Extended

Family

00000000b 0011b 00b 0110 1010b xxxxb

to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4,

or Intel used to identify the model of the processor within the processor’s family. processor, an OverDrive processor, or a dual processor (capable of being used in a dual processor

system). register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of

the Device ID register accessible through Boundary Scan. register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the

Device ID register accessible through Boundary Scan. stepping ID number in the CPUID information.

Core™ processor family.

Processor

Type

Family

Code

Model

Number

Stepping

When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family C ode, Mode l Number and Step ping ID

value in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.

The processor can be identified by the following register contents:

Stepping Vendor ID

E-1 8086h 0154h 0166h 09h L-1 8086h 0154h 0166h 09h

Notes:

1. The Vendor ID corresponds to bits 15:0 of the Vendor ID Register located at offset 00h–01h in the PCI

2. The Host Device ID corresponds to bits 15:0 of the Device ID Register located at Device 0 offset 02h–

3. The Processor Graphics Device ID (DID2) corresponds to bits 15:0 of the Device ID Register located at

4. The Revision Number corre sponds to bits 7:0 of the Re vision ID Register located at offset 08h in the PCI

14 Specification Update

function 0 configuration space. 03h in the PCI function 0 configuration space. Device 2 offset 02h–03h in the PCI function 0 configuration space. function 0 configuration space.

Host Device ID

Processor Graphics

Device ID

Revision ID

Component Marking Information

The processor stepping can be identified by the following component markings.

Table 1. Processor Identification (Sheet 1 of 6)

Core Frequency

Number

SR0T2 i7-3920XM E-1 000306A9h 2.9 / 1600 / 650

SR0MJ i7-3820QM E-1 000306A9h 2.7 / 1600 / 650

SR0MK i7-3820QM E-1 000306A9h 2.7 / 1600 / 650

SR0ML i7-3720QM E-1 000306A9h 2.6 / 1600 / 650

SR0MM i7-3720QM E-1 000306A9h 2.6 / 1600 / 650

SR0MN i7-3610QM E-1 000306A9h 2.3 / 1600 / 650

SR0MP i7-3615QM E-1 000306A9h 2.3 / 1600 / 650

SR0MQ i7-3612QM E-1 000306A9h 2.1 / 1600 / 650

SR0MR i7-3612QM E-1 000306A9h 2.1 / 1600 / 650

SR0MT i7-3520M L-1 000306A9h 2.9 / 1600 / 650

SR0MU i7-3520 M L-1 000306A9h 2.9 / 1600 / 650

SR0MV i5-3360M L-1 000306A9h 2.8 / 1600 / 650

SR0MW i5-3360M L-1 000306A9h 2.8 / 1600 / 650

Processor

Number

Stepping

Processor Signature

(GHz) /

DDR3 (MHz) /

Processor

Graphics

Frequency

Max Intel

Turbo Boost

Technology

2.0 Frequency (GHz)

3/4 core: 3.6

2 core: 3.7 1 core: 3.8

3/4 core: 3.5

2 core: 3.6 1 core: 3.7

3/4 core: 3.5

2 core: 3.6 1 core: 3.7

3/4 core: 3.4

2 core: 3.5 1 core: 3.6

3/4 core: 3.4

2 core: 3.5 1 core: 3.6

3/4 core: 3.1

2 core: 3.2 1 core: 3.3

3/4 core: 3.1

2 core: 3.2 1 core: 3.3

3/4 core: 2.8

2 core: 3

1 core: 3.1

3/4 core: 2.8

2 core: 3

1 core: 3.1

4 core: 0

3 core: 0 2 core: 3.4 1 core: 3.6

4 core: 0

3 core: 0 2 core: 3.4 1 core: 3.6

4 core: 0

3 core: 0 2 core: 3.3 1 core: 3.5

4 core: 0

3 core: 0 2 core: 3.3 1 core: 3.5

Shared

L3 Cache

Size (MB)

8 2,3,4,5,6

6 2,3,4,5,6

6 2,4,6

6 2,4,5,6

6 2,4,6

6 2,4,5,6

4 2,3,4,5,6

3 2,3,4,5,6

Notes

Specification Update 15

Table 1. Processor Identification (Sheet 2 of 6)

Core Frequency

(GHz) /

DDR3 (MHz) /

Processor

Graphics

Frequency

Number

Processor

Number

Stepping

Processor Signature

SR0MX i5-3320M L-1 000306A9h 2.6 / 1600 / 650

SR0MY i5-3320M L-1 000306A9h 2.6 / 1600 / 650

SR0MZ i5-3210M L-1 000306A9h 2.5 / 1600 / 650

SR0N0 i5-3210M L-1 000306A9h 2.5 / 1600 / 650

SR0N1 i3-3110M L-1 000306A9h 2.4 / 1600 / 650

SR0N2 i3-3110M L-1 000306A9h 2.4 / 1600 / 650

SR0N5 i7-3667U L-1 000306A9h 2 / 1600 / 350

SR0N6 i7-3517U L-1 000306A9h 1.9 / 1600 / 350

SR0N7 i5-3427U L-1 000306A9h 1.8 / 1600 / 350

SR0N8 i5-3317U L-1 000306A9h 1.7 / 1600 / 350

SR0N9 i3-3217U L-1 000306A9h 1.8 / 1600 / 350

SR0X6 i7-3540M L-1 000306A9h 3.0 / 1600 / 1300

SR0X8 i7-3540M L-1 000306A9h 3.0 / 1600 / 1300

(GHz)

Max Intel Turbo Boost Technology

2.0 Frequency

4 core: 0

3 core: 0 2 core: 3.1 1 core: 3.3

4 core: 0

3 core: 0 2 core: 3.1 1 core: 3.3

4 core: 0

3 core: 0 2 core: 2.9 1 core: 3.1

4 core: 0

3 core: 0 2 core: 2.9 1 core: 3.1

4 core: 0

3 core: 0

2 core: 0 1 core: 2.4

4 core: 0

3 core: 0

2 core: 0 1 core: 2.4

4 core: 0

3 core: 0

2 core: 3 1 core: 3.2

4 core: 0

3 core: 0 2 core: 2.8

1 core: 3

4 core: 0

3 core: 0 2 core: 2.6 1 core: 2.8

4 core: 0

3 core: 0 2 core: 2.4 1 core: 2.6

4 core: 0

3 core: 0

2 core: 0

1 core: 0 2 core: 3.5

1 core: 3.7 2 core: 3.5

1 core: 3.7

Shared

L3 Cache

Notes

Size (MB)

3 2,3,4,5,6

32,4,6

3 2,4,5,6

32,4

4 2,3,4,5,6

4 2,4,5,6

3 2,3,4,5,6

3 2,4,5,6

32,4

4 2,3,4,5,6

16 Specification Update

Table 1. Processor Identification (Sheet 3 of 6)

Core Frequency

Number

SR0X7 i5-3380 M L-1 000306A9h 2.9 /1600 /650

SR0X9 i5-3380 M L-1 000306A9h 2.9 /1600 /650

SR0XA i5-3340M L-1 000306A9h 2.7 / 1600 /650

SR0XB i5-3340M L-1 000306A9h 2.7 / 1600 /650

SR0WY i5-3230M L-1 000306A9h 2.6 / 1600 / 650

SR0WX i5-3230M L-1 000306A9h 2.6 / 1600 / 650

SR0XD i3-3130M L-1 000306A9h 2.6 / 1600 / 650

SR0XC i3-3130M L-1 000306A9h 2.6 / 1600 / 650

SR0XH i7-3687U L-1 000306A9h 2.1 /1600 /350

SR0XG i7-3537U L-1 000306A9h 2 / 1600/ 350

SR0XE i5-3437U L-1 000306A9h 1.9 / 1600 / 350

SR0XL i5-3337U L-1 000306A9h 1.8 / 1600 / 350

SR0XF i3-3227U L-1 000306A9h 1.9 / 1600 / 350

Processor

Number

Stepping

Processor Signature

SR0US i7-3940XM E-1 000306A9h 3.0 / 1200 / 650

SR0UT i7-3840QM E-1 000306A9h 2.8 / 1200 / 650

SR0UV i7-3740QM E-1 000306A9h 2.7 / 1200 / 650

SR12R i7-3689Y L-1 000306A9h 1.5 /1600/ 350

SR0ZP i7-3689Y L-1 000306A9h 1.5 /1600/ 350

SR12Q i5-3439Y L-1 000306A9h 1.5 /1600/ 350

(GHz) /

DDR3 (MHz) /

Processor

Graphics

Frequency

Max Intel

Turbo Boost

Technology

2.0 Frequency

(GHz)

2 core: 3.4 1 core: 3.6

2 core: 3.2 1 core: 3.4

2 core: 3.0 1 core: 3.2

2 core:

1 core: 2.6

2 core:

1 core: 2.6 2 core: 3.1

1 core: 3.3 2 core: 2.9

1 core: 3.1 2 core: 2.7

1 core: 2.9 2 core: 2.5

1 core: 2.7

2 core: N/A

1 core: 1.9

4 core: 3.7 3 core: 3.8 2 core: 3.9 1 core: 3.9

4 core: 3.6 3 core: 3.7 2 core: 3.8 1 core: 3.8

4 core: 3.5 3 core: 3.6 2 core: 3.7 1 core: 3.7

2 core: N/A

1 core: 2.6

2 core: N/A

1 core: 2.6

2 core: N/A

1 core: 2.3

Shared

L3 Cache

Size (MB)

3 2,3,4,5,6

3 2,4,5,6

32,4

4 2,3,4,5,6

4 2,4,5,6

3 2,3,4,5,6

3 2,4,5,6

3 2,4,7

Notes

8 1,2,3,4,5,6

6 1,2,3,4,5,6

4 2,3,4,5,6

3 2,3,4,5,6

Specification Update 17

+ 39 hidden pages

Intel BX80638I53320M User Manual

Mobile 3rd Generation Intel® Core™ Processor Family

Revision History

Preface

Affected Documents

Related Documents

Nomenclature

Summary Tables of Changes

Codes Used in Summary Tables

Errata (Sheet 1 of 5)

Specification Clarifications

Documentation Changes

Identification Information

Component Identification using Programming Interface

Component Marking Information