Intel BX80637I53350P User Manual

Desktop 3rd Generation Intel® Core™ Processor Family

Specification Update

September 2013 Revision 015

Reference Number: 326766

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Intel

Turbo Boost Technology requires a system with Intel® Turbo Boost Technology. Intel Turbo Boost Technology and Intel Turbo Boost Technology

2.0 are only available on select Intel

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Intel

Hyper-Threading Technology requires an Intel® HT T echnology enabled system, check with your PC manufacturer. Performance will vary depending on the specific hardware and software used. Not available on Intel processors support HT Technology, visit http://www.intel.com/info/hyperthreading.

Intel

64 architecture requires a system with a 64-bit enab led processor, chipset, BIOS and so f tware. Per formance wil l vary depending on the specific

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2 Specification Update

Contents

Revision History...............................................................................................................5

Preface ..............................................................................................................................6

Summary Tables of Changes..........................................................................................8

Identification Information..............................................................................................14

Errata...............................................................................................................................21

Specification Changes...................................................................................................53

Specification Clarifications...........................................................................................54

Documentation Changes...............................................................................................55

§ §

Specification Update 3

Contents

4 Specification Update

Revision History

Revision Description Date

001 • Initial Release. April 2012

002

003

004 • Added errata BV84-BV87 June 2012

005

006 • Added errata BV88-BV91 November 2012 007 • Added errata BV92-BV95 December 2012 008 • Documentation Change January 2013 009 • Added Errata BV96, BV97 March 2013

010

011 • Added Errata BV99, BV100, BV101 May 2013

012

013 • Added Erratum BV106 July 2013 014 • Added Erratum BV107, BV108 August 2013 015 • Added Erratum BV109 September 2013

• Added Errata BV68–BV83

• Updated Processor Identification Table

• Added L-1 and N-0 steppings to errata summary table

• Added L-1 and N-0 steppings to Component Identification using Programming Interface table

• Updated Processor Identification Table

• Added Intel Pentium G2120 and G2100T Processors

• Added Desktop 3rd Generation Intel Core i3-3220,i3-3220T,i3-3225,i3-3240,i33240T,i5-3330,i5-3330S,i5-3330P processors

•Added Errata BV98

• Updated the SKU table

• Added Errata BV102, BV103, BV104, BV105

• Made changes to Erratum BV98

• Added new SKU’s to SKU table

October 2012

May 2012

June 2012

April 2013

June 2013

Specification Update 5

Preface

This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.

This document may also contain information that was not previously published.

Affected Documents

Desktop 3rd Generation Intel Desktop 3rd Generation Intel

Nomenclature

Errata are design defects or errors. These may cause the processor behavior to

deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics such as, core speed, L2 cache size, package type, etc. as described in the processor identification information table. Read all notes associated with each S-Spec number.

Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in any new release of the specification.

Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification.

Note: Errata remain in the specification update throughout the product’s lifecycle, or until a

particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, and so on).

Specification Update 7

Summary Tables of Changes

The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations:

Codes Used in Summary Tables

Stepping

X: Errata exists in the stepping indicated. Specification Change or

(No mark) or (Blank box): This erratum is fixed in listed stepping or specification change

Page

(Page): Page location of item in this document.

Status

Doc: Document change or update will be implemented. Plan Fix: This erratum may be fixed in a future stepping of the product. Fixed: This erratum has been previously fixed. No Fix: There are no plans to fix this erratum.

Row

Change bar to left of a table row indicates this erratum is either new or modified from the previous version of the document.

Errata (Sheet 1 of 5)

Number

BV1

BV2

BV3 BV4

BV5

BV6

Steppings

Status ERRATA

E-1 L-1 N-0

XXXNo FixThe Processor May Report a #TS Instead of a #GP Fault

XXXNo Fix

XXXNo FixIO_SMI Indication in SMRAM State Save Area May be Set Incorrectly XXXNo FixPerformance Monitor SSE Retired Instructions May Return Incorrect Values

XXXNo Fix

Clarification that applies to this stepping.

does not apply to listed stepping.

REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations.

IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception

Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions

8 Specification Update

Errata (Sheet 2 of 5)

Number

BV7

BV8

BV9

BV10

BV11

BV12

BV13

BV14

BV15 BV16 BV17 BV18 BV19

BV20

BV21

BV22

BV23

BV24

BV25

BV26

BV27

BV28

BV29

BV30

BV31

BV32

Steppings

E-1 L-1 N-0

XXXNo Fix

Status ERRATA

General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted

LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode

Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR or XSAVE/ XRSTOR Image Leads to Partial Memory Update

XXXNo FixValues for LBR/BTS/BTM Will be Incorrect after an Exit from SMM XXXNo Fix

EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change

XXXNo FixB0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set XXXNo Fix

XXXNo Fix

MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error

Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled

Breakpoints

XXXNo FixLER MSRs May Be Unreliable XXXNo FixStorage of PEBS Record Delayed Following Execution of MOV SS or STI XXXNo FixPEBS Record not Updated when in Probe Mode XXXNo FixMONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang XXXNo FixFaulting MMX Instruction May Incorrectly Update x87 FPU Tag Word

XXXNo Fix

An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a

System Hang

#GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not

Provide Correct Exception Error Code

DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is

Followed by a Store or an MMX Instruction

XXXNo FixAPIC Error “Received Illegal Vector” May be Lost XXXNo Fix

XXXNo Fix

Changing the Memory Type for an In-Use Page Translation May Lead to Memory-

Ordering Violations

Reported Memory Type May Not Be Used to Access the VMCS and Referenced

Data Structures

LBR, BTM or BTS Records May have Incorrect Branch From Information After an

EIST/T-state/S-state/C1E Transition or Adaptive Thermal Throttling

Fault Not Reported When Setting Reserved Bits of Intel® VT-d Queued Invalidation

Descriptors

FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which

Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode

VMREAD/VMWRITE Instruction May Not Fail When Accessing an Unsupported

Field in VMCS

XXXNo FixSpurious Interrupts May be Generated From the Intel® VT-d Remap Engine XXXNo Fix

XXXNo Fix

Malformed PCIe Transactions May be Treated as Unsupported Requests Instead of

as Critical Errors

Reception of Certain Malformed Transactions May Cause PCIe Port to Hang

Rather Than Reporting an Error

Specification Update 9

Errata (Sheet 3 of 5)

Number

BV33 BV34 BV35

BV36

BV37

BV38

BV39

BV40

BV41

BV42

BV43

BV44

BV45

BV46

BV47

BV48

BV49

BV50

BV51 BV52 BV53 BV54

BV55

BV56

BV57

BV58

BV59

Steppings

E-1 L-1 N-0

Status ERRATA

XXXNo FixClock Modulation Duty Cycle Cannot be Programmed to 6.25% XXXNo FixProcessor May Fail to Acknowledge a TLP Request XXXNo FixAn Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2

XXXNo Fix

A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain Conditions

XXXNo FixPCIe* LTR Incorrectly Reported as Being Supported XXXNo Fix

XXXNo Fix

PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred

#GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch Instructions

XXXNo FixInterrupt From Local APIC Timer May Not Be Detectable While Being Delivered XXXNo Fix

XXXNo Fix

PCI Express* Differential Peak-Peak Tx Voltage Swing May Violate the Specification

PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate with 32-bit Length Registers

Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter 0

XXXNo FixIA32_FEATURE_CONTROL MSR May be Uninitialized on a Cold Reset XXXNo Fix

XXXNo Fix

DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is Followed by a REP MOVSB or STOSB

Setting Hardware Autonomous Speed Disable Configuration Bit Will Block Initial Speed Upgrade

XXXNo FixLTR Message is Not Treated as an Unsupported Request XXXNo Fix

XXXNo Fix

64-bit REP MOVSB/STOSB May Clear The Upper 32-bits of RCX, RDI And RSI Before Any Data is Transferred

An Interrupt Recognized Prior to First Iteration of REP MOVSB/STOSB May Result EFLAGS.RF Being Incorrectly Set

Accessing Physical Memory Space 0-640K through the Graphics Aperture May

Cause Unpredictable System Behavior

XXXNo FixPEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full XXXNo FixInstructions Retired Event May Over Count Execution of IRET Instructions XXXNo FixPCIe* Link May Unexpectedly Exit Loopback State XXXNo FixThe RDRAND Instruction Will Not Execute as Expected

XXXNo Fix

A PCIe* Device That Initially Transmits Minimal Posted Data Credits May Cause a

System Hang

XXXNo FixPCI Express* Gen3 Receiver Return Loss May Exceed Specifications XXXNo Fix

XXXNo Fix

Direct Access Via VT-d to The Processor Graphics Device May Lead to a System

Hang

An Event May Intervene Before a System Management Interrupt That Results from

IN or INS

PCIe* May Associate Lanes That Are Not Part of Initial Link Training to L0 During

Upconfiguration

10 Specification Update

Errata (Sheet 4 of 5)

Number

BV60

BV61

BV62

BV63

BV64

BV65

BV66 BV67 BV68

BV69

BV70 BV71 BV72

BV73

BV74

BV75

BV76 BV77 BV78 BV79 BV80 BV81 BV82

BV83

BV84 BV85 BV86 BV87

BV88

BV89

Steppings

E-1 L-1 N-0

XXXNo Fix

Status ERRATA

The Processor May Not Comply With PCIe* Equalization Preset Reflection Requirements for 8 GT/s Mode of Operation

XXXNo FixProcessor May Issue PCIe* EIEOS at Incorrect Rate XXXNo Fix

XXXNo Fix

Reduced Swing Output Mode Needs Zero De-emphasis to be Supported in PCIe* 5GT/s Speed

PCIe* Root-port Initiated Compliance State Transmitter Equalization Settings May be Incorrect

XXXNo FixPCIe* Controller May Incorrectly Log Errors on Transition to RxL0s XXXNo Fix

Reception of Certain Malformed Transactions May Cause PCIe* Port to Hang

Rather Than Reporting an Error

XXXNo FixPCIe* Link Width May Degrade After a Warm Reset XXXNo FixMSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate XXXNo FixPCIe* Link May Not Enter Loopback.Active When Directed

XXXNo Fix

Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for

VEX.vvvv May Produce a #NM Exception

XXXNo FixUnexpected #UD on VZEROALL/VZEROUPPER XXXNo FixPCIe* Root Port May Not Initiate Link Speed Change XXXNo FixSuccessive Fixed Counter Overflows May be Discarded

XXXNo Fix

Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM

Exception

VM Exits Due to “NMI-Window Exiting” May Not Occur Following a VM Entry to the

Shutdown State

Execution of INVVPID Outside 64-Bit Mode Cannot Invalidate Translations For 64-

Bit Linear Addresses

XXXNo FixPCIe* Controller May Not Properly Indicate Link Electrical Idle Condition XXXNo FixPCIe* Controller May Not Enter Loopback XXXNo FixLink Margin Characterization May Hang Link XXXNo FixUnused PCIe* Lanes May Report Correctable Errors XXXNo FixRDMSR of IA32_PERFEVTSEL{4-7} May Return Erroneous Information XXXNo FixPCIe* Link May Fail Link Width Upconfiguration XXXNo FixGraphics L3 Cache Parity Errors May Not be Detected

XXXNo Fix

A PCIe* Link That is in Link Disable State May Prevent DDR I/O Buffers From

Entering a Power Gated State

XXXNo FixREP MOVSB May Incorrectly Update ECX, ESI, and EDI XXXNo FixPerformance-Counter Overflow Indication May Cause Undesired Behavior XXXNo FixRDMSR of IA32_PERFEVTSEL4-7 May Return an Incorrect Result XXXNo FixVEX.L is Not Ignored with VCVT*2SI Instructions

XXXNo Fix

Concurrently Changing the Memory Type and Page Size May Lead to a System

Hang

XXXNo FixMCI_ADDR May be Incorrect For Cache Parity Errors

Specification Update 11

Errata (Sheet 5 of 5)

Number

BV90

BV91

BV92

BV93

BV94

BV95

BV96

BV97

BV98

BV99

BV100 BV101

BV102

BV103 BV104

BV105

BV106

BV107 BV108

BV109

Steppings

E-1 L-1 N-0

XXXNo Fix

Status ERRATA

During Package Power States Repeated PCIe* and/or DMI L1 Transitions May Cause a System

Instruction Fetches Page-Table Walks May be Made Speculatively to Uncacheable Memory

The Processor May Not Properly Execute Code Modified Using A Floating-Point Store

XXXNo FixExecution of GETSEC[SEXIT] May Cause a Debug Exception to be Lost XXXNo Fix

XXXNo Fix

VM Exits Due to GETSEC May Save an Incorrect Value for “Blocking by STI” in the Context of Probe-Mode Redirection

Specific Graphics Blitter Instructions May Result in Unpredictable Graphics Controller Behavior

XXXNo FixIA32_MC5_CTL2 is Not Cleared by a Warm Reset XXXNO Fix

CPUID Instruction May Not Report the Processor Number in the Brand String for Intel® Core™ i3-3227U and i5-3337U Processors.

XXXNo FixPerformance Monitor Counters May Produce Incorrect Results XXXNo Fix

The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated

After a UC Error is Logged

XXXNo FixSpurious VT-d Interrupts May Occur When the PFO Bit is Set XXXNo FixProcessor May Livelock During On Demand Clock Modulation

XXXNo Fix

IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report The Highest

Index Value Used For VMCS Encoding

XXXNo FixThe Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging XXXNo FixEPT Violations May Report Bits 11:0 of Guest Linear Address Incorrectly

XXXNo Fix

IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report The Highest

Index Value Used For VMCS Encoding

DMA Remapping Faults for the Graphics VT-d Unit May Not Properly Report Type

of Faulted Request

XXXNo FixIntel® Trusted Execution Technology ACM Authentication Failure XXXNo FixVirtual-APIC Page Accesses With 32-Bit PAE Paging May Cause a System Crash

XXXNo Fix

Address Translation Faults for Intel® VT -d May Not be Reported for Display Engine

Memory Accesses

Specification Changes

Number SPECIFICATION CHANGES

None for this revision of this specification update.

Specification Clarifications

Number SPECIFICATION CLARIFICATIONS

None for this revision of this specification update.

12 Specification Update

Documentation Changes

Number DOCUMENTATION CHANGES

BU1

On-Demand Clock Modulation Feature Clarification

§ §

Specification Update 13

Identification Information

Component Identification using Programming Interface

The processor stepping can be identified by the following register contents:

Extended

Model

Reserved

31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0

Notes:

1. The Extended Family , bits [27:20] are used in con junction with the F amily Code, specif ied in bits [11:8],

2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are

3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM

4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX

5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX

6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Table 1 for the processor

Extended

Family

00000000b 0011b 00b 0110 1010b xxxxb

to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4,

or Intel used to identify the model of the processor within the processor’s family. processor, an OverDrive processor, or a dual processor (capable of being used in a dual processor

system). register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of

the Device ID register accessible through Boundary Scan. register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the

Device ID register accessible through Boundary Scan. stepping ID number in the CPUID information.

Core™ processor family.

Processor

Type

Family

Code

Model

Number

Stepping

When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family C ode, Mode l Number and Step ping ID

value in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.

The processor can be identified by the following register contents:

Stepping Vendor ID

E-1 8086h 0150h 0162h 09h L-1 8086h 0150h 0162h 09h N-0 8086h 0150h 0152h 09h

Notes:

1. The Vendor ID corresponds to bits 15:0 of the Vendor ID Register located at offset 00h–01h in the PCI

2. The Host Device ID corresponds to bits 15:0 of the Device ID Register located at Device 0 offset 02h–

3. The Processor Graphics Device ID (DID2) corresponds to bits 15:0 of the Device ID Register located at

4. The Revision Number corresponds to bits 7:0 of the Re vision ID Register located at offset 08h in the PCI

14 Specification Update

function 0 configuration space. 03h in the PCI function 0 configuration space. Device 2 offset 02h–03h in the PCI function 0 configuration space. function 0 configuration space.

Host Device ID

Processor Graphics

Device ID

Revision ID

LOT NO S/N

Component Marking Information

The processor stepping can be identified by the following component markings.

Figure 1. Processor Production Top-side Markings (Example)

Table 1. Processor Identification (Sheet 1 of 6)

Number

SR0PQ i7-3770T E-1 000306A9h 2.5 / 1600 / 650

SR0PN i7-3770S E-1 000306A9h 3.1 / 1600 / 650

SR0PL i7-3770K E-1 000306A9h 3.5 / 1600 / 650

SR0PK i7-3770 E-1 000306A9h 3.4 / 1600 / 650

SR0P1 i5-3570T E-1 000306A9h 2.3 / 1600 / 650

Processor

Number

Stepping

Processor Signature

Core Frequency

(GHz) /

DDR3 (MHz) /

Processor

Graphics

Frequency

(GHz)

Max Intel

Turbo Boost

Technology

2.0 Frequency

4 core: 3.1 3 core: 3.4 2 core: 3.6 1 core: 3.7

4 core: 3.5 3 core: 3.6 2 core: 3.8 1 core: 3.9

4 core: 3.7 3 core: 3.8 2 core: 3.9 1 core: 3.9

4 core: 2.9

3 core: 3 2 core: 3.2 1 core: 3.3

Shared

L3 Cache

Size (MB)

8 2,3,4,5,6

82,4,6

8 2,3,4,5,6

6 3,4,5,6

Notes

Specification Update 15

Table 1. Processor Identification (Sheet 2 of 6)

Core Frequency

(GHz) /

DDR3 (MHz) /

Processor

Graphics

Frequency

Number

Processor

Number

Stepping

Processor Signature

SR0P3 i5-3550S E-1 000306A9h 3 / 1600 / 650

SR0PM i5-3570K E-1 000306A9h 3.4 / 1600 / 650

SR0P0 i5-3550 E-1 000306A9h 3.3 / 1600 / 650

SR0PP i5-3475S E-1 000306A9h 2.9 / 1600 / 650

SR0P2 i5-3450S E-1 000306A9h 2.8 / 1600 / 650

SR0PF i5-3450 E-1 000306A9h 3.1 / 1600 / 650

SR0T9 i5-3570S N-0 000306A9h 3 .1 / 1600 / 650

SR0T7 i5-3570 N-0 000306A9h 3.4 / 1600 / 650

SR0TA i5-3470S N-0 000306A9h 2.9 / 1600 / 650

SR0T8 i5-3470 N-0 000306A9h 3.2 / 1600 / 650

SR0RR i5-3330S E-1 000306A9h 2.7 / 1600 / 650

SR0RQ i5-3330 E-1 000306A9h 3 / 1600 / 650

(GHz)

Max Intel

Turbo Boost

Technology

2.0 Frequency

4 core: 3.3 3 core: 3.4 2 core: 3.6 1 core: 3.7

4 core: 3.6 3 core: 3.7 2 core: 3.8 1 core: 3.8

4 core: 3.5 3 core: 3.6 2 core: 3.7 1 core: 3.7

4 core: 3.2 3 core: 3.3 2 core: 3.5 1 core: 3.6

4 core: 3.1 3 core: 3.2 2 core: 3.4 1 core: 3.5

4 core: 3.3 3 core: 3.4 2 core: 3.5 1 core: 3.5

4 core: 3.4 3 core: 3.5 2 core: 3.7 1 core: 3.8

4 core: 3.6 3 core: 3.7 2 core: 3.8 1 core: 3.8

4 core: 3.2 3 core: 3.3 2 core: 3.5 1 core: 3.6

4 core: 3.4 3 core: 3.5 2 core: 3.6 1 core: 3.6

4 core: 2.8 3 core: 2.9 2 core: 3.1 1 core: 3.2

4 core: 3 3 core: 3.1 2 core: 3.2 1 core: 3.2

Shared

L3 Cache

Notes

Size (MB)

6 3,4,5,6

64,6

6 3,4,5,6

64,6

6 3,4,5,6

64,5,6

16 Specification Update

Table 1. Processor Identification (Sheet 3 of 6)

Core Frequency

(GHz) /

DDR3 (MHz) /

Processor

Graphics

Frequency

Number

Processor

Number

Stepping

Processor Signature

SR0PC E3-1290V2 E-1 000306A9h 3.7 / 1600 / 0

SR0P7 E3-1280V2 E-1 000306A9h 3.6 / 1600 / 0

SR0PA E3-1275V2 E-1 000306A9h 3.5 / 1600 / 650

SR0P6 E3-1270V2 E-1 000306A9h 3.5 / 1600 / 0

SR0PB

E3-

1265LV2

E-1 000306A9h 2.5 / 1600 / 650

SR0P9 E3-1245V2 E-1 000306A9h 3.4 / 1600 / 650

SR0P5 E3-1240V2 E-1 000306A9h 3.4 / 1600 / 0

SR0P4 E3-1230V2 E-1 000306A9h 3.3 / 1600 / 0

SR0PJ E3-1225V2 E-1 000306A9h 3.2 / 1600 / 650

SR0PH E3-1220V2 E-1 000306A9h 3.1 / 1600

SR0R6

E3-

1220LV2

L-1 000306A9h 2.3 / 1600 / 0

SR0RJ i5-3470T L-1 000306A9h 2.9 / 1600 / 650

(GHz)

Max Intel

Turbo Boost

Technology

2.0 Frequency

4 core: 3.8 3 core: 3.9

2 core: 4

1 core: 4.1 4 core: 3.7

3 core: 3.8 2 core: 3.9

1 core: 4

4 core: 3.7 3 core: 3.8 2 core: 3.9 1 core: 3.9

4 core: 3.1 3 core: 3.2 2 core: 3.4 1 core: 3.5

4 core: 3.6 3 core: 3.7 2 core: 3.8 1 core: 3.8

4 core: 3.5 3 core: 3.6 2 core: 3.7 1 core: 3.7

4 core: 3.4 3 core: 3.5 2 core: 3.6 1 core: 3.6

4 core: 3.3 3 core: 3.4 2 core: 3.5 1 core: 3.5

4 core: 0

3 core: 0 2 core: 3.3 1 core: 3.5

4 core: 0

3 core: 0 2 core: 3.3 1 core: 3.6

Shared

L3 Cache

Size (MB)

8 2,3,4,5,6

8 3,4,5,6

3 2,3,4,5,6

Notes

Specification Update 17

+ 39 hidden pages

Intel BX80637I53350P User Manual

Desktop 3rd Generation Intel® Core™ Processor Family

Revision History

Preface

Affected Documents

Related Documents

Nomenclature

Summary Tables of Changes

Codes Used in Summary Tables

Errata (Sheet 1 of 5)

Specification Clarifications

Documentation Changes

Identification Information

Component Identification using Programming Interface

Component Marking Information