Intel BX80637G2010 User Manual

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Desktop 3rd Generation Intel® Core™ Processor Family, Desktop

Intel and Desktop Intel

Pentium® Processor Family,

Celeron®

Processor Family

Datasheet – Volume 1 of 2

November 2013

Document Number: 326764-008

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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained

by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm.

No computer system can provide absolute security under all conditions. Intel a computer system with Intel Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses. For more information, see http://www.intel.com/technology/security/

Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor

Intel (VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configur ations and may re quire a BIOS update. S oftware applicatio ns may not be compatible

Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code

Tru sted Ex ecution Technology (Intel® TXT) requires

with all operating systems. Please check with your application vendor.

Active Management Technology requires the computer system to have an Intel(R) AMT-enabled chipset, network hardware

Intel and software, as well as connection with a power source and a corporate network connection. Setup requires configuration by the purchaser and may require scripting with the management console or further integration into existing security frameworks to enable certain functionality. It may also require modifications of implementation of new business processes. With regard to notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see http://www.intel.com/technology/

platform-technology/intel-amt/

Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technologyenabled chipset, BIOS and operating system. Performance will va ry de pe ndi ng on the specific hardware and software y ou use. For more information including details on which processors support HT Technology, see http://www.intel.com/info/hyperthreading.

“Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology.For more information, see http://www.intel.com/

technology/turboboost.”

Enhanced Intel SpeedStep

Technology See the Processor Spec Finder or contact your Intel representative for more information.

Intel processor numbers are not a measure of performance. Processor numb ers differentia te features withi n each processo r family, not across different processor families. See www.intel.com/products/processor_number for details.

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information.

Intel, Pentium, Celeron, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2013, Intel Corporation. All rights reserved.

Datasheet, Volume 1



Contents

1Introduction..............................................................................................................9

1.1 Processor Feature Details ...................................................................................11

1.1.1 Supported Technologies..........................................................................11

1.2 Interfaces ........................................................................................................11

1.2.1 System Memory Support.........................................................................11

1.2.2 PCI Express*.........................................................................................12

1.2.3 Direct Media Interface (DMI)....................................................................14

1.2.4 Platform Environment Control Interface (PECI)...........................................14

1.2.5 Processor Graphics.................................................................................14

1.2.6 Intel

1.3 Power Management Support...............................................................................15

1.3.1 Processor Core.......................................................................................15

1.3.2 System.................................................................................................15

1.3.3 Memory Controller.......................................... ............................ ............15

1.3.4 PCI Express*.........................................................................................16

1.3.5 Direct Media Interface (DMI)....................................................................16

1.3.6 Processor Graphics Controller (GT) ...........................................................16

1.3.7 Thermal Management Support .................................................................16

1.4 Processor SKU Definitions...................................................................................16

1.5 Package...........................................................................................................17

1.6 Processor Compatibility......................................................................................18

1.7 Terminology .....................................................................................................19

1.8 Related Documents ...........................................................................................22

2Interfaces................................................................................................................23

2.1 System Memory Interface ..................................................................................23

2.1.1 System Memory Technology Supported... .. .. .. .. .. .. .. ... ............................. ....23

2.1.2 System Memory Timing Support...................................... .. .. .....................24

2.1.3 System Memory Organization Modes.........................................................25

2.1.4 Rules for Populating Memory Slots............................................................26

2.1.5 Technology Enhancements of Intel

2.1.6 Data Scrambling ....................................................................................27

2.1.7 DDR3 Reference Voltage Generation................... .. ... .. ........................... .. ..27

2.2 PCI Express* Interface.......................................................................................28

2.2.1 PCI Express* Architecture .......................................................................28

2.2.2 PCI Express* Configuration Mechanism .....................................................30

2.2.3 PCI Express* Port...................................................................................31

2.3 Direct Media Interface (DMI)...............................................................................32

2.3.1 DMI Error Flow....................................... ................................................32

2.3.2 Processor / PCH Compatibility Assumptions................................................ 32

2.3.3 DMI Link Down ................... .. ......................... .. .. .......................... .. .. ......32

2.4 Processor Graphics Controller (GT) ......................................................................33

Flexible Display Interface (Intel® FDI)................ .............................15

2.1.3.1 Single-Channel Mode.................................................................25

2.1.3.2 Dual-Channel Mode – Intel

2.1.5.1 Just-in-Time Command Scheduling......................... .. .. ... .. ............27

2.1.5.2 Command Overlap....................................................................27

2.1.5.3 Out-of-Order Scheduling............................................................27

2.2.1.1 Transaction Layer .....................................................................29

2.2.1.2 Data Link Layer ........................................................................29

2.2.1.3 Physical Layer ..........................................................................29

2.2.3.1 PCI Express* Lanes Connection ..................................................31

Flex Memory Technology Mode ........... 25

Fast Memory Access (Intel® FMA)..........27

Datasheet, Volume 1 3

2.4.1 3D and Video Engines for Graphics Processing ............................................33

2.4.1.1 3D Engine Execution Units..........................................................33

2.4.1.2 3D Pipeline................................. ......................... .. .. .................34

2.4.1.3 Video Engine ............................................................................34

2.4.1.4 2D Engine ................................................. ......................... ......35

2.4.2 Processor Graphics Display ......................................................................36

2.4.2.1 Display Planes .......................... .. ......................... .. .. .................36

2.4.2.2 Display Pipes................... .......................... .. .. ......................... ..37

2.4.2.3 Display Ports ........................................ .......................... .. .. ......37

2.4.3 Intel

Flexible Display Interface (Intel® FDI) .............................................37

2.4.4 Multi Graphics Controllers Multi-Monitor Support.........................................37

2.5 Platform Environment Control Interface (PECI)......................................................38

2.6 Interface Clocking....................................... .......................... .. .. .........................38

2.6.1 Internal Clocking Requirements......................................... .......................38

3 Technologies............................................................................................................39

3.1 Intel® Virtualization Technology (Intel® VT)..........................................................39

3.1.1 Intel® Virtualization Technology (Intel® VT) for

3.1.2 Intel® Virtualization Technology (Intel® VT) for

3.1.3 Intel

3.1.4 Intel

3.1.5 Intel

3.2 Intel

IA-32, Intel (Intel

I/O (Intel

Trusted Execution Technology (Intel® TXT) ................................ .. ...............42

Virtualization Technology (Intel® VT) for Directed Virtualization Technology (Intel® VT) for Directed Virtualization Technology (Intel® VT) for Directed

64 and Intel® Architecture 

VT-x) Objectives.................................... .. .. .......................... .. .. ....39

64 and Intel® Architecture 

VT-x) Features ..................... .. .......................... .. .. .......................40

VT-d) Objectives ....................................................................40

VT-d) Features.......................................................................41

VT-d) Features Not Supported..................................................41

3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)....................................42

3.4 Intel® Turbo Boost Technology............................................................................43

3.4.1 Intel

Turbo Boost Technology Frequency............................................ .. .. ..43

3.4.2 Intel® Turbo Boost Technology Graphics Frequency.....................................43

3.5 Intel® Advanced Vector Extensions (Intel® AVX)....................................................44

3.6 Security and Cryptography Technologies...............................................................44

3.6.1 Intel

Advanced Encryption Standard New Instructions (Intel® AES-NI) ........44

3.6.2 PCLMULQDQ Instruction ..........................................................................44

3.6.3 RDRAND Instruction................................................................................45

3.7 Intel

64 Architecture x2APIC.............................................................................45

3.8 Supervisor Mode Execution Protection (SMEP) .......................................................46

3.9 Power Aware Interrupt Routing (PAIR)..................................................................46

4 Power Management .................................................................................................47

4.1 Advanced Configuration and Power Interface

(ACPI) States Supported.....................................................................................48

4.1.1 System States................................................................. .. .. ...................48

4.1.2 Processor Core / Package Idle States.........................................................48

4.1.3 Integrated Memory Controller States............................ .. ...........................48

4.1.4 PCI Express* Link States.........................................................................49

4.1.5 Direct Media Interface (DMI) States ..........................................................49

4.1.6 Processor Graphics Controller States .........................................................49

4.1.7 Interface State Combinations....................... ............................................49

4.2 Processor Core Power Management......................................................................50

4.2.1 Enhanced Intel

SpeedStep® Technology ..................................................50

4.2.2 Low-Power Idle States.............................................................................50

4.2.3 Requesting Low-Power Idle States ................................................ ............52

Datasheet, Volume 1



4.2.4 Core C-states ......................................................... .. .. ......................... ..52

4.2.4.1 Core C0 State...........................................................................52

4.2.4.2 Core C1 / C1E State..................................................................53

4.2.4.3 Core C3 State...........................................................................53

4.2.4.4 Core C6 State...........................................................................53

4.2.4.5 C-State Auto-Demotion .............................. .. .. .. .........................53

4.2.5 Package C-States.......... .. .. ......................... .. .. .......................... .. .. ..........54

4.2.5.1 Package C0..............................................................................55

4.2.5.2 Package C1/C1E .......................................................................55

4.2.5.3 Package C3 State......................................................................56

4.2.5.4 Package C6 State......................................................................56

4.3 Integrated Memory Controller (IMC) Power Management ........................................56

4.3.1 Disabling Unused System Memory Outputs ............................... ... .. .. .. .. ......56

4.3.2 DRAM Power Management and Initialization...............................................57

4.3.2.1 Initialization Role of CKE............................................................58

4.3.2.2 Conditional Self-Refresh ............................................................58

4.3.2.3 Dynamic Power Down Operation .................................................59

4.3.2.4 DRAM I/O Power Management....................................................59

4.3.3 DDR Electrical Power Gating (EPG) ...........................................................59

4.4 PCI Express* Power Management........................................................................60

4.5 DMI Power Management...................... ...............................................................60

4.6 Graphics Power Management..............................................................................60

4.6.1 Intel

4.6.2 Intel

4.6.3 Graphics Render C-State.........................................................................60

4.6.4 Intel

Rapid Memory Power Management (Intel® RMPM) 

(also known as CxSR).............................................................................60

Graphics Performance Modulation Technology (Intel® GPMT)..............60

Smart 2D Display Technology (Intel® S2DDT) .................................. 61

4.6.5 Intel® Graphics Dynamic Frequency..........................................................61

4.7 Graphics Thermal Power Management..................................................................61

5 Thermal Management..............................................................................................63

6 Signal Description ...................................................................................................65

6.1 System Memory Interface Signals............................ .. ............................ .. .. ..........66

6.2 Memory Reference and Compensation Signals.......................................................67

6.3 Reset and Miscellaneous Signals..........................................................................68

6.4 PCI Express*-based Interface Signals ..................................................................69

6.5 Intel

Flexible Display (Intel® FDI) Interface Signals.............................................69

6.6 Direct Media Interface (DMI) Signals....................................................................70

6.7 Phase Lock Loop (PLL) Signals ............................................................................70

6.8 Test Access Points (TAP) Signals .........................................................................70

6.9 Error and Thermal Protection Signals ...................................................................71

6.10 Power Sequencing Signals..................................................................................72

6.11 Processor Power Signals.....................................................................................73

6.12 Sense Signals............... .. .. ......................... ... .. ......................... .. .......................73

6.13 Ground and Non-Critical to Function (NCTF) Signals...............................................74

6.14 Processor Internal Pull-Up / Pull-Down Resistors....................................................74

7 Electrical Specifications...........................................................................................75

7.1 Power and Ground Lands....................................................................................75

7.2 Decoupling Guidelines........................................................................................75

7.2.1 Voltage Rail Decoupling...........................................................................75

7.3 Processor Clocking (BCLK[0], BCLK#[0])...................................................... .. .. ....76

7.3.1 Phase Lock Loop (PLL) Power Supply.........................................................76

7.4 VCC Voltage Identification (VID)..........................................................................76

7.5 System Agent (SA) V

VID................................................................................80

7.6 Reserved or Unused Signals................................................................................80

Datasheet, Volume 1 5

7.7 Signal Groups ...................................................................................................80

7.8 Test Access Port (TAP) Connection.................. ... .. .. ........................... .. .................82

7.9 Storage Conditions Specifications.........................................................................83

7.10 DC Specifications.................................. .. .. .......................... .. .. ......................... ..84

7.10.1 Voltage and Current Specifications... ............................ .. .. .. .......................84

7.11 Platform Environmental Control Interface (PECI) DC Specifications...........................90

7.11.1 PECI Bus Architecture..............................................................................90

7.11.2 DC Characteristics ........................... .. ... ........................... .......................91

7.11.3 Input Device Hysteresis....................................... .. ... .. .............................91

8 Processor Land and Signal Information....................................................................93

8.1 Processor Land Assignments ...............................................................................93

9 DDR Data Swizzling................................................................................................ 109

Figures

1-1 Desktop Processor Platform........................................................... ...........................10

1-2 Desktop Processor Compatibility Diagram ..................................................................18

2-1 Intel

2-2 PCI Express* Layering Diagram................................................................................28

2-3 Packet Flow Through the Layers ...............................................................................29

2-4 PCI Express* Related Register Structures in the Processor ...........................................30

2-5 PCI Express* Typical Operation 16 Lanes Mapping ......................................................31

2-6 Processor Graphics Controller Unit Block Diagram .......................................................33

2-7 Processor Display Block Diagram ..............................................................................36

4-1 Processor Power States ...........................................................................................47

4-2 Idle Power Management Breakdown of the Processor Cores..........................................51

4-3 Thread and Core C-State Entry and Exit.....................................................................51

4-4 Package C-State Entry and Exit ................................................... ........................... ..55

7-1 Example for PECI Host-Clients Connection..................................................................90

7-2 Input Device Hysteresis...........................................................................................91

8-1 LGA Socket Land Map..............................................................................................94

Flex Memory Technology Operation .................................................................26

Tables

1-1 Desktop 3rd Generation Intel® Core™ Processor Family, Desktop Intel® 

Pentium

1-2 Terminology...........................................................................................................19

1-3 Related Documents.................................................................................................22

2-1 Processor DIMM Support Summary by Product ...........................................................23

2-2 Supported UDIMM Module Configurations...................................................................24

2-3 Supported SO-DIMM Module Configurations (AIO Only)................................................24

2-4 System Memory Timing Support................ .. ..................................................... ........25

2-5 Reference Clock.................................................... .. ......................... .. .....................38

4-1 System States........................................................................................................48

4-2 Processor Core / Package State Support ....................................................................48

4-3 Integrated Memory Controller States.........................................................................48

4-4 PCI Express* Link States.........................................................................................49

4-5 Direct Media Interface (DMI) States ..........................................................................49

4-6 Processor Graphics Controller States .........................................................................49

4-7 G, S, and C State Combinations................................................................................49

4-8 Coordination of Thread Power States at the Core Level................................................51

4-9 P_LVLx to MWAIT Conversion...................................................................................52

4-10 Coordination of Core Power States at the Package Level ..............................................54

6-1 Signal Description Buffer Types ................................................................................65

Processor Family, and Desktop Intel® Celeron® Processor Family SKUs...........16

Datasheet, Volume 1



6-2 Memory Channel A Signals ......................................................................................66

6-3 Memory Channel B Signals ......................................................................................67

6-4 Memory Reference and Compensation.......................................................................67

6-5 Reset and Miscellaneous Signals...............................................................................68

6-6 PCI Express* Graphics Interface Signals....................................................................69

6-7 Intel

Flexible Display (Intel® FDI) Interface.............................................................69

6-8 Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface .......................70

6-9 Phase Lock Loop (PLL) Signals .................................................................................70

6-10 Test Access Points (TAP) Signals ..............................................................................70

6-11 Error and Thermal Protection Signals ........................................................................71

6-12 Power Sequencing Signals.......................................................................................72

6-13 Processor Power Signals..........................................................................................73

6-14 Sense Signals........................................................................................................73

6-15 Ground and Non-Critical to Function (NCTF) Signals....................................................74

6-16 Processor Internal Pull-Up / Pull-Down Resistors.........................................................74

7-1 VR 12.0 Voltage Identification Definition....................................................................77

7-2 Signal Groups 1 .....................................................................................................81

7-3 Storage Condition Ratings .......................................................................................83

7-4 Processor Core Active and Idle Mode DC Voltage and Current Specifications...................84

7-5 Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications........... 86

7-6 Processor Graphics VID based (V

) Supply DC Voltage and Current Specifications........87

AXG

7-7 DDR3 Signal Group DC Specifications........................................................................87

7-8 Control Sideband and TAP Signal Group DC Specifications ...........................................89

7-9 PCI Express* DC Specifications ................................................................................89

7-10 PECI DC Electrical Limits .........................................................................................91

8-1 Processor Land List by Land Name............................................................................95

9-1 DDR Data Swizzling Table – Channel A.................................................................... 110

9-2 DDR Data Swizzling table – Channel B .................................................................... 111

Datasheet, Volume 1 7

Revision History

Revision

Number

001 • Initial release April 2012 002

003

004

005

006

007

008 • Added Desktop Intel Pentium Processor A1018 November 2013

• Added Desktop 3rd Generation Intel i5-3475S, i5-3570, i5-3570S processors

• Updated Section 1.2.2, PCI Express*

• Updated Section 2.1.1, System Memory Technology Supported

• Updated Table 7-4, “Processor Core Active and Idle Mode DC Voltage and Current Specifications”. Added 65 W to 2011C.

• Minor edits throughout for clarity

• Added Intel Pentium G2120 and G2100T processors

• Added Desktop 3rd Generation Intel 3240, i3-3240T, i5-3330, i5-3330S, i5-3335S, i5-3350P processors

• Added Desktop 3rd Generation Intel

• Added Desktop Intel

• Added Desktop 3rd Generation Intel processor

• Added Desktop Intel

• Added Desktop 3rd Generation Intel

• Added Desktop Intel

Pentium® G2130, G2020, G2020T, G2010 processor

Celeron® G1620, G1610, G1610T processor

Pentium® G2140, G2120T, G2030, G2030T processor

Celeron® G1630, G1620, G1620T processor

Description Revision Date

Core™ i5-3470T, i5-3470, i5-3470S,

Core™ i3-3220, i3-3220T, i3-3225, i3-

Core™ i3-3210 processor

Core™ i3-3250, i3-3250T, i3-3245

Core™ i5-3340, i5-3340S processor

June 2012

September 2012

January 2013

June 2013

September 2013

§ §

Datasheet, Volume 1

Introduction

1 Introduction

The Desktop 3rd Generation Intel® Core™ processor family, Desktop Intel® Pentium® processor family , and Desktop Intel® Celeron® processor family are the next generation of 64-bit, multi-core processors built on 22-nanometer process technology. The processors are designed for a two-chip platform. The two-chip platform consists of a processor and a Platform Controller Hub (PCH) and enables higher performance, lower cost, easier validation, and improved x-y footprint. The processor includes an Integrated Display Engine, Processor Graphics, PCI Express ports, and an Integrated Memory Controller. The processor is designed for desktop platforms. The processor offers either 6 or 16 graphic execution units (EUs). The number of EU engines supported may vary between processor SKUs. The processor is offered in an 1155-land LGA package (H2). Figure 1-1 shows an example desktop platform block diagram.

The Datasheet provides DC specifications, pinout and signal definitions, interface functional descriptions, and additional feature information pertinent to the implementation and operation of the processor on its respective platform.

Note: Throughout this document, the Intel® 6 / 7 Series Chipset Platform Controller Hub may

Note: Throughout this document, the Desktop 3rd Generation Intel® Core™ processor family ,

Note: Some processor features are not available on all platforms. Refer to the processor

Note: The term “DT” refers to desktop platforms.

be referred to as “PCH”.

Desktop Intel family may be referred to simply as “processor”.

Desktop Intel family refer to the processor SKUs listed in

specification update for details.

Pentium® processor family, and Desktop Intel® Celeron® processor

Table 1-1.

Datasheet, Volume 1 9

Figure 1-1. Desktop Processor Platform

DMI2 x4

Discrete

Graphics (PEG)

Analog CRT

Gigabit

Network Connection

USB 2.0 / USB 3.0

Intel®HD Audio

FWH

Super I/O

Serial ATA

DDR3

PCI Express* 3.0

1 x16 or 2x8

8 PCI Express* 2.0

x1 Ports

(5 GT/s)

SPI

Digital Display x 3

PCI Express*

SPI Flash x 2

LPC

SMBUS 2.0

GPIO

WiFi / WiMax

Controller Link 1

PECI

Intel®6/7 Series

Chipset Families

Intel

Management

Engine

Intel

Processor

Note:

1. USB 3.0 is supported on the Intel

7 Series Chipset family only.

Introduction

10 Datasheet, Volume 1

Introduction

1.1 Processor Feature Details

• Four or two execution cores

• A 32-KB instruction and 32-KB data first-level cache (L1) for each core

• A 256-KB shared instruction / data second-level cache (L2) for each core

• Up to 8-MB shared instruction / data third-level cache (L3), shared among all cores

1.1.1 Supported Technologies

•Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d)

•Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Intel® Active Management Technology (Intel® AMT) 8.0

•Intel® Trusted Execution Technology (Intel® TXT)

•Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)

•Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)

•Intel® Hyper-Threading Technology (Intel® HT Technology)

•Intel® 64 Architecture

• Execute Disable Bit

•Intel® Turbo Boost Technology

•Intel® Advanced Vector Extensions (Intel® AVX)

•Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)

• PCLMULQDQ Instruction

• RDRAND instruction for random number generation

• SMEP – Supervisor Mode Execution Protection

• PAIR – Power Aware Interrupt Routing

1.2 Interfaces

1.2.1 System Memory Support

• T wo channels of DDR3 Unbuffered Dual In-Line Memory Modules (UDIMM) or DDR3 Unbuffered Small Outline Dual In-Line Memory Modules (SO-DIMM) with a maximum of two DIMMs per channel

• Single-channel and dual-channel memory organization modes

• Data burst length of eight for all memory organization modes

• Memory DDR3 data transfer rates of 1333 MT/s and 1600 MT/s. The DDR3 data transfer rates supported by the processor is dependent on the PCH SKU in the target platform:

— Desktop PCH platforms support 1333 MT/s and 1600 MT/s for One DIMM and

Two DIMMs per channel

— All In One platforms (AIO) support 1333 MT/s and 1600 MT/s for One DIMM

and Two DIMMs per channel

• 64-bit wide channels

• System Memory Interface I/O Voltage of 1.5 V

• DDR3 and DDR3L DIMMs/DRAMs running at 1.5 V

• No support for DDR3L DIMMs/DRAMS running at 1.35 V

Datasheet, Volume 1 11

Introduction

• Support memory configurations that mix DDR3 DIMMs/DRAMs with DDR3L DIMMs/DRAMs running at 1.5 V

• The type of the DIMM modules supported by the processor is dependent on the PCH SKU in the target platform:

— Desktop PCH platforms support non-ECC UDIMMs only — All In One platforms (AIO) support SO-DIMMs

• Theoretical Maximum Memory Bandwidth:

— 10.6 GB/s in single-channel mode or 21.3 GB/s in dual-channel mode assuming

DDR3 1333 MT/s

— 12.8 GB/s in single-channel mode or 25.6 GB/s in dual-channel mode assuming

DDR3 1600 MT/s

• Processor on-die Reference Voltage (VREF) generation for both DDR3 Read (RDVREF) and Write (VREFDQ)

• 1Gb, 2Gb, and 4Gb DDR3 DRAM device technologies are supported

— Using 4Gb DRAM device technologies, the largest memory capacity possible is

GB, assuming Dual Channel Mode with four x8 dual ranked DIMM memory

configuration

• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank devices)

• Command launch modes of 1N/2N

• On-Die Termination (ODT)

• Asynchronous ODT

•Intel® Fast Memory Access (Intel® FMA):

— Just-in-Time Command Scheduling —Command Overlap — Out-of-Order Scheduling

1.2.2 PCI Express*

• The PCI Express* lanes (PEG[15:0] TX and RX) are fully-compliant to the PCI Express Base Specification, Revision 3.0, including support for 8.0 GT/s transfer

speeds.

• Processor with Desktop PCH Supports (may vary depending on PCH SKUs)

12 Datasheet, Volume 1

• PCI Express* supported configurations in desktop products

Configuration Organization Desktop

2 2x8 Graphics, I/O 3 1x16 Graphics, I/O

1x8 2x4

Graphics, I/O

• The port may negotiate down to narrower widths

— Support for x16/x8/x4/x2/x1 widths for a single PCI Express* mode

• 2.5 GT/s, 5.0 GT/s and 8.0 GT/s PCI Express* frequencies are supported

• Gen1 Raw bit-rate on the data pins Gen 2 Raw bit -rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per pair of 500 MB/s given the 8b/10b encoding used

Introduction

to transmit data across this interface. This also does not account for packet overhead and link maintenance.

• Maximum theoretical bandwidth on the interface of 8 GB/s in each direction simultaneously, for an aggregate of 16 GB/s when x16 Gen 2

• Gen 3 raw bit-rate on the data pins of 8.0 GT/s, resulting in a real bandwidth per pair of 984 MB/s using 128b/130b encoding to transmit data across this interface. This also does not account for packet overhead and link maintenance.

• Maximum theoretical bandwidth on the interface of 16 GB/s in each direction simultaneously, for an aggregate of 32 GB/s when x16 Gen 3

• Hierarchical PCI-compliant configuration mechanism for downstream devices

• Traditional PCI style traffic (asynchronous snooped, PCI ordering)

• PCI Express* extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space.

• PCI Express* Enhanced Access Mechanism. Accessing the device configuration space in a flat memory mapped fashion.

• Automatic discovery, negotiation, and training of link out of reset

• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)

• Peer segment destination posted write traffic (no peer-to-peer read traffic) in Virtual Channel 0:

— DMI -> PCI Express* Port 0

• 64-bit downstream address format; however, the processor never generates an address above 64 GB (Bits 63:36 will always be zeros)

• 64-bit upstream address format; however, the processor responds to upstream read transactions to addresses above 64 GB (address e s wh ere any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64

GB will be dropped.

• Re-issues Configuration cycles that have been previously completed with the Configuration Retry status

• PCI Express* reference clock is 100-MHz differential clock

• Power Management Event (PME) functions

• Dynamic width capability

• Message Signaled Interrupt (MSI and MSI-X) messages

• Polarity inversion

Note: The processor does not support PCI Express* Hot-Plug.

Datasheet, Volume 1 13

1.2.3 Direct Media Interface (DMI)

• DMI 2.0 support

• Four lanes in each direction

• 5 GT/s point-to-point DMI interface to PCH is supported

• Raw bit-rate on the data pins of 5.0 Gb/s, resulting in a real bandwidth per pair of 500 MB/s given the 8b/10b encoding used to transmit data across this interface. Does not account for packet overhead and link maintenance.

• Maximum theoretical bandwidth on interface of 2 GB/s in each direction simultaneously, for an aggregate of 4 GB/s when DMI x4

• Shares 100-MHz PCI Express* reference clock

• 64-bit downstream address format; however, the processor never generates an address above 64 GB (Bits 63:36 will always be zeros)

• 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped.

• Supports the following traffic types to or from the PCH:

—DMI -> DRAM — DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only) — Processor core -> DMI

• APIC and MSI interrupt messaging support:

— Message Signaled Interrupt (MSI and MSI-X) messages

• Downstream SMI, SCI and SERR error indication

• Legacy support for ISA regime protocol (PHOLD / PHOLDA) required for parallel port DMA, floppy drive, and LPC bus masters

• DC coupling – no capacitors between the processor and the PCH

• Polarity inversion

• PCH end-to-end lane reversal across the link

• Supports Half Swing “low-power / low-voltage”

Introduction

1.2.4 Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between a PECI client (the processor) and a PECI master. The processor supports the PECI 3.0 Specification.

1.2.5 Processor Graphics

• The Processor Graphics contains a refresh of the seventh generation graphics core enabling substantial gains in performance and lower power consumption. Up to

EU support.

• Next Generation Intel Clear Video Technology HD Support is a collection of video playback and enhancement features that improve the end user’s viewing experience

— Encode / transcode HD content — Playback of high definition content including Blu-ray Disc* — Superior image quality with sharper, more colorful images — Playback of Blu-ray Disc* S3D content using HDMI* (V.1.4 with 3D)

14 Datasheet, Volume 1

Introduction

• DirectX* Video Acceleration (DXVA) support for accelerating video processing — Full AVC/VC1/MPEG2 HW Decode

• Advanced Scheduler 2.0, 1.0, XPDM support

• Windows* 7, Windows* XP, OSX, Linux OS Support

• DirectX* 11, DirectX* 10.1, DirectX* 10, DirectX* 9 support

•OpenGL* 3.0 support

• Switchable Graphics support on Desktop AIO platforms with MxM solutions only

1.2.6 Intel® Flexible Display Interface (Intel® FDI)

• For SKUs with graphics, carries display traffic from the Processor Graphics in the

processor to the legacy display connectors in the PCH

• Based on DisplayPort standard

• The two Intel FDI links are capable of being configured to support three

independent channels, one for each display pipeline

• There are two Intel FDI channels, each one consists of four unidirectional

downstream differential transmitter pairs:

— Scalable down to 3X, 2X, or 1X based on actual display bandwidth

requirements

— Fixed frequency 2.7 GT/s data rate

• Two sideband signals for display synchronization: — FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization)

• One Interrupt signal used for various interrupts from the PCH: — FDI_INT signal shared by both Intel FDI Links

• PCH supports end-to-end lane reversal across both links

• Common 100-MHz reference clock

1.3 Power Management Support

1.3.1 Processor Core

• Full support of ACPI C-states as implemented by the following processor C-states: — C0, C1, C1E, C3, C6

• Enhanced Intel SpeedStep Technology

1.3.2 System

• S0, S3, S4, S5

1.3.3 Memory Controller

• Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM))

• Dynamic power down

1.3.4 PCI Express*

• L0s and L1 ASPM power management capability

Datasheet, Volume 1 15

1.3.5 Direct Media Interface (DMI)

• L0s and L1 ASPM power management capability

1.3.6 Processor Graphics Controller (GT)

•Intel® Rapid Memory Power Management (Intel® RMPM) – CxSR

•Intel® Graphics Performance Modulation Technology (Intel® GPMT)

•Intel® Smart 2D Display Technology (Intel® S2DDT)

• Graphics Render C-State (RC6)

1.3.7 Thermal Management Support

• Digital Thermal Sensor

• Intel Adaptive Thermal Monitor

• THERMTRIP# and PROCHOT# support

• On-Demand Mode

• Memory Thermal Throttling

• External Thermal Sensor (TS-on-DIMM and TS-on-Board)

• Render Thermal Throttling

• Fan speed control with DTS

Introduction

1.4 Processor SKU Definitions

Table 1-1. Desktop 3rd Generation Intel® Core™ Processor Family, Desktop Intel® 

Pentium SKUs (Sheet 1 of 2)

Processor

Processor Family, and Desktop Intel® Celeron® Processor Family

Number

i7-3770T 45 1600 MHz 2.5 GHz up to 3.7 GHz 650 MHz up to 1150 MHz 94 i7-3770S 65 1600 MHz 3.1 GHz up to 3.9 GHz 650 MHz up to 1150 MHz 103 i7-3770K 77 1600 MHz 3.5 GHz up to 3.9 GHz 650 MHz up to 1150 MHz 105

i7-3770 77 1600 MHz 3.4 GHz up to 3.9 GHz 650 MHz up to 1150 MHz 105 i5-3570T 45 1600 MHz 2.3 GHz up to 3.3 GHz 650 MHz up to 1150 MHz 94 i5-3570S 65 1600 MHz 3.1 GHz up to 3.8 GHz 650 MHz up to 1150 MHz 103 i5-3570K 77 1600 MHz 3.4 GHz up to 3.8 GHz 650 MHz up to 1150 MHz 105

i5-3570 77 1600 MHz 3.4 GHz up to 3.8 GHz 650 MHz up to 1150 MHz 105 i5-3550S 65 1600 MHz 3 GHz up to 3.7 GHz 650 MHz up to 1150 MHz 103

i5-3550 77 1600 MHz 3.3 GHz up to 3.7 GHz 650 MHz up to 1150 MHz 105 i5-3475S 65 1600 MHz 2.9 GHz up to 3.6 GHz 650 MHz up to 1100 MHz 103 i5-3470S 65 1600 MHz 2.9 GHz up to 3.6 GHz 650 MHz up to 1100 MHz 103 i5-3470T 35 1600 MHz 2.9 GHz up to 3.6 GHz 650 MHz up to 1100 MHz, 91

i5-3470 77 1600 MHz 3.2 GHz up to 3.6 GHz 650 MHz up to 1100 MHz 105 i5-3450S 65 1600 MHz 2.8 GHz up to 3.5 GHz 650 MHz up to 1100 MHz 103

i5-3450 77 1600 MHz 3.1 GHz up to 3.5 GHz 650 MHz up to 1100 MHz 105 i5-3350P 69 1600 MHz 3.1 GHZ up to 3.3 GHZ N/A 105

i5-3340 77 1600 MHz 3.1 GHZ up to 3.3 GHZ 650 MHz up to 1050 MHz 105

TDP (W)

IA LFM

Frequency

IA Frequency range GT Frequency range

jMAX

(°C)

16 Datasheet, Volume 1

Introduction

Table 1-1. Desktop 3rd Generation Intel® Core™ Processor Family, Desktop Intel® 

Pentium

Processor Family, and Desktop Intel® Celeron® Processor Family

SKUs (Sheet 2 of 2)

Processor

Number

i5-3340S 65 1600 MHz 3.0 GHZ up to 3.3 GHZ 650 MHz up to 1050 MHz 103 i5-3335S 65 1600 MHz 2.7 GHz up to 3.2 GHz 650 MHz up to 1050 MHz 103 i5-3330S 65 1600 MHz 2.7 GHz up to 3.2 GHz 650 MHz up to 1050 MHz 103

i3-3250T 35 1600 MHz N/A 650 MHz up to 1050 MHz 91

i3-3250 55 1600 MHz N/A 650 MHz up to 1050 MHz 105 i3-3245 55 1600 MHz N/A 650 MHz up to 1050 MHz 105 i5-3330 77 1600 MHz 3 GHz up to 3.2 GHz 650 MHz up to 1050 MHz 105

i3-3240T 35 1600 MHz Up to 3.0 GHz 650 MHz up to 1050 MHz 91

i3-3240 55 1600 MHz Up to 3.4 GHz 650 MHz up to 1050 MHz 105 i3-3225 55 1600 MHz Up to 3.3 GHz 650 MHz up to 1050 MHz 105

i3-3220T 35 1600 MHz Up to 2.8 GHz 650 MHz up to 1050 MHz 91

i3-3220 55 1600 MHz Up to 3.3 GHz 650 MHz up to 1050 MHz 105 i3-3210 55 1600 MHz Up to 3.2 GHz 650 MHz up to 1050 MHz 105

G2140 55 1600 MHz N/A 650 MHz up to 1050 MHz 105 G2130 55 1600 MHz Up to 3.2 GHz 650 MHz up to 1050 MHz 105

G2120T 3 5 1600 MHz N/A 650 MHz up to 1050 MHz 91

G2120 55 1600 MHz 3.1 GHZ 650 MHZ up to 1.05 GHZ 105 G2100T 35 1600 MHz 2.6 GHZ 650 MHZ up to 1.05 GHZ 91 G2030T 3 5 1600 MHz N/A 650 MHz up to 1050 MHz 91

G2030 35 1600 MHz N/A 650 MHz up to 1050 MHz 105

G2020 55 1600 MHz 2.9 GHZ 650 MHZ up to 1050 MHz 105 G2020T 3 5 1600 MHz 2.5 GHZ 650 MHZ up to 1050 MHz 91

G2010 55 1600 MHz 2.8 GHZ 650 MHZ up to 1050 MHz 105

G1630 55 1600 MHz 2.8 GHZ 650 MHZ up to 1050 MHz 105

G1620 55 1600 MHz 2.7 GHZ 650 MHZ up to 1050 MHz 105 G1620T 3 5 1600 MHz 2.4 GHZ 650 MHZ up to 1050 MHz 91

G1610 55 1600 MHz 2.6 GHZ 650 MHZ up to 1050 MHz 105 G1610T 3 5 1600 MHz 2.3 GHZ 650 MHZ up to 1050 MHz 91

A1018 35 1600 MHz 2.1 GHz 650 MHz up to 1 GHz 105

TDP (W)

IA LFM

Frequency

IA Frequency range GT Frequency range

jMAX

(°C)

1.5 Package

The processor socket type is noted as LGA 1155. The package is a 37.5 x 37.5 mm Flip Chip Land Grid Array (FCLGA 1155). See the Desktop 3rd Generation Intel

Processor Family, Desktop Intel

Pentium® Processor Family, Desktop Intel® Celeron® Processor Family, and LGA1155 Socket Thermal / Mechanical Specifications and Design Guidelines for complete details on the package.

Datasheet, Volume 1 17

Core™

1.6 Processor Compatibility

2 x 330 µF

2 x 330 µF + 1 placeholder

VCCIO

VDDQ

VCore

VCCSA

VAXG

DDR3

G2_Core: 1.5 V

G3_Core: 1.5 V

G2_Core: 1.05 V

G3_Core: 1.05 V

VCCIO_SEL#

G2_Core: ‘1’

G3_Core: ‘1’

Processor

PCH

VCCSA_VID

G2_Core: ‘0’

G3_Core: ‘0’

G2_Core: 0.925 V

G3_Core: 0.925 V

PEG AC Decoupling

PEG Gen 1,2 – 100 nF

PEG Gen 1,2,3 – 220 nF

*VAXG: 2 ph required for some of the SKUs

SVID

PROC_SELECT#

G2_Core: ‘1’

G3_Core: ‘0’

Controls DMI And FDI termination

DF_TVS

The Desktop 3rd Generation Intel® Core™ processor family, Desktop Intel® Pentium® processor family, Desktop Intel requirements that differentiate it from a 2nd Generation Intel® Core™ processor family Desktop, Intel

Pentium® processor family Desktop, Intel® Celeron® processor Family Desktop processor. Platforms intending to support both processor families need to address the platform compatibility requirements detailed in Figure 1-2.

Figure 1-2. Desktop Processor Compatibility Diagram

Celeron® processor Family has specific platform

Introduction

18 Datasheet, Volume 1

Notes:

1. G2_Core = 2nd Generation Intel

2. G3_Core = Desktop 3rd Generation Intel

family Desktop, Intel

processor, Desktop Intel

Celeron® processor family Desktop,

Core™ processor family Desktop, Intel® Pentium® processor

Celeron® processor family

Core™ processor family, Desktop Intel® Pentium®

Introduction

1.7 Terminology

Table 1-2. Terminology (Sheet 1 of 3)

Term Description

ACPI Advanced Configuration and Power Interface ADB Automatic Display Brightness APD Active Power Down ASPM Active State Power Management BGA Ball Grid Array BLT Block Level Transfer CLTT Closed Loop T hermal Throttling CRT Cathode Ray Tube cTDP Configurable Thermal Design Power DDDR3L-RS DDR3L Reduced Standby Power DDR3 Third-generation Double Data Rate SDRAM memory technology DDR3L DDR3 Low Voltage DMA Direct Memory Access DMI Direct Media Interface DP DisplayPort* DPST Display Power Savings Technology DTS Digital Thermal Sensor EC Embedded Controller ECC Error Correction Code eDP* Embedded DisplayPort* Enhanced Intel

SpeedStep Technology

EPG Electrical Power Gating EU Execution Unit

Execute Disable Bit

HDMI* High Definition Multimedia Interface HFM High Frequency Mode IMC Integrated Memory Controller

Intel

64 Technology 64-bit memory extensions to the IA-32 architecture

Intel

DPST Intel® Display Power Saving Technology

Intel

FDI Intel® Flexible Display Interface

Intel

TXT Intel® Trusted Execution Technology

Intel

Virtualization

Technology

Technology that provides power management capabilities to laptops.

The Execute Disable bit allows memory to be marked as executable or non-executable, when combined with a supporting operating system. If code attempts to run in nonexecutable memory the processor r aises an error t o the operat ing system. This featu re can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the

Intel

64 and IA-32 Architectures Software Developer's Manuals for more detailed

information.

Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform.

Datasheet, Volume 1 19

Table 1-2. Terminology (Sheet 2 of 3)

Term Description

Virtualization T echnology (Intel® VT) for Directed I/O. Intel VT -d is a hardware

Intel

VT-d

IOV I/O Virtualization

ISA

ITPM Integrated Trusted Platform Module LCD Liquid Crystal Display LFM Low Frequency Mode LPC Low Pin Count LPM Low Power Mode

LVDS

MLE Measured Launched Environment MSI Message Signaled Interrupt

NCTF

ODT On-Die Termination PAIR Power Aware Interrupt Routing

PCH

PECI Platform Environment Control Interface.

PEG

PGA Pin Grid Array PLL Phase Lock Loop PME Power Management Event PPD Precharged Power Down Processor The 64-bit, single-core or multi-core component (package).

Processor Core

Processor Graphics Intel Processor Graphics

Rank

SCI System Control Interrupt. Used in ACPI protocol. Intel SDRRS

Technology SMEP Supervis or Mode Execution Protection

assist, under system software (Virtual Machine Manager or operating system) control, for enabling I/O device virtualization. Intel VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d.

Industry Standard Architecture. Th is is a legacy computer bus standard for IBM PC compatible computers.

Low Voltage Differential Signaling. A high speed, low power data transmission standard used for display connections to LCD panels.

Non-Critical to Function. NCTF locations are typically redundant ground or non-critical reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality.

Platform Controller Hub. The chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security and storage features.

PCI Express* Graphics. External Graphics using PCI Express* Architecture. A highspeed serial interface whose configuration is software compatible with the existing PCI specifications.

The term “processor core” refers to Si die itself that can contain multiple execution cores. Each execution core has an ins truction cache, data cache , and 256-KB L2 cache. All execution cores share the L3 cache.

A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a SO-DIMM.

Intel Seamless Display Refresh Rate Switching Technology

Introduction

20 Datasheet, Volume 1

Introduction

Table 1-2. Terminology (Sheet 3 of 3)

Term Description

A non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these

Storage Conditions

SVID Serial Voltage IDentification interface TAC Thermal Averaging Constant TAP Test Access Point TCC Thermal Control Circuit TDC Thermal Design Current TDP Thermal Design Power TLP Transaction Layer Packet V

AXG

CCIO

CCPLL

CCSA

DDQ

VGA Video Graphics Array VID Voltage Identification VLD Variable Length Decoding VLW Virtual Legacy Wire VR Voltage Regulator V

VTS Virtual Temperature Sensor x1 Refers to a Link or Port with one Physical Lane. x16 Refers to a Link or Port with sixteen Physical Lanes. x4 Refers to a Link or Port with four Physical Lanes. x8 Refers to a Link or Port with eight Physical Lanes.

conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (that is, unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.

Graphics core power supply Processor core power supply High Frequency I/O logic power supply PLL power supply System Agent (memory controller, DMI, PCIe controllers, and display engine) power

supply DDR3 power supply

Processor ground

Datasheet, Volume 1 21

1.8 Related Documents

Table 1-3. Related Documents

Introduction

Document

Desktop 3rd Generation Intel

Pentium Datasheet, Volume 2

Desktop 3rd Generation Intel Pentium Specification Update

Desktop 3rd Generation Intel Pentium LGA1155 Socket Thermal / Mechanical Specifications and Design Guidelines

Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info/ PCI Local Bus Specification 3.0 http://www.pcisig.com/speci

PCI Express* Base Specification 2.0 http://www.pcisig.com DDR3 SDRAM Specification http://www.jedec.org DisplayPort* Specification http://www.vesa.org Intel

Processor Family, and Desktop Intel® Celeron® Processor Family

Processor Family, Desktop Intel® Celeron® Processor Family, and

64 and IA-32 Architectures Software Developer's Manuals http://www.intel.com/produ

Volume 1: Basic Architecture 253665 Volume 2A: Instruction Set Reference, A-M 253666 Volume 2B: Instruction Set Reference, N-Z 253667 Volume 3A: System Programming Guide 253668 Volume 3B: System Programming Guide 253669

Core™ Processor Family, Desktop Intel®

Document Number /

Location

326765

326766

326767

fications

cts/processor/manuals/inde

x.htm

Note: Contact your Intel representative for the latest revision of this item.

§ §

22 Datasheet, Volume 1

Interfaces

2 Interfaces

This chapter describes the interfaces supported by the processor.

2.1 System Memory Interface

2.1.1 System Memory Technology Supported

The Integrated Memory Controller (IMC) supports DDR3 / DDR3L protocols with two independent, 64-bit wide channels, each accessing one or two DIMMs. The type of memory supported by the processor is dependant on the PCH SKU in the target platform. Refer to Chapter 1 for supported memory configuration details.

Note: The processor supports only JEDEC approved memory modules and devices. Note: The IMC supports a maximum of two DIMMs per channel; thus, allowing up to four

device ranks per channel.

Note: The supported memory interface frequencies and number of DIMMs per channel are

SKU dependent.

Table 2-1. Processor DIMM Support Summary by Product

Processor

cores

Dual Core, Quad Core

Note: There is no support for DDR3L DIMMs/DRAMS running at 1.35 V.

Package

uLGA

DIMM per

channel

1 DPC 2 DPC 1333,1600 1333/1600 1 DPC 2 DPC 1333/1600 1333/1600

DIMM type DDR3 DDR3L at 1.5 V

SO-DIMM

UDIMM

1333/1600 1333/1600

• DDR3 / DDR3L at 1.5 V Data Transfer Rates — 1333 MT/s (PC3-10600), 1600 MT/s (PC3-12800)

• DDR3 / DDR3L at 1.5 V SO-DIMM Modules — Raw Card A – Dual Ranked x16 unbuffered non-ECC — Raw Card B – Single Ranked x8 unbuffered non-ECC

— Raw Card C – Single Ranked x16 unbuffered non-ECC — Raw Card F – Dual Ranked x8 (planar) unbuffered non-ECC

• Desktop platform DDR3/DDR3L at 1.5 V UDIMM Modules — Raw Card A – Single Ranked x8 unbuffered non-ECC

— Raw Card B – Dual Ranked x8 unbuffered non-ECC — Raw Card C – Single Ranked x16 unbuffered non-ECC

Note: The processor supports memory configurations that mix DDR3 DIMMs / DRAMs with

DDR3L DIMMs / DRAMs running at 1.5

Datasheet, Volume 1 23

Table 2-2. Supported UDIMM Module Configurations

Raw

Card

Version

DIMM

Capacity

DRAM

Device

Technology

DRAM

Organization

# of

DRAM

Devices

# of

Physical

Device

Ranks

# of

Row/Col

Address

Bits

Interfaces

# of Banks Inside DRAM

Page

Size

Unbuffered/Non-ECC Supported DIMM Module Configurations

1 GB 1 Gb 128 M X 8 8 1 14/10 8 8K

C 1 GB 2 Gb 128 M X 16 4 1 14/10 8 16K

Note:

1. DIMM module support is based on availability and is subject to change.

2 GB 2 Gb 128 M X 16 8 1 1510 8 8K 4 GB 4 Gb 512 M X 8 8 1 15/10 8 8K 2 GB 1 Gb 128 M X 8 16 2 14/10 8 8K 4 GB 2 Gb 256 M X 8 16 2 15/10 8 8K 8 GB 4 Gb 512 M X 8 16 2 16/10 8 8K

Desktop Platforms:

Table 2-3. Supported SO-DIMM Module Configurations (AIO Only)

Raw

Card

Version

DIMM

Capacity

2 GB 2 Gb 128 M x 16 8 2 14/10 8 8K 4 GB 4 Gb 256 M x 16 8 2 15/10 8 8K 1 GB 1 Gb 128 M x 8 8 1 14/10 8 8K 2 GB 2 Gb 256 M x 8 8 1 15/10 8 8K 4 GB 4 Gb 512 M x 8 8 1 16/10 8 8K 1 GB 2 Gb 128 M x 16 4 1 14/10 8 8K 2 GB 4 Gb 256 M x 16 4 1 15/10 8 8K 2 GB 1 Gb 128 M x 8 16 2 14/10 8 8K 4 GB 2 Gb 256 M x 8 16 2 15/10 8 8K 8 GB 4 Gb 512 M x 8 16 2 16/ 10 8 8K

DRAM

Device

Technology

DRAM

Organization

# of

DRAM

Devices

# of

Physical

Device

Ranks

# of

Row/Col

Address

Bits

# of

Banks

Inside

DRAM

Page

Size

Note:

1. System memory configurations are based on availability and are subject to change.

2.1.2 System Memory Timing Support

The IMC supports the following Speed Bins, CAS Write Latency (CWL), and command signal mode timings on the main memory interface:

• tCL = CAS Latency

• tRCD = Activate Command to READ or WRITE Command delay

• tRP = PRECHARGE Command Period

• CWL = CAS Write Latency

• Command Signal modes = 1N indicates a new command may be issued every clock and 2N indicates a new command may be issued every 2 clocks. Command launch mode programming depends on the transfer rate and memory configuration.

24 Datasheet, Volume 1

Interfaces

Table 2-4. System Memory Timing Support

Segment

Desktop

AIO

Note:

1. System memory timing support is based on availability and is subject to change.

Transfer

Rate

(MT/s)

1333 9 9 9 7

1600 11 11 11 8

1333 9 9 9 7

1600 11 11 11 8 1 1N/2N

tCL

(tCK)

tRCD

(tCK)

tRP

(tCK)

2.1.3 System Memory Organization Modes

The IMC supports two memory organization modes, single-channel and dual-channel. Depending upon how the DIMM Modules are populated in each memory channel, a number of different configurations can exist.

2.1.3.1 Single-Channel Mode

In this mode, all memory cycles are directed to a single-channel. Single-channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order, but not both.

CWL

(tCK)

DPC

11N/2N 22N 11N/2N 22N 11N/2N 22N

CMD

Mode

Notes

2.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode

The IMC supports Intel Flex Memory Technology Mode. Memory is divided into a symmetric and a asymmetric zone. The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached. In this mode, the system runs with one zone of dual-channel mode and one zone of single-channel mode, simultaneously, across the whole memory array.

Note: Channels A and B can be mapped for physical channel 0 and 1 respectively or vice

versa; however, channel A size must be greater or equal to channel B size.

Datasheet, Volume 1 25

Figure 2-1. Intel® Flex Memory Technology Operation

CH BCH A

B B

Non interleaved access

Dual channel interleaved access

TOM

CH A and C H B can be configured to be physical channels 0 or 1 B – The largest physical mem ory amount of the sm aller size me m ory module C – The rema ining physical m em ory amoun t of the larger size m em ory mod ule

Interfaces

2.1.3.2.1 Dual-Channel Symmetric Mode

Note: The DRAM device technology and width may vary from one channel to the other.

2.1.4 Rules for Populating Memory Slots

Note: In a Two DIMM Per Channel (2DPC) daisy chain layout memory configuration, the

Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum performance on real world applications. Addresses are ping-ponged between the channels after each cache line (64-byte boundary). If there are two requests, and the second request is to an address on the opposite channel from the first, that request can be sent before data from the first request has returned. If two consecutive cache lines are requested, both may be retrieved simultaneously, since they are ensured to be on opposite channels. Use Dual-Channel Symmetric mode when both Channel A and Channel B DIMM connectors are populated in any order, with the total amount of memory in each channel being the same.

When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory, the IMC operates completely in Dual-Channel Symmetric mode.

In all System Memory Organization Modes, the frequency and latency timings of the system memory is the lowest supported frequency and slowest supported latency timings of all memory DIMM modules placed in the system, as determined through the SPD registers.

furthest DIMM from the processor of any given channel must always be populated first.

26 Datasheet, Volume 1

Interfaces

2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements.

2.1.5.1 Just-in-Time Command Scheduling

The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next. The most efficient request is picked from all pending requests and issued to system memory Just-in-Time to make optimal use of Command Overlapping. Thus, instead of having all memory access requests go individually through an arbitration mechanism forcing requests to be executed one at a time, they can be started without interfering with the current request allowing for concurrent issuing of requests. This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol.

2.1.5.2 Command Overlap

Command Overlap allows the insertion of the DRAM commands between the Activate, Precharge, and Read/Write commands normally used, as long as the inserted commands do not affect the currently executing command. Multiple commands can be issued in an overlapping manner, increasing the efficiency of system memory protocol.

2.1.5.3 Out-of-Order Scheduling

While leveraging the Just-in-Time Scheduling and Command Overlap enhancements, the IMC continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency. If there are multiple requests to the same open page, these requests would be launched in a back to back manner to make optimum use of the open memory page. This ability to reorder requests on the fly allows the IMC to further reduce latency and increase bandwidth efficiency.

2.1.6 Data Scrambling

The memory controller incorporates a DDR3 Data Scrambling feature to minimize the impact of excessive di/dt on the platform DDR3 VRs due to successive 1s and 0s on the data bus. Past experience has demonstrated that traffic on the data bus is not r andom. Rather, it can have energy concentrated at specific spectral harmonics creating high di/dt that is generally limited by data patterns that excite resonance between the package inductance and on die capacitances. As a result the memory controller uses a data scrambling feature to create pseudo-random patterns on the DDR3 data bus to reduce the impact of any excessive di/dt.

2.1.7 DDR3 Reference Voltage Generation

The processor memory controller has the capability of generating the DDR3 Reference Voltage (VREF) internally for both read (RDVREF) and write (VREFDQ) operations. The generated VREF can be changed in small steps, and an optimum VREF value is determined for both during a cold boot through advanced DDR3 training procedures in order to provide the best voltage and signal margins.

Datasheet, Volume 1 27

2.2 PCI Express* Interface

Transaction

Data Link

Physical

Logical Sub-block

Electrical Sub-block

RX TX

Transaction

Data Link

Physical

Logical Sub-block

Electrical Sub-block

RX TX

This section describes the PCI Express interface capabilities of the processor. See the PCI Express Base Specification for details of PCI Express.

The number of PCI Express controllers is dependent on the platform. Refer to Chapter 1 for details.

2.2.1 PCI Express* Architecture

Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers may operate unchanged.

The PCI Express configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification. The processor external graphics ports support Gen 3 speed as well. At 8 GT/s, Gen 3 operation results in twice as much bandwidth per lane as compared to Gen 2 operation. The 16-lane PCI Express* graphics port can operate at either 2.5 GT/s, 5 GT/s, or 8 GT/s.

PCI Express* Gen 3 uses a 128/130b encoding scheme, eliminating nearly all of the overhead of the 8b/10b encoding scheme used in Gen 1 and Gen 2 operation.

Interfaces

The PCI Express architecture is specified in three layers – Transaction Layer, Data Link Layer, and Physical Layer. The partitioning in the component is not necessarily along these same boundaries. Refer to Figure 2-2 for the PCI Express layering diagram.

Figure 2-2. PCI Express* Layering Diagram

PCI Express uses packets to communicate information between components. Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side, the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device.

28 Datasheet, Volume 1

Interfaces

Sequence

Number

Framing Header Data ECRC LCRC Framing

Transaction Layer

Data Link Layer

Physical Layer

Figure 2-3. Packet Flow Through the Layers

2.2.1.1 Transaction Layer

The upper layer of the PCI Express* architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events. The Transaction Layer also manages flow control of TLPs.

2.2.1.2 Data Link Layer

The middle layer in the PCI Express stack, the Data Link Layer, serves as an intermediate stage between the Transaction Layer and the Physical Layer. Responsibilities of Data Link Layer include link management, error detection, and error correction.

The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer, calculates and applies data protection code and TLP sequence number, and submits them to Physical Layer for transmission across the Link. The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the T ransaction Layer for further processing. On detection of TLP error(s), this layer is responsible for requesting retransm ission of TLPs until information is correctly received, or the Link is determined to have failed. The Data Link Layer also generates and consumes packets which are used for Link management functions.

2.2.1.3 Physical Layer

The Physical Layer includes all circuitry for interface operation, including driver and input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), clock recovery circuits and impedance matching circuitry. It also includes logical functions related to interface initialization and maintenance. The Physical Layer exchanges data with the Data Link Layer in an implementation-specific format, and is responsible for converting this to an appropriate serialized format and transmitting it across the PCI Express Link at a frequency and width compatible with the remote device.

Datasheet, Volume 1 29

2.2.2 PCI Express* Configuration Mechanism

PCI-PCI Bridge

representing

root PCI

Express* ports

(Device 1 and

Device 6)

PCI Compatible

Host Bridge

Device

(Device 0)

PCI

Express*

Device

PEG0

DMI

The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure.

Figure 2-4. PCI Express* Related Register Structures in the Processor

Interfaces

PCI Express extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express configuration space is divided into a PCI-compatible region (that consists of the first 256 bytes of a logical device's configuration space) and an extended PCI Express region (that consists of the remaining configuration space). The PCI-compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express configuration access mechanism described in the PCI Express Enhanced Configuration Mechanism section.

The PCI Express Host Bridge is required to translate the memory-mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is recommended that system software access the enhanced configuration space using 32-bit operations (32-bit aligned) only. See the PCI Express Base Specification for details of both the PCI-compatible and PCI Express Enhanced configuration mechanisms and transaction rules.

30 Datasheet, Volume 1

Interfaces

1 X 16 Controller

Lane 0

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

Lane 9

Lane 10

Lane 11

Lane 12

Lane 13

Lane 14

Lane 15

1 X 8 Controller

1 X 4 Controller

2.2.3 PCI Express* Port

The PCI Express interface on the processor is a single, 16-lane (x16) port that can also be configured at narrower widths. The PCI Express port is being designed to be compliant with the PCI Express Base Specification, Revision 3.0.

2.2.3.1 PCI Express* Lanes Connection

Figure 2-5 demonstrates the PCIe lanes mapping.

Figure 2-5. PCI Express* Typical Operation 16 Lanes Mapping

Datasheet, Volume 1 31

2.3 Direct Media Interface (DMI)

Direct Media Interface (DMI) connects the processor and the PCH. Next generation DMI

2.0 is supported.

Note: Only DMI x4 configuration is supported.

2.3.1 DMI Error Flow

DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or GPE. Any DMI related SERR activity is associated with Device 0.

2.3.2 Processor / PCH Compatibility Assumptions

The processor is compatible with the Intel 7 Series Chipset PCH products.

2.3.3 DMI Link Down

The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to data link down, after the link was up, then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption. This link behavior is controlled by the PCH.

Interfaces

Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal. No completions from downstream, non-posted transactions are returned upstream over the DMI link after a link down event.

32 Datasheet, Volume 1

Interfaces

Vertex

Fetch

VS/GS

Setup/Rasterize

Hierachical Z

Hardware Clipper

EU EU

Unified Execution Unit Array

Texture

Unit

Pixel

Backend

Full MPEG2, VC1, AV C De cod e

Fixed Function Post Processing

Full AVC Encode

Partial MPEG2, VC1 Encode

Multi-Form at Decode/Encode

Additional Post Processing

2.4 Processor Graphics Controller (GT)

New Graphics Engine Architecture includes 3D compute elements, Multi-format hardware assisted decode/encode pipeline, and Mid-Level Cache (MLC) for superior high definition playback, video quality, and improved 3D performance and Media.

The Display Engine handles delivering the pixels to the screen, and is the primary channel interface for display memory accesses and “PCI-like” traffic in and out.

Figure 2-6. Processor Graphics Controller Unit Block Diagram

2.4.1 3D and Video Engines for Graphics Processing

2.4.1.1 3D Engine Execution Units

Datasheet, Volume 1 33

The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive. All the cores are fully programmable, increasing the versatility of the 3D Engine. The Gen 7.0 3D engine provides the following performance and power-management enhancements:

• Up to 16 Execution units (EUs)

•Hierarchal-Z

• Video quality enhancements

• Supports up to 16 EUs. The EUs perform 128-bit wide execution per clock

• Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing

2.4.1.2 3D Pipeline

2.4.1.2.1 Vertex Fetch (VF) Stage

The VF stage executes 3DPRIMITIVE commands. Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL*.

2.4.1.2.2 Vertex Shader (VS) Stage

The VS stage performs shading of vertices output by the VF function. The VS unit produces an output vertex reference for every input vertex reference received from the VF unit, in the order received.

2.4.1.2.3 Geometry Shader (GS) Stage

The GS stage receives inputs from the VS stage. Compiled application-provided GS programs, specifying an algorithm to convert the vertices of an input object into some output primitives. For example, a GS shader may convert lines of a line strip into polygons representing a corresponding segment of a blade of grass centered on the line. Or it could use adjacency information to detect silhouette edges of triangles and output polygons extruding out from the edges.

Interfaces

2.4.1.2.4 Clip Stage

The Clip stage performs general processing on incoming 3D objects. However, it also includes specialized logic to perform a Clip T est function on incoming objects. The Clip Test optimizes generalized 3D Clipping. The Clip unit examines the position of incoming vertices, and accepts/rejects 3D objects based on its Clip algorithm.

2.4.1.2.5 Strips and Fans (SF) Stage

The SF stage performs setup operations required to rasterize 3D objects. The outputs from the SF stage to the Windower stage contain implementation-specific information required for the rasterization of objects and also supports clipping of primitives to some extent.

2.4.1.2.6 Windower/IZ (WIZ) Stage

The WIZ unit performs an early depth test, which removes failing pixels and eliminates unnecessary processing overhead.

The Windower uses the parameters provided by the SF unit in the object-specific rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of pixels. The Windower is also capable of performing dithering, whereby the illusion of a higher resolution when using low-bpp channels in color buffers is possible. Color dithering diffuses the sharp color bands seen on smooth-shaded objects.

2.4.1.3 Video Engine

The video engine is part of the Intel Processor Graphics for image processing, playback and transcode of Video applications. The Processor Graphics video engine has a dedicated fixed hardware pipe-line for high quality decode and encode of media content. This engine supports Full hardware acceleration for decode of AVC/H.264,  VC-1 and MPEG -2 contents along with encode of MPEG-2 and AVC/H.264 apart from various video processing features. The new Processor Graphics Video engine adds support for processing features such as frame rate conversion, image stabilization, and gamut conversion.

34 Datasheet, Volume 1

Interfaces

2.4.1.4 2D Engine

The Display Engine fetches the raw data from the memory, puts the data into a stream, converts the data into raw pixels, organizes pixels into images, blends different planes into a single image, encodes the data, and sends the data out to the display device.

The Display Engine executes its functions with the help of three main functional blocks – Planes, Pipes, and Ports, except for eDP. The Planes and Pipes are in the processor while the Ports reside in the PCH. Intel FDI connects the displa y engine in the processor with the Ports in the PCH. The 2D Engine adds a new display pipe C that enables support for three simultaneous and concurrent display configurations.

2.4.1.4.1 Processor Graphics Registers

The 2D registers consists of original VGA registers and others to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original VGA standard.

2.4.1.4.2 Logical 128-Bit Fixed BLT and 256 Fill Engine

This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The 128-bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations. The BLT engine can be used for the following:

• Move rectangular blocks of data between memory locations

• Data alignment

• To perform logical operations (raster ops)

The rectangular block of data does not change, as it is transferred between memory locations. The allowable memory transfers are between cacheable system memory and frame buffer memory, frame buffer memory and frame buffer memory, and within system memory. Data to be transferred can consist of regions of memory, patterns, or solid color fills. A pattern is always 8 x 8 pixels wide and may be 8, 16, or 32 bits per pixel.

The BLT engine expands monochrome data into a color depth of 8, 16, or 32 bits. BLTs can be either opaque or transparent. Opaque transfers move the data specified to the destination. Transparent transfers compare destination color to source color and write according to the mode of transparency selected.

Data is horizontally and vertically aligned at the destination. If the destination for the BLT overlaps with the source memory location, the BLT engine specifies which area in memory to begin the BLT transfer. Hardware is included for all 256 raster operations (source, pattern, and destination) defined by Microsoft, including transparent BLT.

The BLT engine has instructions to invoke BLT and stretch BLT operations, permitting software to set up instruction buffers and use batch processing. The BLT engine can perform hardware clipping during BLTs.

Datasheet, Volume 1 35

2.4.2 Processor Graphics Display

Memory

Host

Interface

(Outside of

Display

Engine)

Pipe A Plane

Pipe B Plane

Pipe C

Plane

Panel Fitting

Cross Point

Mux

Panel Fitting

Transcoder

FDI 0

(Tx side)

FDI 1

(Tx side)

VGA

The Processor Graphics controller display pipe can be broken down into three components:

•Display Planes

• Display Pipes

• DisplayPort* and Intel® FDI

Figure 2-7. Processor Display Block Diagram

Interfaces

2.4.2.1 Display Planes

A display plane is a single displayed surface in memory and contains one image (desktop, cursor, overlay). It is the portion of the display hardware logic that defines the format and location of a rectangular region of memory that can be displayed on display output device and delivers that data to a display pipe. This is clocked by the Core Display Clock.

2.4.2.1.1 Primary Planes A, B, and C

Planes A, B, and C are the main display planes and are associated with Pipes A, B, and C respectively.

2.4.2.1.2 Sprite A, B, and C

Sprite A and Sprite B are planes optimized for video decode, and are associated with Planes A and B respectively. Sprite A and B are also double-buffered.

2.4.2.1.3 Cursors A, B, and C

Cursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration, and are associated with Planes A and B respectively. These planes support resolutions up to 256 x 256 each.

2.4.2.1.4 Video Graphics Array (VGA)

VGA is used for boot, safe mode, legacy games, and so on. It can be changed by an application without operating system/driver notification, due to legacy requirements.

36 Datasheet, Volume 1

Interfaces

2.4.2.2 Display Pipes

The display pipe blends and synchronizes pixel data received from one or more display planes and adds the timing of the display output device upon which the image is displayed.

The display pipes A, B, and C operate independently of each other at the rate of 1 pixel per clock. They can attach to any of the display ports. Each pipe sends display data to eDP* or to the PCH over the Intel® Flexible Display Interface (Intel® FDI).

2.4.2.3 Display Ports

The display ports consist of output logic and pins that transmit the display data to the associated encoding logic and send the data to the display device (that is, LVDS, HDMI*, DVI, SDVO, and so on). All display interfaces connecting external displays are now repartitioned and driven from the PCH. Refer to the PCH datasheet for more details on display port support.

2.4.3 Intel® Flexible Display Interface (Intel® FDI)

Intel® Flexible Display Interface (Intel® FDI) is a proprietary link for carrying display traffic from the Processor Graphics controller to the PCH display I/Os. Intel FDI supports two or three independent channels – one for pipe A, one for pipe B, and one for Pipe C.

Channels A and B have a maximum of four transmit (Tx) differential pairs used for transporting pixel and framing data from the display engine in two display configurations. In three display configurations Channel A has 4 transmit (Tx) differential pairs while Channel B and C have two transmit (Tx) differential pairs.

• Each channel has four transmit (Tx) differential pairs used for transporting pixel and framing data from the display engine

• Each channel has one single-ended LineSync and one FrameSync input (1-V CMOS signaling)

• One display interrupt line input (1-V CMOS signaling)

• Intel FDI may dynamically scale down to 2X or 1X based on actual display bandwidth requirements

• Common 100-MHz reference clock

• Each channel transports at a rate of 2.7 Gbps

• PCH supports end-to-end lane reversal across both channels (no reversal support required in the processor)

2.4.4 Multi Graphics Controllers Multi-Monitor Support

The processor supports simultaneous use of the Processor Graphics Controller (GT) and a x16 PCI Express* Graphics (PEG) device.

The processor supports a maximum of 2 displays connected to the PEG card in parallel with up to 2 displays connected to the processor and PCH.

Note: When supporting Multi Graphics Multi Monitors, “drag and drop” between monitors and

the 2x8 PEG is not supported.

Datasheet, Volume 1 37

Interfaces

2.5 Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between a PECI client (processor) and a PECI master. The processor implements a PECI interface to:

• Allow communication of processor thermal and other information to the PECI master.

• Read averaged Digital Thermal Sensor (DTS) values for fan speed control.

2.6 Interface Clocking

2.6.1 Internal Clocking Requirements

Table 2-5. Reference Clock

Reference Input Clock Input Frequency Associated PLL

BCLK[0]/BCLK#[0] 100 MHz Processor/Memory/Graphics/PCIe/DMI/FDI

§ §

38 Datasheet, Volume 1

Technologies

3 Technologies

This chapter provides a high-level description of Intel technologies implemented in the processor.

The implementation of the features may vary between the processor SKUs. Details on the different technologies of Intel processors and other relevant external

notes are located at the Intel technology web site: http://www.intel.com/technology/.

3.1 Intel® Virtualization Technology (Intel® VT)

Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets. Intel

(Intel performance and robustness. Intel Virtualization Technology for Directed I/O (Intel VTd) adds chipset hardware implementation to support and improve I/O virtualization performance and robustness.

Intel VT-x specifications and functional descriptions are included in the Intel IA-32 Architectures Software Developer’s Manual, Volume 3B and is available at:

http://www.intel.com/products/processor/manuals/index.htm

VT-x) added hardware support in the processor to improve the virtualization

Virtualization Technology for IA-32, Intel® 64 and Intel® Architecture

64 and

Other Intel VT documents can be referenced at:

http://www.intel.com/technology/virtualization/index.htm

3.1.1 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture  (Intel® VT-x) Objectives

Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual Machine Monitor (VMM) can use Intel VT-x features to provide improved reliable virtualized platform. By using Intel VT-x, a VMM is:

• Robust: VMMs no longer need to use paravirtualization or binary translation. This means that they will be able to run off-the-shelf operating systems and applications without any special steps.

• Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA x86 processors.

• More reliable: Due to the hardware support, VMMs can now be smaller, less complex, and more efficient. This improves reliability and availability and reduces the potential for software conflicts.

• More secure: The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system.

Datasheet, Volume 1 39

3.1.2 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture  (Intel® VT-x) Features

The processor core supports the following Intel VT-x features:

• Extended Page Tables (EPT) — EPT is hardware assisted page table virtualization

— It eliminates VM exits from guest operating system to the VMM for shadow

page-table maintenance

• Virtual Processor IDs (VPID) — Ability to assign a VM ID to tag processor core hardware structures (such as

TLBs)

— This avoids flushes on VM transitions to give a lower-cost VM transition time

and an overall reduction in virtualization overhead

• Guest Preemption Timer — Mechanism for a VMM to preempt the execution of a guest operating system

after an amount of time specified by the VMM. The VMM sets a timer value before entering a guest.

— The feature aids VMM developers in flexibility and Quality of Service (QoS)

guarantees

• Descriptor-Table Exiting — Descriptor-table exiting allows a VMM to protect a guest operating system from

internal (malicious software based) attack by preventing relocation of key system data structures like IDT (interrupt descriptor table), GDT (global descriptor table), LDT (local descriptor table), and TSS (task segment selector)

— A VMM using this feature can intercept (by a VM exit) attempts to relocate

these data structures and prevent them from being tampered by malicious software

Technologies

3.1.3 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Objectives

The key Intel VT-d objectives are domain-based isolation and hardware-based virtualization. A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated. Virtualization allows for the creation of one or more partitions on a single system. This could be multiple partitions in the same operating system, or there can be multiple operating system instances running on the same system – offering benefits such as system consolidation, legacy migration, activity partitioning, or security.

40 Datasheet, Volume 1

Technologies

3.1.4 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features

The processor supports the following Intel VT-d features:

• Memory controller and processor graphics comply with Intel® VT -d 1.2 specification

•Two VT-d DMA remap engines: —iGFX DMA remap engine

—DMI / PEG

• Support for root entry, context entry, and default context

• 39-bit guest physical address and host physical address widths

• Support for 4K page sizes only

• Support for register-based fault recording only (for single entry only) and support

for MSI interrupts for faults

• Support for both leaf and non-leaf caching

• Support for boot protection of default page table

• Support for non-caching of invalid page table entries

• Support for hardware based flushing of translated but pending writes and pending

reads, on IOTLB invalidation

• Support for page-selective IOTLB invalidation

• MSI cycles (MemWr to address FEEx_xxxxh) not translated — Translation faults result in cycle forwarding to VBIOS region (byte enables

masked for writes). Returned data may be bogus for internal agents, PEG / DMI interfaces return unsupported request status.

• Interrupt Remapping is supported

• Queued invalidation is supported

• VT-d translation bypass address range is supported (Pass Through)

Note: Intel VT-d Technology may not be available on all SKUs.

3.1.5 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features Not Supported

The following features are not supported by the processor with Intel VT-d:

• No support for PCIe* endpoint caching (ATS)

• No support for Intel VT-d read prefetching / snarfing (that is, translations within a cacheline are not stored in an internal buffer for reuse for subsequent translations)

• No support for advance fault reporting

• No support for super pages

• No support for Intel VT-d translation bypass address range (such usage models need to be resolved with VMM help in setting up the page tables correctly)

Datasheet, Volume 1 41

Technologies

3.2 Intel® Trusted Execution Technology (Intel® TXT)

Intel Trusted Execution Technology (Intel TXT) defines platform-level enhancements that provide the building blocks for creating trusted platforms.

The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision. The Intel TXT platform determines the identity of the controlling environment by accurately measuring and verifying the controlling software.

Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment. The Intel TXT platform will resist attempts by software processes to change the controlling environment or bypass the bounds set by the controlling environment.

Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute.

These extensions enhance two areas:

• The launching of the Measured Launched Environment (MLE)

• The protection of the MLE from potential corruption

The enhanced platform provides these launch and control interfaces using Safer Mode Extensions (SMX).

The SMX interface includes the following functions:

• Measured / Verified launch of the MLE

• Mechanisms to ensure the above measurement is protected and stored in a secure location

• Protection mechanisms that allow the MLE to control attempts to modify itself

For more information, refer to the Intel® TXT Measured Launched Environment Developer’s Guide in http://www.intel.com/content/www/us/en/software-

developers/intel-txt-software-development-guide.html.

3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)

The processor supports Intel® Hyper-Threading Technology (Intel® HT Technology) that allows an execution core to function as two logical processors. While some execution resources such as caches, execution units, and buses are shared, each logical processor has its own architectural state with its own set of general-purpose registers and control registers. This feature must be enabled using the BIOS and requires operating system support.

Intel recommends enabling Intel Windows Vista*, Microsoft Windows* XP Professional / Windows* XP Home, and disabling Intel operating systems. For more information on Intel

http://www.intel.com/technology/platform-technology/hyper-threading/.

HT Technology using the BIOS for all previous versions of Windows

HT T echno logy with Microsoft Windows 7*, Microsoft

HT Technology, see

42 Datasheet, Volume 1

Technologies

3.4 Intel® Turbo Boost Technology

Intel® Turbo Boost Technology is a feature that allows the processor core to opportunistically and automatically run faster than its rated operating frequency/render clock if it is operating below power, temperature, and current limits. The Intel Turbo Boost Technology feature is designed to increase performance of both multi-threaded and single-threaded workloads. Maximum frequency is dependant on the SKU and number of active cores. No special hardware support is necessary for Intel Turbo Boost Technology. BIOS and the operating system can enable or disable Intel Turbo Boost Technology. Intel Turbo Boost Technology will increase the ratio of application power to TDP. Thus, thermal solutions and platform cooling that are designed to less than thermal design guidance might experience thermal and performance issues since more applications will tend to run at the maximum power limit for significant periods of time.

Note: Intel Turbo Boost Technology may not be available on all SKUs.

3.4.1 Intel® Turbo Boost Technology Frequency

The processor’s rated frequency assumes that all execution cores are running an application at the thermal design power (TDP). However, under typical operation, not all cores are active. Therefore most applications are consuming less than the TDP at the rated frequency . To take advantage of the available thermal headroom, the active cores can increase their operating frequency.

To determine the highest performance frequency amongst active cores, the processor takes the following into consideration:

• The number of cores operating in the C0 state

• The estimated current consumption

• The estimated power consumption

•The temperature

Any of these factors can affect the maximum frequency for a given workload. If the power, current, or thermal limit is reached, the processor will automatically reduce the frequency to stay with its TDP limit.

Note: Intel Turbo Boost Technology processor frequencies are only active if the operating

system is requesting the P0 state. For more information on P-states and C -states, refer

Chapter 4.

3.4.2 Intel® Turbo Boost Technology Graphics Frequency

Graphics render frequency is selected by the processor dynamically based on graphics workload demand. The processor can optimize both processor and Processor Graphics performance by managing power for the overall package. For the integrated graphics, this allows an increase in the render core frequency and increased graphics performance for graphics intensive workloads. In addition, during processor intensive workloads when the graphics power is low, the processor core can increase its frequency higher within the package power limit. Enabling Intel Turbo Boost Technology will maximize the performance of the processor core and the graphics render frequency within the specified package power levels.

Datasheet, Volume 1 43

Technologies

3.5 Intel® Advanced Vector Extensions (Intel® AVX)

Intel Advanced Vector Extensions (Intel AVX) is the latest expansion of the Intel instruction set. It extends the Intel Streaming SIMD Extensions (Intel SSE) from 128bit vectors to 256-bit vectors. Intel AVX addresses the continued need for vector floating-point performance in mainstream scientific and engineering numerical applications, visual processing, recognition, data-mining / synthesis, gaming, physics, cryptography and other application areas.

The enhancement in Intel AVX allows for improved performance due to wider vectors, new extensible syntax, and rich functionality including the ability to better manage, rearrange, and sort data. In the processor, new instructions were added to allow graphics, media and imaging applications to speed up the processing of large amount of data by reducing the memory bandwidth and footprint. The new instructions convert operands between single-precision floating point values and half-precision (16 bit) floating point values.

For more information on Intel AVX, see http://www.intel.com/software/avx.

3.6 Security and Cryptography Technologies

3.6.1 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)

The processor supports Intel Advanced Encryption Standard New Instructions (Intel AES-NI) that are a set of Single Instruction Multiple Data (SIMD) instructions that enable fast and secure data encryption and decryption based on the Advanced Encryption Standard (AES). Intel AES-NI are valuable for a wide range of cryptographic applications, for example: applications that perform bulk encryption / decryption, authentication, random number generation, and authenticated encryption. AES is broadly accepted as the standard for both government and industry applications, and is widely deployed in various protocols.

AES-NI consists of six Intel SSE instructions. Four instructions, namely AESENC, AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption and decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key expansion procedure. To gether, these instructions provide a full hardware for support AES, offering security, high performance, and a great deal of flexibility.

3.6.2 PCLMULQDQ Instruction

The processor supports the carry-less multiplication instruction, PCLMULQDQ. PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the 128-bit carry-less multiplication of two, 64-bit operands without generating and propagating carries. Carry-less multiplication is an essential processing component of several cryptographic systems and standards. Hence, accelerating carry-less multiplication can significantly contribute to achieving high speed secure computing and communication.

44 Datasheet, Volume 1

Technologies

3.6.3 RDRAND Instruction

The processor introduces a software visible random number generation mechanism supported by a high quality entropy source. This capability will be made available to programmers through the new RDRAND instruction. The resultant random number generation capability is designed to comply with existing industry standards in this regard (ANSI X9.82 and NIST SP 800-90).

Some possible usages of the new RDRAND instruction include cryptographic key generation as used in a variety of applications including communication, digital signatures, secure storage, and so on.

3.7 Intel® 64 Architecture x2APIC

The Intel x2APIC architecture extends the xAPIC architecture that provides key mechanism for interrupt delivery. This extension is intended primarily to increase processor addressability.

Specifically, x2APIC:

• Retains all key elements of compatibility to the xAPIC architecture: — delivery modes

— interrupt and processor priorities — interrupt sources — interrupt destination types

• Provides extensions to scale processor addressability for both the logical and

physical destination modes

• Adds new features to enhance performance of interrupt delivery

• Reduces complexity of logical destination mode interrupt delivery on link based

architectures

The key enhancements provided by the x2APIC architecture over xAPIC are the following:

• Support for two modes of operation to provide backward compatibility and

extensibility for future platform innovations:

— In xAPIC compatibility mode, APIC registers are accessed through memory

mapped interface to a 4

— In x2APIC mode, APIC registers are accessed through Model Specific Register

(MSR) interfaces. In this mode, the x2APIC architecture provides significantly increased processor addressability and some enhancements on interrupt delivery.

• Increased range of processor addressability in x2APIC mode: — Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt

processor addressability up to 4 A processor implementation of x2APIC architecture can support fewer than

bits in a software transparent fashion.

— Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical x2APIC

ID is partitioned into two sub-fields – a 16-bit cluster ID and a 16-bit logical ID within the cluster. Consequently, ((2^20) -16) processors can be addressed in logical destination mode. Processor implementations can support fewer than 16

bits in the cluster ID sub-field and logical ID sub-field in a software agnostic

fashion.

Datasheet, Volume 1 45

KB page, identical to the xAPIC architecture.

GB-1 processors in physical destination mode.

• More efficient MSR interface to access APIC registers. — To enhance inter-processor and self directed interrupt delivery as well as the

ability to virtualize the local APIC, the APIC register set can be accessed only through MSR based interfaces in the x2APIC mode. The Memory Mapped IO (MMIO) interface used by xAPIC is not supported in the x2APIC mode.

• The semantics for accessing APIC registers have been revised to simplify the

programming of frequently-used APIC registers by system software. Specifically the software semantics for using the Interrupt Command Register (ICR) and End Of Interrupt (EOI) registers have been modified to allow for more efficient delivery and dispatching of interrupts.

The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the “x2APIC” mode. T o benefit from x2APIC capabilities, a new operating system and a new BIOS are both needed, with special support for the x2APIC mode.

The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendibility for future Intel platform innovations.

Note: Intel x2APIC technology may not be available on all SKUs.

For more information, refer to the Intel 64 Architecture x2APIC specification at

http://www.intel.com/products/processor/manuals/

Technologies

3.8 Supervisor Mode Execution Protection (SMEP)

The processor introduces a new mechanism that provides next level of system protection by blocking malicious software attacks from user mode code when the system is running in the highest privilege level.

This technology helps to protect from virus attacks and unwanted code to harm the system.

For more information, please refer to the Intel Developer’s Manual, Volume 3A (see Section 1.8, “Related Documents” on page 22).

64 and IA-32 Architectures Software

3.9 Power Aware Interrupt Routing (PAIR)

The processor added enhanced power-performance technology which routes interrupts to threads or cores based on their sleep states. For example concerning energy savings, it routes the interrupt to the active cores without waking the deep idle cores. For Performance, it routes the interrupt to the idle (C1) cores without interrupting the already heavily loaded cores. This enhancement is mostly beneficial for high interrupt scenarios like Gigabit LAN, WLAN peripherals, and so on.

§ §

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G0 – Working

S0 – CPU Fully powered on

C0 – Active mode

C1 – Auto halt

C1E – Auto halt, low freq, low voltage

C3 – L1/L2 caches flush, clocks off

C6 – save core states before shutdown

G1 – Sleeping

S3 cold – Sleep – Suspend To Ram (STR)

S4 – Hibernate – Suspend To Disk (STD), Wakeup on PCH

S5 – Soft Off – no power, Wakeup on PCH

G3 – Mechanical Off

Note: Power states availability may vary between the different SKUs.

4 Power Management

This chapter provides information on the following power management topics:

• Advanced Configuration and Power Interface (ACPI) States

• Processor Core

• Integrated Memory Controller (IMC)

• PCI Express*

• Direct Media Interface (DMI)

• Processor Graphics Controller

Figure 4-1. Processor Power States

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Power Management

4.1 Advanced Configuration and Power Interface (ACPI) States Supported

The ACPI states supported by the processor are described in this section.

4.1.1 System States

Table 4-1. System States

State Description

G0/S0 Full On

G1/S3-Cold

G1/S4 Suspend-to-Disk (STD). All power lost (except wakeup on PCH). G2/S5 Soft off. All power lost (except wakeup on PCH). Total reboot.

G3 Mechanical off. All power removed from system.

4.1.2 Processor Core / Package Idle States

Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor).

Table 4-2. Processor Core / Package State Support

State Description

C0 Active mode, processor executing code C1 AutoHALT state

C1E AutoHALT state with lowest frequency and voltage operating point

Execution cores in C3 flush their L1 instruction cache, L1 data cache, and L2 cache to the L3 shared cache. Clocks are shut off to each core

Execution cores in this state save the ir architectural state before removing core voltage

4.1.3 Integrated Memory Controller States

Table 4-3. Integrated Memory Controller States

State Description

Power up CKE asserted. Active mode.

Pre-charge Power Down CKE de-asserted (not self-refresh) with all banks closed

Active Power Down CKE de-asserted (not self-refresh) with minimum one bank active

Self-Refresh CKE de-asserted using device self-refresh

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4.1.4 PCI Express* Link States

Table 4-4. PCI Express* Link States

State Description

L0 Full on – Active transfer state.

L0s First Active Power Management low power state – Low exit latency

L1 Lowest Active Power Management – Longer exit latency L3 Lowest power state (po wer-off) – Longest exit latency

4.1.5 Direct Media Interface (DMI) States

Table 4-5. Direct Media Interface (DMI) States

State Description

L0 Full on – Active transfer state

L0s First Active Power Management low power state – Low exit latency

L1 Lowest Active Power Management – Longer exit latency L3 Lowest power state (po wer-off) – Longest exit latency

4.1.6 Processor Graphics Controller States

Table 4-6. Processor Graphics Controller States

State Description

D0 Full on, display active

D3 Cold Power-off

4.1.7 Interface State Combinations

Table 4-7. G, S, and C State Combinations

Global (G)

State

G0 S0 C0 Full On On Full On G0 S0 C1/C1E Auto-Halt On Auto-Halt G0 S0 C3 Deep Sleep On Deep Sleep

G0 S0 C6

G1 S3 Power off Off, except RTC Suspend to RAM G1 S4 Power off Off, except RTC Suspend to Disk G2 S5 Power off Off, except RTC Soft Off G3 NA Power off Power off Hard off

Sleep

(S) State

Processor

Package

Processor

State

Deep Power

Down

System Clocks Description

Deep Power Down

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4.2 Processor Core Power Management

While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-state. When the processor is not executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power C-states have longer entry and exit latencies.

4.2.1 Enhanced Intel® SpeedStep® Technology

The following are the key features of Enhanced Intel SpeedStep Technology:

• Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states.

• Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor cores.

— If the target frequency is higher than the current frequency, VCC is ramped up

in steps to an optimized voltage. This voltage is signaled by the SVID bus to the voltage regulator. Once the voltage is established, the PLL locks on to the target frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the

target frequency, then transitions to a lower voltage by signaling the target voltage on SVID bus.

— All active processor cores share the same frequency and voltage. In a multi-

core processor, the highest frequency P-state requested amongst all active cores is selected.

— Software-requested transitions are accepted at any time. If a previous

transition is in progress, the new transition is deferred until the previous transition is completed.

• The processor controls voltage ramp rates internally to ensure glitch-free transitions.

• Because there is low transition latency between P-states, a significant number of transitions per-second are possible.

Power Management

4.2.2 Low-Power Idle States

When the processor is idle, low-power idle states (C-states) are used to save power. More power savings actions are taken for numerically higher C-states. However, higher C-states have longer exit and entry latencies. Resolution of C-states occur at the thread, processor core, and processor package level. Thread-level C-states are available if Intel

Caution: Long term reliability cannot be assured unless all the Low Power Idle States are

enabled.

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Power Management

Processor Package State

Core 1 State

Thread 1Thread 0

Core 0 State

Thread 1Thread 0

C1 C1E C6C3

MWAIT(C1), HLT

MWAIT(C6),

P_LVL3 I/O Read

MWAIT(C3),

P_LV2 I/O Read

MWAIT(C1), HLT

(C1E Enabled)

Figure 4-2. Idle Power Management Breakdown of the Processor Cores

Entry and exit of the C-States at the thread and core level are shown in Figure 4-3.

Figure 4-3. Thread and Core C-State Entry and Exit

While individual threads can request low power C-states, power saving actions only take place once the core C-state is resolved. Core C-states are automatically resolved by the processor. For thread and core C-states, a transition to and from C0 is required before entering any other C-state.

Table 4-8. Coordination of Thread Power States at the Core Level

Processor Core

C-State

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Thread 0

Note: If enabled, the core C-state will be C1E if all enabled cores have also resolved a core C1 state or higher.

C0 C0 C0 C0 C0 C1 C0 C1 C3 C0 C1 C6 C0 C1

Thread 1

C0 C1 C3 C6

1 1 1

C3 C3 C3 C6

4.2.3 Requesting Low-Power Idle States

The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E). However, software may make C-state requests using the legacy method of I/O reads from the ACPI-defined processor clock control registers, referred to as P_LVLx. This method of requesting C-states provides legacy support for operating systems that initiate C-state transitions using I/O reads.

To seamle ss support of legacy operating systems, P_LVLx I/O reads are converted within the processor to the equivalent MWAIT C-state request. Therefore, P_L VLx reads do not directly result in I/O reads to the system. The feature, known as I/O MWAIT redirection, must be enabled in the BIOS.

Power Management

Note: The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read

interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as shown in

Table 4-9.

Table 4-9. P_LVLx to MWAIT Conversion

P_LVLx MWAIT(Cx) Notes

P_LVL2 MWAIT(C3) P_LVL3 MWAIT(C6) C6. No sub-states allowed.

The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any P_LVLx reads outside of this r ange does not cause an I/O redirection to an MWAIT(Cx)like request. They fall through like a normal I/O instruction.

Note: When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The

MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_L VLx I/O redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS.IF.

4.2.4 Core C-states

The following are general rules for all core C-states, unless specified otherwise:

• A core C-State is determined by the lowest numerical thread state (such as Thread 0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See

Table 4-7.

• A core transitions to C0 state when:

— An interrupt occurs — There is an access to the monitored address if the state was entered using an

MWAIT instruction

• For core C1/C1E, core C3, and core C6, an interrupt directed toward a single thread wakes only that thread. However, since both threads are no longer at the same core C-state, the core resolves to C0.

• A system reset re-initializes all processor cores

4.2.4.1 Core C0 State

The normal operating state of a core where code is being executed.

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4.2.4.2 Core C1 / C1E State

C1/C1E is a low power state entered when all threads within a core execute a HLT or MWAIT(C1/C1E) instruction.

A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.

While a core is in C1/C1E state, it processes bus snoops and snoops from other threads. For more information on C1E, see “Package C1/C1E”.

4.2.4.3 Core C3 State

Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while maintaining its architectural state. All core clocks are stopped at this point. Because the core’s caches are flushed, the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory.

4.2.4.4 Core C6 State

Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an MWAIT(C6) instruction. Before entering core C6, the core will save its architectural state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts. During exit, the core is powered on and its architectural state is restored.

4.2.4.5 C-State Auto-Demotion

In general, deeper C-states such as C6 have long latencies and have higher energy entry / exit costs. The resulting performance and energy penalties become significant when the entry / exit frequency of a deeper C-state is high. Therefore, incorrect or inefficient usage of deeper C-states have a negative impact on idle power. To increase residency and improve idle power in deeper C-states, the processor supports C-state auto-demotion.

64 and IA-32 Architecture Software

There are two C-State auto-demotion options:

•C6 to C3

• C6/C3 To C1

The decision to demote a core from C6 to C3 or C3/C6to C1 is based on each core’s immediate residency history. Upon each core C6 request, the core C-state is demoted to C3 or C1 until a sufficient amount of residency has been established. At that point, a core is allowed to go into C3/C6. Each option can be run concurrently or individually.

This feature is disabled by default. BIOS must enable it in the PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by this register.

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4.2.5 Package C-States

The processor supports C0, C1/C1E, C3, and C6 power states. The following is a summary of the general rules for package C-state entry. These apply to all package Cstates unless specified otherwise:

• A package C-state request is determined by the lowest numerical core C-state amongst all cores.

• A package C-state is automatically resolved by the processor depending on the core idle power states and the status of the platform components.

— Each core can be at a lower idle power state than the package if the platform

does not grant the processor permission to enter a requested package C-state.

— The platform may allow additional power savings to be realized in the

processor.

— For package C-states, the processor is not required to enter C0 before entering

any other C-state.

The processor exits a package C-state when a break event is detected. Depending on the type of break event, the processor does the following:

• If a core break event is received, the target core is activated and the break event message is forwarded to the target core.

— If the break event is not masked, the target core enters the core C0 state and

the processor enters package C0.

• If the break event was due to a memory access or snoop request.

— But the platform did not request to keep the processor in a higher package C-

state, the package returns to its previous C-state.

— And the platform requests a higher power C-state, the memory access or snoop

request is serviced and the package remains in the higher power C-state.

Power Management

Table 4-10 shows package C-state resolution for a dual-core processor. Figure 4-4

summarizes package C-state transitions.

Table 4-10. Coordination of Core Power States at the Package Level

Package C-State

C0 C0 C0 C0 C0

Core 0

Note: If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher.

54 Datasheet, Volume 1

C1 C0 C1 C3 C0 C1 C6 C0 C1

C0 C1 C3 C6

Core 1

1 1 1

C3 C3 C3 C6

Power Management

Figure 4-4. Package C-State Entry and Exit

4.2.5.1 Package C0

Package C0 is the normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be in lower power idle states while the package is in C0.

4.2.5.2 Package C1/C1E

No additional power reduction actions are taken in the package C1 state. However, if the C1E sub-state is enabled, the processor automatically transitions to the lowest supported core clock frequency, followed by a reduction in voltage.

The package enters the C1 low power state when:

• At least one core is in the C1 state

• The other cores are in a C1 or lower power state

The package enters the C1E state when:

• All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint

• All cores are in a power state lower that C1/C1E but the package low power state is limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR

• All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is enabled in IA32_MISC_ENABLES

No notification to the system occurs upon entry to C1/C1E.

Datasheet, Volume 1 55

4.2.5.3 Packa ge C3 State

A processor enters the package C3 low power state when:

• At least one core is in the C3 state

• The other cores are in a C3 or lower power state, and the processor has been granted permission by the platform

• The platform has not granted a request to a package C6 state but has allowed a package C6 state

In package C3-state, the L3 shared cache is valid.

4.2.5.4 Packa ge C6 State

A processor enters the package C6 low power state when:

• At least one core is in the C6 state

• The other cores are in a C6 or lower power state and the processor has been granted permission by the platform

In package C6 state, all cores have saved their architectural state and have had their core voltages reduced to zero volts. The L3 shared cache is still powered and snoopable in this state. The processor remains in package C6 state as long as any part of the L3 cache is active.

Power Management

4.3 Integrated Memory Controller (IMC) Power Management

The main memory is power managed during normal operation and in low-power ACPI Cx states.

4.3.1 Disabling Unused System Memory Outputs

Any System Memory (SM) interface signal that goes to a memory module connector in which it is not connected to any actual memory devices (such as SO-DIMM connector is unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM signals are:

• Reduced power consumption

• Reduced possible overshoot/undershoot signal quality issues seen by the processor I/O buffer receivers caused by reflections from potentially un-terminated transmission lines

When a given rank is not populated, the corresponding chip select and CKE signals are not driven.

At reset, all rows must be assumed to be populated, until it can be proven that they are not populated. This is due to the fact that when CKE is tri-stated with a SO-DIMM present, the SO-DIMM is not ensured to maintain data integrity.

SCKE tri-state should be enabled by BIOS where appropriate, since at reset all rows must be assumed to be populated.

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4.3.2 DRAM Power Management and Initialization

The processor implements extensive support for power management on the SDRAM interface. There are four SDRAM operations associated with the Clock Enable (CKE) signals that the SDRAM controller supports. The processor drives four CKE pins to perform these operations.

The CKE is one means of power saving. When CKE is off, the internal DDR clock is disabled and the DDR power is reduced. The power-saving differs according to the selected mode and the DDR type used. For more information, refer to the IDD table in the DDR specification.

The DDR defines 3 levels of power down that differ in power saving and in wakeup time:

1. Active power down (APD): This mode is entered if there are open pages when deasserting CKE. In this mode the open pages are retained . Power-saving in this mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this mode is defined by tXP – small number of cycles.

2. Precharged power down (PPD): This mode is entered if all banks in DDR are precharged when de-asserting CKE. Power-saving in this mode is intermediate – better than APD, but less than DLL-off. Power consumption is defined by IDD2P1. Exiting this mode is defined by tXP. The difference relative to APD mode is that when waking-up in PPD mode, all page-buffers are empty.

3. DLL -off: In this mode the data-in DLLs on DDR are off . P ower-saving in this mode is the best among all power modes. Power consumption is defined by IDD2P1. Exiting this mode is defined by tXP and tXPDLL (10–20 according to the DDR type) until first data transfer is allowed.

The processor supports 6 different types of power down. The different modes are the power down modes supported by DDR3 and combinations of these. The type of CKE power down is defined by configuration. The options are as follows:

1. No power down

2. APD: The rank enters power down as soon as the idle-timer expires, independent of the bank status

3. PPD: When idle timer expires, the MC sends PRE-all to rank and then enters power down

4. DLL-off: Same as option 2 but DDR is configured to DLL-off

5. APD, change to PPD (APD-PPD): Begins as option 1, and when all page-close timers of the rank are expired, it wakes the rank, issues PRE-all, and returns to PPD.

6. APD, change to DLL-off (APD_DLLoff): Begins as option 1, and when all page-close timers of the rank are expired, it wakes the rank, issues PRE-all, and returns to DLL-off power down.

The CKE is determined per rank, when it is inactive. Each rank has an idle counter. The idle counter starts counting as soon as the rank has no accesses, and if it expires, the rank may enter power down while no new transactions to the rank arrive to queues. The idle counter begins counting at the last incoming transaction arrival.

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It is important to understand that since the power down decision is per rank, the MC can find a lot of opportunities to power down ranks, even while running memory intensive applications; savings may be significant (up to a few Watts, depending on DDR configuration). This becomes more significant when each channel is populated with more ranks.

Selection of power modes should be according to power performance or thermal tradeoffs of a given system:

• When trying to achieve maximum performance and power or thermal consideration is a non-issue, use no power down.

• In a system that tries to minimize power-consumption, try to use the deepest power down mode possible – DLL-off or APD_DLLoff.

• In high-performance systems with dense packaging (that is, tricky thermal design) the power down mode should be considered in order to reduce the heating and avoid DDR throttling caused by the heating.

Control of the power-mode through CRB-BIOS: BIOS selects by default no-power down.

Another control is the idle timer expiration count. This is set through PM_PDWN_config bits 7:0 (MCHBAR +4CB0). As this timer is set to a shorter time, the IMC will have more opportunities to put DDR in power down. The minimum recommended value for this register is 15. There is no BIOS hook to set this register. Customers who choose to change the value of this register can do it by changing the BIOS. For experiments, this register can be modified in real time if BIOS did not lock the MC registers.

Note: In APD, APD-PPD, and APD-DLLoff there is no point in setting the idle counter in the

same range of page-close idle timer. Another option associated with CKE power down is the S_DLL-off. When this option is

enabled, the SBR I/O slave DLLs go off when all channel ranks are in power down. (Do not confuse it with the DLL-off mode, in which the DDR DLLs are off). This mode requires an I/O slave DLL wakeup time be defined.

4.3.2.1 Initialization Role of CKE

During power-up, CKE is the only input to the SDRAM that has its level recognized (other than the DDR3 reset pin) once power is applied. The signal must be driven LOW by the DDR controller to make sure the SDRAM components float DQ and DQS during power-up. CKE signals remain LOW (while any reset is active) until the BIOS writes to a configuration register. Using this method, CKE is ensured to remain inactive for much longer than the specified 200 s after power and clocks to SDRAM devices are stable.

4.3.2.2 Conditional Self-Ref resh

Intel® Rapid Memory Power Management (Intel® RMPM) conditionally places memory into self-refresh in the package C3 and C6 low-power states. Intel RMPM functionality depends on graphics/display state (relevant only when processor graphics is being used), as well as memory traffic patterns generated by other connected I/O devices.

When entering the S3 - Suspend-to-RAM (STR) state or S0 conditional self-refresh, the processor core flushes pending cycles and then enters all SDRAM ranks into self refresh. the CKE signals remain LOW so the SDRAM devices perform self-refresh.

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The target behavior is to enter self-refresh for the package C3 and C6 states as long as there are no memory requests to service.

4.3.2.3 Dynamic Power Down Operation

Dynamic power down of memory is employed during normal operation. Based on idle conditions, a given memory rank may be powered down. The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power down state. The processor core controller can be configured to put the devices in active power down (CKE de-assertion with open pages) or precharge power down (CKE de-assertion with all pages closed). Precharge power down provides greater power savings but has a bigger performance impact, since all pages will first be closed before putting the devices in power down mode.

If dynamic power down is enabled, all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh.

4.3.2.4 DRAM I/O Power Management

Unused signals should be disabled to save power and reduce electromagnetic interference. This includes all signals associated with an unused memory channel. Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SODIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.

The I/O buffer for an unused signal should be tri-stated (output driver disabled), the input receiver (differential sense-amp) should be disabled, and any DLL circuitry related ONLY to unused signals should be disabled. The input path must be gated to prevent spurious results due to noise on the unused signals (typically handled automatically when input receiver is disabled).

4.3.3 DDR Electrical Power Gating (EPG)

The DDR I/O of the processor supports on-die Electrical Power Gating (DDR-EPG) during normal operation (S0 mode) while t he processor is at package C3 or deeper power state.

During EPG, the V un-gated V

will stay powered on.

CCIO

The processor will transition in and out of DDR EPG mode on an as needed basis without any external pins or signals.

There is no change to the signals driven by the processor to the DIMMs during DDR IO EPG mode.

During EPG mode, all the DDR IO logic will be powered down, except for the Physical Control registers that are powered by the un-gated V

Unlike S3 exit, at DDR EPG exit, the DDR will not go through training mode. Rather, it will use the previous training information retained in the physical control registers and will immediately resume normal operation.

internal voltage rail will be powered down, while V

CCIO

power supply.

CCIO

DDQ

and the

Datasheet, Volume 1 59

Power Management

4.4 PCI Express* Power Management

• Active power management support using L0s and L1 states.

• All inputs and outputs disabled in L2/L3 Ready state.

Note: PCIe* interface does not support Hot-Plug. Note: An increase in power consumption may be observed when PCIe Active State Power

Management (ASPM) capabilities are disabled.

4.5 DMI Power Management

• Active power management support using L0s/L1 state.

4.6 Graphics Power Management

4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)  (also known as CxSR)

The Intel Rapid Memory Power Management (Intel RMPM) puts rows of memory into self-refresh mode during C3/C6 to allow the system to remain in the lower power states longer. Processors routinely save power during runtime conditions by entering the C3, C6 state. Intel RMPM is an indirect method of power saving that can have a significant effect on the system as a whole.

4.6.2 Intel® Graphics Performance Modulation Technology (Intel® GPMT)

Intel Graphics Power Modulation Technology (Intel® GPMT) is a method for saving power in the graphics adapter while continuing to display and process data in the adapter. This method will switch the render frequency and/or render voltage dynamically between higher and lower power states supported on the platform based on render engine workload.

In products where Intel Technology) is supported and enabled, the functionality of Intel GPMT will be maintained by Intel Graphics Dynamic Frequency (also known as Turbo Boost Technology).

Graphics Dynamic Frequency (also known as Turbo Boost

4.6.3 Graphics Render C-State

Render C-State (RC6) is a technique designed to optimize the average power to the graphics render engine during times of idleness of the render engine. Render C-state is entered when the graphics render engine, blitter engine and the video engine have no workload being currently worked on and no outstanding graphics memory tr ansactions. When the idleness condition is met then the Processor Graphics will program the VR into a low voltage state (~0 V) through the SVID bus.

Caution: Long term reliability cannot be assured unless all the Low Power Idle States are

60 Datasheet, Volume 1

enabled.

Power Management

4.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)

Intel S2DDT reduces display refresh memory traffic by reducing memory reads required for display refresh. Power consumption is reduced by less accesses to the IMC. S2DDT is only enabled in single pipe mode.

Intel S2DDT is most effective with:

• Display images well suited to compression, such as text windows, slide shows, and so on. Poor examples are 3D games.

• Static screens such as screens with significant portions of the background showing 2D applications, processor benchmarks, and so on, or conditions when the processor is idle. Poor examples are full-screen 3D games and benchmarks that flip the display image at or near display refresh rates.

4.6.5 Intel® Graphics Dynamic Frequency

Intel Graphics Dynamic Frequency Technology is the ability of the processor and graphics cores to opportunistically increase frequency and/or voltage above the ensured processor and graphics frequency for the given part. Intel Graphics Dynamic Frequency Technology is a performance feature that makes use of unused package power and thermals to increase application performance. The increase in frequency is determined by how much power and thermal budget is available in the package, and the application demand for additional processor or graphics performance. The processor core control is maintained by an embedded controller. The graphics driver dynamically adjusts between P-States to maintain optimal performance, power, and thermals.

4.7 Graphics Thermal Power Management

See Section 4.6 for all graphics thermal power management-related features.

§ §

Datasheet, Volume 1 61

Power Management

62 Datasheet, Volume 1

Thermal Management

5 Thermal Management

For thermal specifications and design guidelines refer to the Desktop 3rd Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor, Desktop Intel® Celeron® Processor, and LGA1155 Socket Thermal and Mechanical Specifications and Design Guidelines.

§ §

Datasheet, Volume 1 63

Thermal Management

64 Datasheet, Volume 1

Signal Description

6 Signal Description

This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. Th e following notations are used to describe the signal type.

Notations Signal Type

I Input Signal

OOutput Signal

I/O Bi-directional Input/Output Signal

The signal description also includes the type of buffer used for the particular signal (see Table 6-1).

Table 6-1. Signal Description Buffer Types

Signal Description

PCI Express*

DMI

CMOS CMOS buffers. DDR3 DDR3 buffers: 1.5-V tolerant

Ref Voltage reference signal

Asynchronous

PCI Express* interface signals. These signals are compatible with PCI Express* 3.0 Signalling Environment AC Specifications and are AC coupled. The buffers are not 

3.3-V tolerant. Refer to the PCIe specification. Direct Media Interface signals. These signals are compatible with PCI Express* 2.0

Signaling Environment AC Specifications, but are DC coupled. The buffers are not 

3.3-V tolerant.

Analog reference or output. May be used as a threshold voltage or for buffer compensation

Signal has no timing relationship with any reference clock.

Note:

1. Qualifier for a buffer type.

Datasheet, Volume 1 65

6.1 System Memory Interface Signals

Table 6-2. Memory Channel A Signals

Signal Description

Signal Name Description

SA_BS[2:0]

SA_WE#

SA_RAS#

SA_CAS#

SA_DQS[8:0]

SA_DQS#[8:0]

SA_DQ[63:0]

SA_MA[15:0]

SA_CK[3:0]

SA_CK#[3:0]

SA_CKE[3:0]

SA_CS#[3:0]

SA_ODT[3:0]

Bank Select: These signals define which banks are selected within each SDRAM rank.

Write Enable Control Signal: This signal is used with SA_RAS# and SA_CAS# (along with SA_CS#) to define the SDRAM Commands.

RAS Control Signal: This signal is used with SA_CAS# and SA_WE# (along with SA_CS#) to define the SRAM Commands.

CAS Control Signal: This signal is used with SA_RAS# and SA_WE# (along with SA_CS#) to define the SRAM Commands.

Data Strobes: SA_DQS[8:0] and its complement signal group make up a differential strobe pair. The data is captured at the crossing point of SA_DQS[8:0] and its SA_DQS#[8:0] during read and write transactions.

Data Bus: Channel A data signal interface to the SDRAM data bus. I/O

Memory Address: These signals are used to provide the multiplexed

row and column address to the SDRAM. SDRAM Differential Clock: Channel A SDRAM Differential clock signal

pair. The crossing of the positive edge of SA_CK and the negative edge of its complement SA_CK# are used to sample the command and control signals on the SDRAM.

Clock Enable: (1 per rank). These signals are used to:

• Initialize the SDRAMs during power-up.

•Power down SDRAM ranks.

• Place all SDRAM ranks into and out of self-refresh during STR.

Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank.

On Die Termination: Active Term ination Control. O

Direction/

Buffer Type

DDR3

I/O

DDR3

66 Datasheet, Volume 1

Signal Description

Table 6-3. Memory Channel B Signals

Signal Name Description

SB_BS[2:0]

SB_WE#

SB_RAS#

SB_CAS#

SB_DQS[8:0]

SB_DQS#[8:0]

SB_DQ[63:0]

SB_MA[15:0]

SB_CK[3:0]

SB_CK#[3:0]

SB_CKE[3:0]

SB_CS#[3:0]

SB_ODT[3:0]

Bank Select: These signals define which banks are selected within each SDRAM rank.

Write Enable Control Signal: This signal is used with SB_RAS# and SB_CAS# (along with SB_CS#) to define the SDRAM Commands.

RAS Control Signal: This signal is used with SB_CAS# and SB_WE# (along with SB_CS#) to define the SRAM Commands.

CAS Control Signal: This signal is used with SB_RAS# and SB_WE# (along with SB_CS#) to define the SRAM Commands.

Data Strobes: SB_DQS[8:0] and its complement signal group make up a differential strobe pair . The data is captur ed at the crossin g point of SB_DQS[8:0] and its SB_DQS#[8:0] during read and write transactions.

Data Bus: Channel B data signal interface to the SDRAM data bus. I/O

Memory Address: These signals are used to provide the multiplexed

row and column address to the SDRAM. SDRAM Differential Clock: Channel B SDRAM Differential clock

signal pair. The crossing of the positive edge of SB_CK and the negative edge of its complement SB_CK# are used to sample the command and control signals on the SDRAM.

Clock Enable: (1 per rank) These signals are used to:

• Initialize the SDRAMs during power-up.

•Power down SDRAM ranks.

• Place all SDRAM ranks into and out of self-refresh during STR.

Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank.

On Die Termination: Active Termination Control. O

Direction/

Buffer Type

DDR3

I/O

DDR3

6.2 Memory Reference and Compensation Signals

Table 6-4. Memory Reference and Compensation

Signal Name Description

SM_VREF

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

Datasheet, Volume 1 67

DDR3 Reference Voltage: This signal is used as a reference voltage to the DDR3 controller.

Memory Channel A/B DIMM DQ Voltage Reference: These output pins are connected to the DIMMs, and are programmed to have a reference voltage with optimized margin.

The nominal source impedance for these pins is 150 The step size is 7.7 mV for DDR3 (with no load).

Direction/

Buffer Type

O A

6.3 Reset and Miscellaneous Signals

Table 6-5. Reset and Miscellaneous Signals

Signal Description

Signal Name Description

Configuration Signals:

The CFG signals have a default value of '1' if not terminated on the board.

• CFG[1:0]: Reserved configuration lane. A test point may be placed on the board for this lane.

• CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.

— 1 = Normal operation — 0 = Lane numbers reversed

• CFG[3]: PCI Express* Static x4 Lane Numbering Reversal.

CFG[17:0]

FC_x

PM_SYNC

RESET#

RSVD

RSVD_NCTF

SM_DRAMRST#

— 1 = Normal operation — 0 = Lane numbers reversed

• CFG[4]: Reserved configuration lane. A test point may be placed on the board for this lane.

• CFG[6:5]: PCI Express* Bifurcation:

— 00 = 1 x8, 2 x4 PCI Express* — 01 = reserved — 10 = 2 x8 PCI Express* — 11 = 1 x16 PCI Express*

• CFG[17:7]: Reserved configuration lanes. A test point may be placed on the board for these pins.

FC signals are signals that are available for compatibility with other processors. A test point may be placed on the board for these pins.

Power Management Sync: A sideband signal to communicate power management status from the platform to the processor.

Platform Reset pin driven by the PCH. I

Reserved: All signals that are RSVD and RSVD_NCTF must be left unconnected on the board.

DDR3 DRAM Reset: Reset signal from processor to DRAM de vices. One common to all channels.

Note 1

Direction/

Buffer Type

CMOS

No Connect

Non-Critical to

Function

CMOS

Note:

1. PCIe* bifurcation support varies with the processor and PCH SKUs used.

68 Datasheet, Volume 1

Signal Description

6.4 PCI Express*-based Interface Signals

Table 6-6. PCI Express* Graphics Interface Signals

Signal Name Description

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX[15:0]

PEG_RX#[15:0]

PE_RX[3:0]

PE_RX#[3:0] PEG_TX[15:0]

PEG_TX#[15:0]

PE_TX[3:0]

PE_TX#[3:0]

Note:

1. PE_TX[3:0]/PE_TX#[3:0] and PE_RX[3:0]/PE_RX#[3:0] signals are only used for platforms that support 20 PCIe lanes. These signals are reserved on Desktop 3rd Generation Intel Core™ i7/i5 processors, Desktop Intel

Pentium® processors and Desktop Intel® Celeron® processors.

PCI Express* Input Current Compensation I

PCI Express* Current Compensation I

PCI Express* Resistance Compensation I

PCI Express* Receive Differential Pair

PCI Express* Transmit Differential Pair

Direction/

Buffer Type

PCI Express*

6.5 Intel® Flexible Display (Intel® FDI) Interface Signals

Table 6-7. Intel® Flexible Display (Intel® FDI) Interface

Signal Name Description

Flexible Display Interface Frame Sync: Pipe A I

FDI0_FSYNC[0]

FDI0_LSYNC[0]

FDI_TX[7:0]

FDI_TX#[7:0]

FDI1_FSYNC[1]

FDI1_LSYNC[1]

FDI_INT

Datasheet, Volume 1 69

Intel

Flexible Display Interface Line Sync: Pipe A I

Intel

Flexible Display Interface Transmit Differential

Pairs

Flexible Display Interface Frame Sync: Pipe B and C I

Intel

Flexible Display Interface Line Sync: Pipe B and C I

Intel

Flexible Display Interface Hot-Plug Interrupt I

Direction/

Buffer Type

CMOS

FDI

CMOS

Asynchronous

CMOS

Signal Description

6.6 Direct Media Interface (DMI) Signals

Table 6-8. Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface

Signal Name Description

DMI_RX[3:0]

DMI_RX#[3:0]

DMI_TX[3:0]

DMI_TX#[3:0]

DMI Input from PCH: Direct Media Interface receive differential pair.

DMI Output to PCH: Direct Media Interface transmit differential pair.

6.7 Phase Lock Loop (PLL) Signals

Table 6-9. Phase Lock Loop (PLL) Signals

Signal Name Description

BCLK

BCLK#

Differential bus clock input to the processor I

6.8 Test Access Points (TAP) Signals

Table 6-10. Test Access Points (TAP) Signals

Signal Name Description

Breakpoint and Performance Monitor Signals: These signals

BPM#[7:0]

BCLK_ITP

BCLK_ITP#

DBR#

PRDY#

PREQ#

TCK

TDI

TDO

TMS

TRST#

are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance.

These signals are connected in parallel to the top side debug probe to enable debug capacities.

DBR# is used only in systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset.

PRDY# is a processor output used by deb ug tools to determine processor debug readiness.

PREQ# is used by debug tools to request debug operation of the processor.

Test Clock: This signal provides the clock input for the processor Test Bus (also known as the Test Access Port). TCK must be driven low or allowed to float during power on Reset.

Test Data In: This signal transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support.

Test Data Out: This signal transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support.

Test Mode Select: A JTAG specification support signal used by debug tools.

Test Reset: This signal resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset.

Direction/

Buffer Type

DMI

Direction/

Buffer Type

Diff Clk

Direction/

Buffer Type

I/O

CMOS

Asynchronous

CMOS

Asynchronous

CMOS

Open Drain

CMOS

70 Datasheet, Volume 1

Signal Description

6.9 Error and Thermal Protection Signals

Table 6-11. Error and Thermal Protection Signals

Signal Name Description

Catastrophic Error: This signal indicates that the system has

experienced a catastrophic error and cannot continue to operate. The processor will set this for non-recoverable machine check errors or other unrecoverable internal errors.

CATERR#

PECI

PROCHOT#

THERMTRIP#

On the processor, CATERR# is used for signaling the following types of errors:

• Legacy MCERRs – CATERR# is asserted for 16 BCLKs.

• Legacy IERRs – CATERR# remains asserted until warm or cold reset.

PECI (Platform Environment Control Interface): A serial sideband interface to the processor, it is used primarily for thermal, power, and error management.

Processor Hot: PROCHOT# goes active when the processor temperature monitoring sensor(s) detects that the processor has reached its maximum safe opera ting temperatur e. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. This signal can also be driven to the processor to activate the TCC. Note: Toggling PROCHOT# more than once in 1.5 ms period

Thermal Trip: The processor protects itself from catastrophic overheating by use of an interna l thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 130 °C. This is signaled to the system by the THERMTRIP# signal.

will result in constant Pn state of the processor.

Direction/

Buffer Type

CMOS

I/O

Asynchronous

CMOS Input/

Open-Drain

Output

Asynchronous

CMOS

Datasheet, Volume 1 71

6.10 Power Sequencing Signals

Table 6-12. Power Sequencing Signals

Signal Description

Signal Name Description

SM_DRAMPWROK Processor Input: Connects to PCH

SM_DRAMPWROK

DRAMPWROK.

The processor requires this input signal to be a clean indication

, V

AXG

, and V

UNCOREPWRGOOD

that the V stable and within specifications. This requirement applies regardless of the S-state of the processor. 'Clean' implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. This is connected to the PCH PROCPWRGD signal.

CCSA

CCIO

SKTOCC# (Socket Occupied) : This signal is pulled down

SKTOCC#

directly (0 Ohms) on the processor package to the ground. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present.

Processor Select: This signal is an output that indicates if the

PROC_SEL

processor used is 2nd Generation Intel desktop, Intel Celeron

Intel processor family, Desktop Intel

For 2nd Generation Intel

Intel processor family desktop, the output will be high.

For Desktop 3rd Generation Intel Desktop Intel Celeron

Pentium® processor family desktop, Intel®

processor family desktop or Desktop 3rd Generation

Core™ processor family, Desktop Intel® Pentium®

Core™ processor family desktop,

Pentium® processor family desktop, Intel® Celeron®

Pentiu m® processor family, Desktop Intel®

processor family, the output will be low.

Voltage selection for VCCIO: This output signal was initially intended to select the I/O voltage depending on the processor being used.

voltage is the same for 2nd Generation Intel®

CCIO

Celeron® processor family desktop and

Core™ processor family , Des ktop

VCCIO_SEL

Since the V Core™ processor family desktop, Intel family desktop, Intel Desktop 3rd Generation Intel

Pentium® processor family, Desktop Intel® Celeron®

Intel processor family, the usage of this pin was changed as follows:

The pin is configured on the package to be same as 2nd Generation Intel Pentium family desktop . This pin must be pulled high on the

Core™ processor family desktop, Intel®

processor family desktop, Intel® Celeron® processor

motherboard, when using a dual rail voltage regulator.

, power supplies are

DDQ

Core™ processor family

Celeron® processor family .

Core™ processor family,

Pentium® processor

Direction/

Buffer Type

Asynchronous

CMOS

Asynchronous

CMOS

72 Datasheet, Volume 1

Signal Description

6.11 Processor Power Signals

Table 6-13. Processor Power Signals

Signal Name Description

VCC Processor core power rail. Ref

VCCIO Processor power for I/O. Ref

VDDQ Processor I/O supply voltage for DDR3. Ref

VCCAXG Graphics core power supply. Ref

VCCPLL VCCPLL provides isolated power for internal processor PLLs. Ref

VCCSA System Agent power supply. Ref

VIDSOUT

VIDSCLK

VIDALERT#

VCCSA_VID

Note:

1. The VCCSA_VID can toggle at most once in 500 uS; The slew rate of VCCSA_VID is 1 V/nS.

VIDALERT#, VIDSCLK, and VIDSCLK comprise a three signal serial synchronous interface used to transfer power management information between the processor and the voltage regulator controllers. This serial VID interface replaces the parallel VID interface on previous processors.

Voltage selection for VCCSA: O

6.12 Sense Signals

Table 6-14. Sense Signals

Signal Name Description

VCC_SENSE VSS_SENSE

VAXG_SENSE

VSSAXG_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

VCCSA_SENSE

VCC_SENSE and VSS_SENSE provide an isolated, low impedance connection to the processor core voltage and ground. They can be used to sense or measure voltage near the silicon.

VAXG_SENSE and VSSAXG_SENSE provide an isolated, low impedance connection to the V can be used to sense or measure voltage near the silicon.

VCCIO_SENSE and VSS_SENSE_VCCIO provide an isolated, low impedance connection to the processor VCCIO voltage and ground. They can be used to sense or measure voltage near the silicon.

VCCSA_SENSE provide an isolated, low impedance connection to the processor system agent v oltage. It can be used to sense or measure voltage near the silicon.

voltage and ground. They

AXG

Direction/

Buffer Type

CMOS I/ OD O

OD O

CMOS I

CMOS

Direction/

Buffer Type

Analog

Datasheet, Volume 1 73

Signal Description

6.13 Ground and Non-Critical to Function (NCTF) Signals

Table 6-15. Ground and Non-Critical to Function (NCTF) Signals

Signal Name Description

VSS Processor ground node GND

VSS_NCTF (BGA Only)

Non-Critical to Function: These signals are for package mechanical reliability.

Direction/

Buffer Type

6.14 Processor Internal Pull-Up / Pull-Down Resistors

Table 6-16. Processor Internal Pull-Up / Pull-Down Resistors

Signal Name Pull-Up / Pull-Down Rail Value

BPM[7:0] Pull Up VCCIO 65–165 

PRDY# Pull Up VCCIO 65–165  PREQ# Pull Up VCCIO 65–165 

TCK Pull Down VSS 5–15 k TDI Pull Up VCCIO 5–15 k

TMS Pull Up VCCIO 5–15 k

TRST# Pull Up VCCIO 5–15 k

CFG[17:0] Pull Up VCCIO 5–15 k

§ §

74 Datasheet, Volume 1

Electrical Specifications

7 Electrical Specifications

7.1 Power and Ground Lands

The processor has VCC, VDDQ, VCCPLL, VCCSA, VCCAXG, VCCIO and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to their respective processor power planes, while all VSS lands must be connected to the system ground plane. Use of multiple power and ground planes is recommended to reduce I*R drop. The VCC and VCCAXG lands must be supplied with the voltage determined by the processor Serial Voltage IDentification (SVID) interface. A new serial VID interface is implemented on the processor. Table 7-1 specifies the voltage level for the various VIDs.

7.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low- and full-power states. This may cause voltages on power planes to sag below their minimum values, if bulk decoupling is not adequate. Larger bulk storage (C supply current during longer lasting changes in current demand (for example, coming out of an idle condition). Similarly, capaci tors act as a storage well for current when entering an idle condition from a running condition. To keep voltages within specification, output decoupling must be properly designed.

), such as electrolytic capacitors,

BULK

Caution: Design the board to ensure that the voltage provided to the processor remains within

the specifications listed in reduced lifetime of the processor.

Table 7-4. Failure to do so can result in timing violations or

7.2.1 Voltage Rail Decoupling

The voltage regulator solution needs to provide:

• bulk capacitance with low effective series resistance (ESR)

• a low interconnect resistance from the regulator to the socket

• bulk decoupling to compensate for large current swings generated during poweron, or low-power idle state entry/exit

The power delivery solution must ensure that the voltage and current specifications are met, as defined in Table 7-4.

Datasheet, Volume 1 75

Electrical Specifications

7.3 Processor Clocking (BCLK[0], BCLK#[0])

The processor uses a differential clock to gener ate the processor core operating frequency, memory controller frequency, system agent frequencies, and other internal clocks. The processor core frequency is determined by multiplying the processor core ratio by the BCLK frequency. Clock multiplying within the processor is provided by an internal phase locked loop (PLL) that requires a constant frequency input, with exceptions for Spread Spectrum Clocking (SSC).

The processor’s maximum non-turbo core frequency is configured during power-on reset by using its manufacturing default value. This value is the highest non-turbo core multiplier at which the processor can operate. If lower maximum speeds are desired, the appropriate ratio can be configured using the FLEX_RATIO MSR.

7.3.1 Phase Lock Loop (PLL) Power Supply

An on-die PLL filter solution is implemented on the processor. Refer to Table 7-5 for DC specifications.

7.4 VCC Voltage Identification (VID)

The processor uses three signals for the serial voltage identification interface to support automatic selection of voltages. Table 7-1 specifies the voltage level corresponding to the eight bit VID value transmitted over serial VID. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself. VID signals are CMOS push/pull drivers. Refer to Table 7-8 for the DC specifications for these signals. The VID codes will change due to temperature and/or current load changes to minimize the power of the part. A voltage range is provided in Table 7-4. The specifications are set so that one voltage regulator can operate with all supported frequencies.

Individual processor VID values may be set during manufacturing so that two devices at the same core frequency may have different default VID settings. This is shown in the VID range values in Table 7-4. The processor transitioning to an adjacent VID and its associated voltage. This will represent a DC shift in the loadline.

Note: At condition outside functional operation condition limits, neither functionality nor long

term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded on exposure to conditions exceeding the functional operation condition limits.

provides the ability to operate while

76 Datasheet, Volume 1

Electrical Specifications

Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 1 of 3)

VID7VID6VID5VID4VID3VID2VID1VID

HEX V

CC_MAX

0 0 0 0 0 0 0 0 0 0 0.00000 1 0 0 0 0 0 0 0 8 0 0.88500 0 0 0 0 0 0 0 1 0 1 0.25000 1 0 0 0 0 0 0 1 8 1 0.89000 0 0 0 0 0 0 1 0 0 2 0.25500 1 0 0 0 0 0 1 0 8 2 0.89500 0 0 0 0 0 0 1 1 0 3 0.26000 1 0 0 0 0 0 1 1 8 3 0.90000 0 0 0 0 0 1 0 0 0 4 0.26500 1 0 0 0 0 1 0 0 8 4 0.90500 0 0 0 0 0 1 0 1 0 5 0.27000 1 0 0 0 0 1 0 1 8 5 0.91000 0 0 0 0 0 1 1 0 0 6 0.27500 1 0 0 0 0 1 1 0 8 6 0.91500 0 0 0 0 0 1 1 1 0 7 0.28000 1 0 0 0 0 1 1 1 8 7 0.92000 0 0 0 0 1 0 0 0 0 8 0.28500 1 0 0 0 1 0 0 0 8 8 0.92500 0 0 0 0 1 0 0 1 0 9 0.29000 1 0 0 0 1 0 0 1 8 9 0.93000 0 0 0 0 1 0 1 0 0 A 0.29500 1 0 0 0 1 0 1 0 8 A 0.93500 0 0 0 0 1 0 1 1 0 B 0.30000 1 0 0 0 1 0 1 1 8 B 0.94000 0 0 0 0 1 1 0 0 0 C 0.30500 1 0 0 0 1 1 0 0 8 C 0.94500 0 0 0 0 1 1 0 1 0 D 0.31000 1 0 0 0 1 1 0 1 8 D 0.95000 0 0 0 0 1 1 1 0 0 E 0.31500 1 0 0 0 1 1 1 0 8 E 0.95500 0 0 0 0 1 1 1 1 0 F 0.32000 1 0 0 0 1 1 1 1 8 F 0.96000 0 0 0 1 0 0 0 0 1 0 0.32500 1 0 0 1 0 0 0 0 9 0 0.96500 0 0 0 1 0 0 0 1 1 1 0.33000 1 0 0 1 0 0 0 1 9 1 0.97000 0 0 0 1 0 0 1 0 1 2 0.33500 1 0 0 1 0 0 1 0 9 2 0.97500 0 0 0 1 0 0 1 1 1 3 0.34000 1 0 0 1 0 0 1 1 9 3 0.98000 0 0 0 1 0 1 0 0 1 4 0.34500 1 0 0 1 0 1 0 0 9 4 0.98500 0 0 0 1 0 1 0 1 1 5 0.35000 1 0 0 1 0 1 0 1 9 5 0.99000 0 0 0 1 0 1 1 0 1 6 0.35500 1 0 0 1 0 1 1 0 9 6 0.99500 0 0 0 1 0 1 1 1 1 7 0.36000 1 0 0 1 0 1 1 1 9 7 1.00000 0 0 0 1 1 0 0 0 1 8 0.36500 1 0 0 1 1 0 0 0 9 8 1.00500 0 0 0 1 1 0 0 1 1 9 0.37000 1 0 0 1 1 0 0 1 9 9 1.01000 0 0 0 1 1 0 1 0 1 A 0.37500 1 0 0 1 1 0 1 0 9 A 1.01500 0 0 0 1 1 0 1 1 1 B 0.38000 1 0 0 1 1 0 1 1 9 B 1.02000 0 0 0 1 1 1 0 0 1 C 0.38500 1 0 0 1 1 1 0 0 9 C 1.02500 0 0 0 1 1 1 0 1 1 D 0.39000 1 0 0 1 1 1 0 1 9 D 1.03000 0 0 0 1 1 1 1 0 1 E 0.39500 1 0 0 1 1 1 1 0 9 E 1.03500 0 0 0 1 1 1 1 1 1 F 0.40000 1 0 0 1 1 1 1 1 9 F 1.04000 0 0 1 0 0 0 0 0 2 0 0.40500 1 0 1 0 0 0 0 0 A 0 1.04500 0 0 1 0 0 0 0 1 2 1 0.41000 1 0 1 0 0 0 0 1 A 1 1.05000 0 0 1 0 0 0 1 0 2 2 0.41500 1 0 1 0 0 0 1 0 A 2 1.05500 0 0 1 0 0 0 1 1 2 3 0.42000 1 0 1 0 0 0 1 1 A 3 1.06000 0 0 1 0 0 1 0 0 2 4 0.42500 1 0 1 0 0 1 0 0 A 4 1.06500 0 0 1 0 0 1 0 1 2 5 0.43000 1 0 1 0 0 1 0 1 A 5 1.07000 0 0 1 0 0 1 1 0 2 6 0.43500 1 0 1 0 0 1 1 0 A 6 1.07500 0 0 1 0 0 1 1 1 2 7 0.44000 1 0 1 0 0 1 1 1 A 7 1.08000 0 0 1 0 1 0 0 0 2 8 0.44500 1 0 1 0 1 0 0 0 A 8 1.08500 0 0 1 0 1 0 0 1 2 9 0.45000 1 0 1 0 1 0 0 1 A 9 1.09000 0 0 1 0 1 0 1 0 2 A 0.45500 1 0 1 0 1 0 1 0 A A 1.09500 0 0 1 0 1 0 1 1 2 B 0.46000 1 0 1 0 1 0 1 1 A B 1.10000 0 0 1 0 1 1 0 0 2 C 0.46500 1 0 1 0 1 1 0 0 A C 1.10500 0 0 1 0 1 1 0 1 2 D 0.47000 1 0 1 0 1 1 0 1 A D 1.11000

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Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 2 of 3)

VID7VID6VID5VID4VID3VID2VID1VID

HEX V

CC_MAX

001011102E0.47500 1 0 1 0 1 1 1 0 A E 1.11500 001011112F0.48000 1 0 1 0 1 1 1 1 A F 1.12000

00110000300.48500 1 0 1 1 0 0 0 0 B 0 1.12500

00110001310.49000 1 0 1 1 0 0 0 1 B 1 1.13000

00110010320.49500 1 0 1 1 0 0 1 0 B 2 1.13500

00110011330.50000 1 0 1 1 0 0 1 1 B 3 1.14000

00110100340.50500 1 0 1 1 0 1 0 0 B 4 1.14500

00110101350.51000 1 0 1 1 0 1 0 1 B 5 1.15000

00110110360.51500 1 0 1 1 0 1 1 0 B 6 1.15500

00110111370.52000 1 0 1 1 0 1 1 1 B 7 1.16000

00111000380.52500 1 0 1 1 1 0 0 0 B 8 1.16500

00111001390.53000 1 0 1 1 1 0 0 1 B 9 1.17000 001110103A0.53500 1 0 1 1 1 0 1 0 B A 1.17500 001110113B0.54000 1 0 1 1 1 0 1 1 B B 1.18000 001111003C0.54500 1 0 1 1 1 1 0 0 B C 1.18500 001111013D0.55000 1 0 1 1 1 1 0 1 B D 1.19000 001111103E0.55500 1 0 1 1 1 1 1 0 B E 1.19500 001111113F0.56000 1 0 1 1 1 1 1 1 B F 1.20000

01000000400.56500 1 1 0 0 0 0 0 0 C 0 1.20500

01000001410.57000 1 1 0 0 0 0 0 1 C 1 1.21000

01000010420.57500 1 1 0 0 0 0 1 0 C 2 1.21500

01000011430.58000 1 1 0 0 0 0 1 1 C 3 1.22000

01000100440.58500 1 1 0 0 0 1 0 0 C 4 1.22500

01000101450.59000 1 1 0 0 0 1 0 1 C 5 1.23000

01000110460.59500 1 1 0 0 0 1 1 0 C 6 1.23500

01000111470.60000 1 1 0 0 0 1 1 1 C 7 1.24000

01001000480.60500 1 1 0 0 1 0 0 0 C 8 1.24500

01001001490.61000 1 1 0 0 1 0 0 1 C 9 1.25000 010010104A0.61500 1 1 0 0 1 0 1 0 C A 1.25500 010010114B0.62000 1 1 0 0 1 0 1 1 C B 1.26000 010011004C0.62500 1 1 0 0 1 1 0 0 C C 1.26500 010011014D0.63000 1 1 0 0 1 1 0 1 C D 1.27000 010011104E0.63500 1 1 0 0 1 1 1 0 C E 1.27500 010011114F0.64000 1 1 0 0 1 1 1 1 C F 1.28000

01010000500.64500 1 1 0 1 0 0 0 0 D 0 1.2 8500

01010001510.65000 1 1 0 1 0 0 0 1 D 1 1.2 9000

01010010520.65500 1 1 0 1 0 0 1 0 D 2 1.2 9500

01010011530.66000 1 1 0 1 0 0 1 1 D 3 1.3 0000

01010100540.66500 1 1 0 1 0 1 0 0 D 4 1.3 0500

01010101550.67000 1 1 0 1 0 1 0 1 D 5 1.3 1000

01010110560.67500 1 1 0 1 0 1 1 0 D 6 1.3 1500

01010111570.68000 1 1 0 1 0 1 1 1 D 7 1.3 2000

01011000580.68500 1 1 0 1 1 0 0 0 D 8 1.3 2500

01011001590.69000 1 1 0 1 1 0 0 1 D 9 1.3 3000 010110105A0.69500 1 1 0 1 1 0 1 0 D A 1.33500 010110115B0.70000 1 1 0 1 1 0 1 1 D B 1.34000 010111005C0.70500 1 1 0 1 1 1 0 0 D C 1.34500

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Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 3 of 3)

VID7VID6VID5VID4VID3VID2VID1VID

HEX V

CC_MAX

0 1 0 1 1 1 0 1 5 D 0.71000 1 1 0 1 1 1 0 1 D D 1.35000 0 1 0 1 1 1 1 0 5 E 0.71500 1 1 0 1 1 1 1 0 D E 1.35500 0 1 0 1 1 1 1 1 5 F 0.72000 1 1 0 1 1 1 1 1 D F 1.36000 0 1 1 0 0 0 0 0 6 0 0.72500 1 1 1 0 0 0 0 0 E 0 1.36500 0 1 1 0 0 0 0 1 6 1 0.73000 1 1 1 0 0 0 0 1 E 1 1.37000 0 1 1 0 0 0 1 0 6 2 0.73500 1 1 1 0 0 0 1 0 E 2 1.37500 0 1 1 0 0 0 1 1 6 3 0.74000 1 1 1 0 0 0 1 1 E 3 1.38000 0 1 1 0 0 1 0 0 6 4 0.74500 1 1 1 0 0 1 0 0 E 4 1.38500 0 1 1 0 0 1 0 1 6 5 0.75000 1 1 1 0 0 1 0 1 E 5 1.39000 0 1 1 0 0 1 1 0 6 6 0.75500 1 1 1 0 0 1 1 0 E 6 1.39500 0 1 1 0 0 1 1 1 6 7 0.76000 1 1 1 0 0 1 1 1 E 7 1.40000 0 1 1 0 1 0 0 0 6 8 0.76500 1 1 1 0 1 0 0 0 E 8 1.40500 0 1 1 0 1 0 0 1 6 9 0.77000 1 1 1 0 1 0 0 1 E 9 1.41000 0 1 1 0 1 0 1 0 6 A 0.77500 1 1 1 0 1 0 1 0 E A 1.41500 0 1 1 0 1 0 1 1 6 B 0.78000 1 1 1 0 1 0 1 1 E B 1.42000 0 1 1 0 1 1 0 0 6 C 0.78500 1 1 1 0 1 1 0 0 E C 1.42500 0 1 1 0 1 1 0 1 6 D 0.79000 1 1 1 0 1 1 0 1 E D 1.43000 0 1 1 0 1 1 1 0 6 E 0.79500 1 1 1 0 1 1 1 0 E E 1.43500 0 1 1 0 1 1 1 1 6 F 0.80000 1 1 1 0 1 1 1 1 E F 1.44000 0 1 1 1 0 0 0 0 7 0 0.80500 1 1 1 1 0 0 0 0 F 0 1.44500 0 1 1 1 0 0 0 1 7 1 0.81000 1 1 1 1 0 0 0 1 F 1 1.45000 0 1 1 1 0 0 1 0 7 2 0.81500 1 1 1 1 0 0 1 0 F 2 1.45500 0 1 1 1 0 0 1 1 7 3 0.82000 1 1 1 1 0 0 1 1 F 3 1.46000 0 1 1 1 0 1 0 0 7 4 0.82500 1 1 1 1 0 1 0 0 F 4 1.46500 0 1 1 1 0 1 0 1 7 5 0.83000 1 1 1 1 0 1 0 1 F 5 1.47000 0 1 1 1 0 1 1 0 7 6 0.83500 1 1 1 1 0 1 1 0 F 6 1.47500 0 1 1 1 0 1 1 1 7 7 0.84000 1 1 1 1 0 1 1 1 F 7 1.48000 0 1 1 1 1 0 0 0 7 8 0.84500 1 1 1 1 1 0 0 0 F 8 1.48500 0 1 1 1 1 0 0 1 7 9 0.85000 1 1 1 1 1 0 0 1 F 9 1.49000 0 1 1 1 1 0 1 0 7 A 0.85500 1 1 1 1 1 0 1 0 F A 1.49500 0 1 1 1 1 0 1 1 7 B 0.86000 1 1 1 1 1 0 1 1 F B 1.50000 0 1 1 1 1 1 0 0 7 C 0.86500 1 1 1 1 1 1 0 0 F C 1.50500 0 1 1 1 1 1 0 1 7 D 0.87000 1 1 1 1 1 1 0 1 F D 1.51000 0 1 1 1 1 1 1 0 7 E 0.87500 1 1 1 1 1 1 1 0 F E 1.51500 0 1 1 1 1 1 1 1 7 F 0.88000 1 1 1 1 1 1 1 1 F F 1.52000

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7.5 System Agent (SA) VCC VID

Electrical Specifications

The V

is configured by the processor output land VCCSA_VID. VCCSA_VID output

CCSA

default logic state is low for 2nd generation and 3rd generation Desktop Core processors, and configures V

to 0.925 V.

CCSA

7.6 Reserved or Unused Signals

The following are the general types of reserved (RSVD) signals and connection guidelines:

• RSVD – these signals should not be connected.

• RSVD_TP – these signals must be routed to a test point. Failure to route these signal to test points will restrict Intel’s ability to assist in platform debug.

• RSVD_NCTF – these signals are non-critical to function and may be left unconnected.

Arbitrary connection of these signals to VCC, V to any other signal (including each other) may result in component malfunction or incompatibility with future processors. See Chapter 8 for a land listing of the processor and the location of all reserved signals.

For reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level. Unused active high inputs should be connected through a resistor to ground (V

). Unused outputs maybe left unconnected; however, this may

interfere with some Test Access Port (TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bi-directional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. For details, see Table 7-8.

CCIO

, V

DDQ

, V

CCPLL

, V

CCSA, VAXG, VSS

, or

7.7 Signal Groups

Signals are grouped by buffer type and similar characteristics as listed in Table 7-2. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals and selected DDR3 and Control Sideband signals have On-Die Termination (ODT) resistors. There are some signals that do not have ODT and need to be terminated on the board.

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Table 7-2. Signal Groups (Sheet 1 of 2)

Signal Group Type Signals

System Reference Clock

Differential CMOS Input BCLK[0], BCLK#[0]

DDR3 Reference Clocks

Differential DDR3 Output

DDR3 Command Signals

Single Ended DDR3 Output

DDR3 Data Signals

Single ended DDR3 Bi-directional SA_DQ[63:0], SB_DQ[63:0]

Differential DDR3 Bi-directional

TAP (ITP/XDP) Single Ended CMOS Input TCK, TDI, TMS, TRST# Single Ended CMOS Output TDO Single Ended Asynchronous CMOS Output TAPPWRGOOD

Control Sideband

Single Ended CMOS Input CFG[17:0] Single Ended Single Ended Asynchronous CMOS Output THERMTRIP#, CATERR# Single Ended Asynchronous CMOS Input Single Ended Asynchronous Bi-directional PECI

Single Ended

Power/Ground/Other

Asynchronous CMOS/Open Drain Bi-directional

CMOS Input Open Drain Output Bi-directional

Power VCC, VCC_NCTF, VCCIO, VCCPLL, VDDQ, VCCAXG Ground VSS No Connect and test point RSVD, RSVD_NCTF, RSVD_TP, FC_x

Sense Points

Other SKTOCC#, DBR#

SA_CK[3:0], SA_CK#[3:0] SB_CK[3:0], SB_CK#[3:0]

SA_RAS#, SB_RAS#, SA_CAS#, SB_CAS# SA_WE#, SB_WE# SA_MA[15:0], SB_MA[15:0] SA_BS[2:0], SB_BS[2:0] SM_DRAMRST# SA_CS#[3:0], SB_CS#[3:0] SA_ODT[3:0], SB_ODT[3:0] SA_CKE[3:0], SB_CKE[3:0]

SA_DQS[8:0], SA_DQS#[8:0] SB_DQS[8:0], SB_DQS#[8:0]

PROCHOT#

SM_DRAMPWROK, UNCOREPWRGOOD PM_SYNC, RESET#

VIDALERT# VIDSCLK VIDSOUT

VCC_SENSE, VSS_SENSE, VCCIO_SENSE, VSS_SENSE_VCCIO, VAXG_SENSE, VSSAXG_SENSE

Datasheet, Volume 1 81

Electrical Specifications

Table 7-2. Signal Groups (Sheet 2 of 2)

Signal Group Type Signals

PCI Express*

Differential PCI Express Input

Differential PCI Express Output

Single Ended Analog Input PEG_ICOMP0, PEG_COMPI, PEG_RCOMP0

DMI

Differential DMI Input DMI_RX[3:0], DMI_RX#[3:0] Differential DMI Output DMI_TX[3:0], DMI_TX#[3:0]

FDI

Intel

Single Ended FDI Input FDI_FSYNC[1:0], FDI_LSYNC[1:0], FDI_INT Differential FDI Output FDI_TX[7:0], FDI_TX#[7:0] Single Ended Analog Input FDI_COMPIO, FDI_ICOMPO

Notes:

1. Refer to Chapter 8 for signal description details.

2. SA and SB refer to DDR3 Channel A and DDR3 Channel B.

3. The maximum rise/fall time of UNCOREPWRGOOD is 20 ns.

4. PE_TX[3:0]/PE_TX#[3:0] and PE_RX[3:0]/PE_RX#[3:0] signals are only used for platforms that support 20 PCIe* lanes. These signals are reserved on Desktop 3rd Generation Intel Core™ i7/i5 processors.

PEG_RX[15:0], PEG_RX#[15:0], PE_RX[3:0]

PEG_TX[15:0], PEG_TX#[15:0], PE_TX[3:0]

, PE_RX#[3:0]

, PE_TX#[3:0]

Note: All Control Sideband Asynchronous signals are required to be asserted/de-asserted for

at least 10 BCLKs with maximum T recognize the proper signal state. See

rise/Tfall

of 6 ns in order for the processor to

Section 7.10 for the DC specifications.

7.8 Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage. Two copies of each signal may be required with each driving a different voltage level.

The processor supports Boundary Scan (JTAG) IEEE 1149.1-2001 and IEEE 1149.62003 standards. A small portion of the I/O lands may support only one of those standards.

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7.9 Storage Conditions Specifications

Environmental storage condition limits define the temperature and relative humidity to which the device is exposed to while being stored in a moisture barrier bag. The specified storage conditions are for component level prior to board attach.

Table 7-3 specifies absolute maximum and minimum storage temperature limits that

represent the maximum or minimum device condition beyond which damage, latent or otherwise, may occur. The table also specifies sustained storage temperature, relative humidity, and time-duration limits. These limits specify the maximum or minimum device storage conditions for a sustained period of time. Failure to adhere to the following specifications can affect long term reliability of the processors conditions outside sustained limits, but within absolute maximum and minimum ratings, quality and reliability may be affected.

Table 7-3. Storage Condition Ratings

Symbol Parameter Min Max Notes

absolute storage

sustained storage

short term storage

sustained storage

Time

sustained storage

Time

short term storage

Notes:

1. Refers to a component device that is not assembled in a board or socket and is not electrically connected to a voltage reference or I/O signal.

2. Specified temperatures are not to exceed values based on data collected. Exceptio ns for surface mount reflow are specified by the applicable JEDEC standard. Non-adherence may affect processor reliability.

3. T

absolute storage

moisture barrier bags, or desiccant.

4. Component product device storage temperature qualification methods may follow JESD22- A119 (low temp) and JESD22-A103 (high temp) standards when applicable for volatile memory.

5. Intel branded products are specified and certified to meet the following temperature and humidity limits that are given as an example only (Non-Operating Temperature Limit: -40 °C to 70 °C and Humidity: 50% to 90%, non-condensing with a maximum wet bulb of 28 °C.) Post board at tach stor age temper ature limits are not specified for non-Intel branded boards.

6. The JEDEC J-JSTD-020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag.

7. Nominal temperature and humidity conditions and durations are given and tested within the constraints imposed by T

The non-operating device storage temperature. Damage (latent or otherwise) may occur when exceeded for any length of time.

The ambient storage temperature (in shipping media) for a sustained period of time

The ambient storage temperature (in shipping media) for a short period of time.

The maximum device storage relative humidity for a sustained period of time.

A prolonged or extended period of time; typically associated with customer shelf life.

A short-period of time; 0 hours 72 hours

applies to the unassembled component only and does not apply to the shipping media,

sustained storage

and customer shelf life in applicable Intel boxes and bags.

-25 °C 125 °C 1, 2, 3, 4

-5 °C 40 °C 5, 6

-20 °C 85 °C

60% at 24 °C 6, 7

0 Months 30 Months 7

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Electrical Specifications

7.10 DC Specifications

The processor DC specifications in this section are defined at the processor pads, unless noted otherwise. See Chapter 8 for the processor land listings and

Chapter 6 for signal definitions. Voltage and current specifications are detailed in Table 7-4, Table 7-5, and Table 7-6.

The DC specifications for the DDR3 signals are listed in Table 7-7 Control Sideband and Test Access Port (TAP) are listed in Table 7-8.

Table 7-4 through Table 7-6 list the DC specifications for the processor and are valid

only while meeting the thermal specifications (as specified in the Thermal / Mechanical Specifications and Guidelines), clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter.

7.10.1 Voltage and Current Specifications

Note: Noise measurements on SENSE lands for all voltage supplies should be made with a 

20-MHz bandwidth oscilloscope.

Table 7-4. Processor Core Active and Idle Mode DC Voltage and Current Specifications

(Sheet 1 of 2)

Symbol Parameter Min Typ Max Unit Note

VID VID Range 0.2500 — 1.5200 V 1

CC,BOOT

Ripple

VCC Loadline Slope 2011D, 2011C, 2011B (processors with

VCC

77 W, 65 W, 55 W, 45 W TDP) V

Tolerance Band

2011D, 2011C, 2011B (processors with 77 W, 65 W, 55 W, 45 W TDP)

TOB

VCC

TOB

PS0 PS1 PS2

Ripple: 2011D, 2011C, 2011B (processors with

77 W, 65 W, 55 W, 45 W TDP)

PS0 PS1 PS2

VCC Loadline Slope 2011A (processors with 35 W TDP)

Tolerance Band

2011A (processors with 35 W TDP)

PS0 PS1 PS2

Ripple: 2011A (processors with 35 W TDP)

PS0 PS1

PS2 Default V 2011D I 2011C I

voltage for initial power up — 0 — V

(processors with 77 W, TDP) — — 112 A 3

(processors with 55 W TDP) — — 75 A 3

1.7 m 2, 4, 5

±16 ±13

±11.5

±7

±10

-10/+25

2.9 m

±19 ±19

±11.5

±10 ±10

-10/+25

2, 4, 5,

6, 7

2, 4, 5,

6, 7

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Table 7-4. Processor Core Active and Idle Mode DC Voltage and Current Specifications

(Sheet 2 of 2)

Symbol Parameter Min Typ Max Unit Note

2011B I 2011A I 2011D Sustained I

77 W, TDP) 2011C Sustained I

55 W TDP) 2011B Sustained I

45 W TDP) 2011A Sustained I

35 W TDP)

I I

CC_TDC

Notes:

1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maxi mum VID v alu es are cal ibr ated duri ng man ufactu ring such that two processors at the same frequency may have different settings within the VID range. This differs from the VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).

2. The voltage specification requirements are measu red across VCC_SENSE and VSS_SENSE lan ds at the socket with a 20-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-M minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

3. ICC_MAX specification is based on the V

4. The V

5. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage

6. PSx refers to the voltage regulator power state as set by the SVID protocol.

7. 2011A (processors with 35 W TDP) loadline slope, TOB, and ripple specifications allow for a cost reduced

regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and VSS_SENSE lands.

voltage regulator for boards supporting only the 2011A (processors with 35 W TDP). 2011A (processors with 35 W TDP) processors may also use the loadline slope, TOB, and ripple specifications for 2011D, 2011C, and 2011B.

(processors with 45 W TDP) — — 60 A 3

(processors with 35 W TDP) — — 35 A 3

(processors with

loadline at worst case (highest) tolerance and ripple.

specifications represent static and transient limits.

——85A

——55A

——40A

——25A

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Electrical Specifications

Table 7-5. Processor System Agent I/O Buffer Supply DC Voltage and Current

Specifications

Symbol Parameter Min Typ Max Unit Note

CCSA

DDQ

TOL

DDQ

CCPLL

CCIO

SA_TDC

DDQ

DDQ_TDC

DDQ_STANDBY

CC_VCCPLL

CC_VCCPLL_TDC

CC_VCCIO

CC_VCCIO_TDC

Voltage for the system agent 0.879 0.925 0.971 V 1 Processor I/O supply voltage for

DDR3

—1.5 —V

DC= ±3%

Tolerance

DDQ

AC= ±2%

AC+DC= ±5%

PLL supply voltage (DC + AC specification)

Processor I/O supply voltage for other than DDR3

1.71 1.8 1.89 V

-2/-3% 1.05 +2/+3% V 2

Current for the system agent — — 8.8 A Sustained current for the system

agent Processor I/O supply current for

DDR3 Processor I/O supply sustained

current for DDR3 Processor I/O supply standby

current for DDR3

——8.2A

— — 4.75 A

—— 1A

PLL supply current — — 1.5 A PLL sustained supply current — — 0.93 A Processor I/O supply current — — 8.5 A Processor I/O supply sustained

current

——8.5A

Notes:

1. VCCSA must be provided using a separate v oltage source and not be conn ected to V measured at VCCSA_SENSE.

2. ±5% total. Minimum of ±2% DC and 3% AC at the sense point. di/dt = 50 A/us with 150 ns step.

. This specification is

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Table 7-6. Processor Graphics VID based (V

Specifications

Symbol Parameter Min Typ Max Unit Note

GFX_VID

AXG

Range

AXG

TOB

AXG

Ripple

AXG

AXG_TDC

Notes:

1. V

2. The V

3. The loadlines specify voltage limits at the die measured at the VAXG_SENSE and VSSAXG_SENSE lands.

4. PSx refers to the voltage regulator power state as set by the SVID protocol.

5. Each processor is programmed with a maximum valid voltage identification value (VID) that is set at

is VID based rail.

AXG

AXG_MIN

Voltage regulation feedback for voltage regulator circuits must also be taken from processor VAXG_SENSE and VSSAXG_SENSE lands.

manufacturing and cannot be altered. Individual maxi mum VID v alu es are cal ibr ated duri ng man ufactu ring such that two processors at the same frequency may have different settings within the VID range. This differs from the VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).

GFX_VID Range for V

Loadline Slope 4.1 m 2, 3

AXG

Tolerance Band

AXG

PS0, PS1 PS2

Ripple:

PS0 PS1 PS2

Current for Processor Graphics core

Sustained current for Processor Graphics core

and V

loadlines represent static and transient limits.

AXG_MAX

) Supply DC Voltage and Current

AXG

0.2500 — 1.5200 V 1

11.5

±10 ±10

-10/+15

——35 A

——25 A

mV 2, 3, 4

Table 7-7. DDR3 Signal Group DC Specifications (Sheet 1 of 2)

Symbol Parameter Min Typ Max Units Notes

ON_UP(DQ)

ON_DN(DQ)

ODT(DQ)

ODT(DC)

Input Low Voltage

Input High Voltage SM_VREF

Input Low Voltage (SM_DRAMPWROK)

Input High Voltage (SM_DRAMPWROK)

Output Low Voltage

Output High Voltage

DDR3 Data Buffer pullup Resistance

DDR3 Data Buffer pulldown Resistance

DDR3 On-die termination equivalent resistance for data signals

——

+ 0.1

——

*0.55

DDQ

+ 0.1

—

20 28.6 40  5

40 50 60 

DDR3 On-die termination DC working point (driver set to receive mode)

0.4*V

DDQ

/(RON+R

DDQ

——V3, 9

——V8

/ 2)* (R

TERM

- ((V

DDQ

/(RON+R

TERM

0.5*V

DDQ

))

/ 2)*

))

1,7

SM_VREF

– 0.1

*0.55

DDQ

– 0.1

V2, 4, 9

—6

—V4, 6

0.6*V

DDQ

Datasheet, Volume 1 87

Table 7-7. DDR3 Signal Group DC Specifications (Sheet 2 of 2)

Symbol Parameter Min Typ Max Units Notes

ON_UP(CK)

ON_DN(CK)

ON_UP(CMD)

ON_DN(CMD)

ON_UP(CTL)

ON_DN(CTL)

DDR3 Clock Buffer pullup Resistance

DDR3 Clock Buffer pulldown Resistance

DDR3 Command Buffer pull-up Resistance

DDR3 Command Buffer pull-down Resistance

DDR3 Control Buffer pull-up Resistance

DDR3 Control Buffer pull-down Resistance

Input Leakage Current (DQ, CK)

0.2*V

DDQ

0.8*V

DDQ

Input Leakage Current (CMD, CTL)

0.2*V

DDQ

0.8*V

DDQ

20 26 40  5, 10

15 20 25  5, 10

——

Electrical Specifications

± 0.75 ± 0.55

± 0.9 ± 1.4

± 0.85 ± 0.65

± 1.10 ± 1.65

1,7

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low

2. V

value.

is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

3. V

value.

and VOH may experience excursions above V

4. V

signal quality specifications.

5. This is the pull-up/pull-down driver resistance.

6. R

7. The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.

8. SM_DRAMPWROK must have a maximum of 15 ns rise or fall time over V

9. SM_VREF is defined as V

10. R

is the termination on the DIMM and in not controlled by the processor.

TERM

must be monotonic.

tolerance is preliminary and might be subject to change.

DDQ

. However, input signal drivers must comply with the

DDQ

* 0.55 ±200 mV and the edge

DDQ

88 Datasheet, Volume 1

Electrical Specifications

Table 7-8. Control Sideband and TAP Signal Group DC Specifications

Symbol Parameter Min Max Units Notes

V V V

V R

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. The V

3. For V

4. V

Input Low Voltage — V

Input High Voltage V

Output Low Voltage — V

Output High Voltage V

Buffer on Resistance 23 73 

Input Leakage Current — ±200 A3

referred to in these specifications refers to instantaneous V

CCIO

between “0” V and V

and VOH may experience excursions above V

signal quality specifications.

. Measured when the driver is tri-stated.

CCIO

* 0.7 — V 2, 4

CCIO

* 0.9 — V 2, 4

CCIO

. However, input signal drivers must comply with the

CCIO

Table 7-9. PCI Express* DC Specifications

Symbol Parameter Min Typ Max Units Notes

TX-DIFF-DC

RX-DC

RX-DIFF-DC

PEG_ICOMPO Comp Resistance 24.75 25 25.25  5, 6

PEG_ICOMPI Comp Resistance 24.75 25 25.25  5, 6

PEG_RCOMPO Comp Resistance 24.75 25 25.25  5, 6

DC Differential Tx Impedance (Gen 1 Only)

DC Differential Tx Impedance (Gen 2 and Gen 3)

80 — 120  2

— — 120  2

DC Common Mode Rx Impedance 40 — 60  3, 4 DC Differential Rx Impedance (Gen 1

Only)

80 — 120 

* 0.3 V 2

* 0.1 V 2

Notes:

1. Refer to the PCI Express Base Specification for more details.

2. Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.

3. DC impedance limits are needed to ensure Receiver detect.

4. The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately and the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50  ±20%) must be within the specified range by the time Detect is entered.

5. COMP resistance must be provided on the system board with 1% resistors.

6. PEG_ICOMPO, PEG_ICOMPI, PEG_RCOMPO are the same resistor. Intel allows using 24.9  1% resistors.

Datasheet, Volume 1 89

Electrical Specifications

Q1 nX

Q2 1X

PECI

<10 pF / Node

Q3 nX

PECI ClientHost / Originator

Additional PECI

Clients

PECI

7.11 Platform Environmental Control Interface (PECI) DC Specifications

PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature. Te mperature sensors located throughout the die are implemented as analog-to-digital converters calibrated at the factory. PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control. More detailed information may be found in the Platform Environment Control Interface (PECI) Specification.

7.11.1 PECI Bus Architecture

The PECI architecture based on wired OR bus which the clients (as processor PECI) can pull up high (with strong drive).

The idle state on the bus is near zero.

Figure 7-1 demonstrates PECI design and connectivity, while the host/originator can be

3rd party PECI host, and one of the PECI clients is the processor PECI device.

Figure 7-1. Example for PECI Host-Clients Connection

90 Datasheet, Volume 1

Electrical Specifications

Minimum V

Maximum V

Minimum V

Maximum V

PECI High Range

PECI Low Range

Valid Input Signal Range

Minimum Hysteresis

TTD

PECI Ground

7.11.2 DC Characteristics

The PECI interface operates at a nominal voltage set by V specifications shown in Table 7-10 are used with devices normally operating from a V

interface supply. V

CCIO

PECI devices will operate at the V system. For specific nominal V

Table 7-10. PECI DC Electrical Limits

Symbol Definition and Conditions Min Max Units Notes

Rup

hysteresis

V V

bus

Cpad

Ileak000 leakage current at 0V — 0.6 mA Ileak025 leakage current at 0.25*V Ileak050 leakage current at 0.50*V Ileak075 leakage current at 0.75*V Ileak100 leakage current at V

Notes:

1. V

2. The leakage specification applies to powered devices on the PECI bus.

3. The PECI buffer internal pull up resistance measured at 0.75*V

Output resistance 15 45  3 Input Voltage Range -0.15 V

Hysteresis 0.1 * V Negative-Edge Threshold Voltage 0.275 * V

Positive-Edge Threshold Voltage 0.550 * V

Bus Capacitance per Node N/A 10 pF Pad Capacitance 0.7 1.8 pF

supplies the PECI interface. PECI behavior does not affect V

CCIO

. The DC electrical

CCIO

nominal levels will vary between processor families. All

level determined by the processor installed in the

CCIO

levels, refer to Table 7-5.

CCIO

V V

CCIO

—0.4mA —0.2mA —0.13mA —0.10mA

N/A V

0.500 * V

0.725 * V

CCIO

CCIO.

CCIO

min/max specifications.

7.11.3 Input Device Hysteresis

The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 7-2 as a guide for input buffer design.

Figure 7-2. Input Device Hysteresis

Datasheet, Volume 1 91

§ §

Electrical Specifications

92 Datasheet, Volume 1

Processor Land and Signal Information

8 Processor Land and Signal

Information

8.1 Processor Land Assignments

The processor land map is shown in Figure 8-1. Table 8-1 provides a listing of all processor lands ordered alphabetically by land name.

Note: SA_ECC_CB[7:0] and SB_ECC_CB[7:0] Lands are RSVD on Desktop 3rd Generation

Note: PE_TX[3:0]/PE_TX#[3:0] and PE_RX[3:0]/PE_RX#[3:0] Lands are RSVD on Desktop

Intel

Core™ i7/i5 processors.

3rd Generation Intel Desktop Intel Celeron processors.

Core™ i7/i5 processors, Desktop Intel Pentium processors, and

Datasheet, Volume 1 93

Figure 8-1. LGA Socket Land Map

40393837363534333231302928272625242322212019181716151413121110987654321 AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC

AB AA

V U T R P N

L K J

G F E D C B A

40393837363534333231302928272625242322212019181716151413121110987654321

Processor Land and Signal Information

94 Datasheet, Volume 1

Processor Land and Signal Information

Table 8-1. Processor Land List by

Land Name

Land Name Land # Buffer Type Dir.

BCLK_ITP C40 Diff Clk I BCLK_ITP# D40 Diff Clk I BCLK[0] W2 Diff Clk I BCLK#[0] W1 Diff Clk I BPM#[0] H40 GTL I/O BPM#[1] H38 GTL I/O BPM#[2] G38 GTL I/O BPM#[3] G40 GTL I/O BPM#[4] G39 GTL I/O BPM#[5] F38 GTL I/O BPM#[6] E40 GTL I/O BPM#[7] F40 GTL I/O CATERR# E37 GTL O CFG[0] H36 CMOS I CFG[1] J36 CMOS I CFG[2] J37 CMOS I CFG[3] K36 CMOS I CFG[4] L36 CMOS I CFG[5] N35 CMOS I CFG[6] L37 CMOS I CFG[7] M36 CMOS I CFG[8] J38 CMOS I CFG[9] L35 CMOS I CFG[10] M38 CMOS I CFG[11] N36 CMOS I CFG[12] N38 CMOS I CFG[13] N39 CMOS I CFG[14] N37 CMOS I CFG[15] N40 CMOS I CFG[16] G37 CMOS I CFG[17] G36 CMOS I DBR# E39 Async CMOS O DMI_RX[0] W5 DMI I DMI_RX[1] V3 DMI I DMI_RX[2] Y3 DMI I DMI_RX[3] AA4 DMI I DMI_RX#[0] W4 DMI I DMI_RX#[1] V4 DMI I DMI_RX#[2] Y4 DMI I DMI_RX#[3] AA5 DMI I DMI_TX[0] V7 DMI O DMI_TX[1] W7 DMI O DMI_TX[2] Y6 DMI O DMI_TX[3] AA7 DMI O DMI_TX#[0] V6 DMI O DMI_TX#[1] W8 DMI O DMI_TX#[2] Y7 DMI O

Table 8-1. Processor Land List by

Land Name

Land Name Land # Buffer Type Dir.

DMI_TX#[3] AA8 DMI O SB_DIMM_VREFDQ AH1 Analog O

SA_DIMM_VREFDQ AH4 Analog O FDI_COMPIO AE2 Analog I FDI_FSYNC[0] AC5 CMOS I FDI_FSYNC[1] AE5 CMOS I FDI_ICOMPO AE1 Analog I FDI_INT AG3 CMOS I FDI_LSYNC[0] AC4 CMOS I FDI_LSYNC[1] AE4 CMOS I FDI_TX[0] AC8 FDI O FDI_TX[1] AC2 FDI O FDI_TX[2] AD2 FDI O FDI_TX[3] AD4 FDI O FDI_TX[4] AD7 FDI O FDI_TX[5] AE7 FDI O FDI_TX[6] AF3 FDI O FDI_TX[7] AG2 FDI O FDI_TX#[0] AC7 FDI O FDI_TX#[1] AC3 FDI O FDI_TX#[2] AD1 FDI O FDI_TX#[3] AD3 FDI O FDI_TX#[4] AD6 FDI O FDI_TX#[5] AE8 FDI O FDI_TX#[6] AF2 FDI O FDI_TX#[7] AG1 FDI O NCTF A38 NCTF AU40 NCTF AW38 NCTF C2 NCTF D1 PE_RX[0] P3 PCI Express I PE_RX[1] R2 PCI Express I PE_RX[2] T4 PCI Expr ess I PE_RX[3] U2 PCI Express I PE_RX#[0] P4 PCI Express I PE_RX#[1] R1 PCI Express I PE_RX#[2] T3 PCI Express I PE_RX#[3] U1 PCI Express I PE_TX[0] P8 PCI Express O PE_TX[1] T7 PCI Express O PE_TX[2] R6 PCI Express O PE_TX[3] U5 PCI Express O PE_TX#[0] P7 PCI Express O PE_TX#[1] T8 PCI Express O PE_TX#[2] R5 PCI Express O PE_TX#[3] U6 PCI Express O

Datasheet, Volume 1 95

Processor Land and Signal Information

Table 8-1. Processor Land List by

Land Name

Land Name Land # Buffer Type Dir.

PECI J35 Async I/O PEG_COMPI B4 Analog I PEG_ICOMPO B5 Analog I PEG_RCOMPO C4 Analog I PEG_RX[0] B11 PCI Express I PEG_RX[1] D12 PCI Express I PEG_RX[2] C10 PCI Express I PEG_RX[3] E10 PCI Express I PEG_RX[4] B8 PCI Express I PEG_RX[5] C6 PCI Express I PEG_RX[6] A5 PCI Express I PEG_RX[7] E2 PCI Express I PEG_RX[8] F4 PCI Express I PEG_RX[9] G2 PCI Express I PEG_RX[10] H3 PCI Express I PEG_RX[11] J1 PCI Express I PEG_RX[12] K3 PCI Express I PEG_RX[13] L1 PCI Express I PEG_RX[14] M3 PCI Express I PEG_RX[15] N1 PCI Express I PEG_RX#[0] B12 PCI Express I PEG_RX#[1] D11 PCI Express I PEG_RX#[2] C9 PCI Express I PEG_RX#[3] E9 PCI Express I PEG_RX#[4] B7 PCI Express I PEG_RX#[5] C5 PCI Express I PEG_RX#[6] A6 PCI Express I PEG_RX#[7] E1 PCI Express I PEG_RX#[8] F3 PCI Express I PEG_RX#[9] G1 PCI Express I PEG_RX#[10] H4 PCI Express I PEG_RX#[11] J2 PCI Express I PEG_RX#[12] K4 PCI Express I PEG_RX#[13] L2 PCI Express I PEG_RX#[14] M4 PCI Express I PEG_RX#[15] N2 PCI Express I PEG_TX[0] C13 PCI Expr ess O PEG_TX[1] E14 PCI Express O PEG_TX[2] G14 PCI Express O PEG_TX[3] F12 PCI Express O PEG_TX[4] J14 PCI Express O PEG_TX[5] D8 PCI Express O PEG_TX[6] D3 PCI Express O PEG_TX[7] E6 PCI Express O PEG_TX[8] F8 PCI Express O PEG_TX[9] G10 PCI Express O PEG_TX[10] G5 PCI Express O

Table 8-1. Processor Land List by

Land Name

Land Name Land # Buffer Type Dir.

PEG_TX[11] K7 PCI Express O PEG_TX[12] J5 PCI Express O PEG_TX[13] M8 PCI Express O PEG_TX[14] L6 PCI Ex press O PEG_TX[15] N5 PCI Express O PEG_TX#[0] C14 PCI Express O PEG_TX#[1] E13 PCI Express O PEG_TX#[2] G13 PCI Express O PEG_TX#[3] F11 PCI Express O PEG_TX#[4] J13 PCI Express O PEG_TX#[5] D7 PCI Express O PEG_TX#[6] C3 PCI Express O PEG_TX#[7] E5 PCI Express O PEG_TX#[8] F7 PCI Express O PEG_TX#[9] G9 PCI Express O PEG_TX#[10] G6 PCI Express O PEG_TX#[11] K8 PCI Express O PEG_TX#[12] J6 PCI Express O PEG_TX#[13] M7 PCI Express O PEG_TX#[14] L5 PCI Express O PEG_TX#[15] N6 PCI Express O PM_SYNC E38 CMOS I PRDY# K38 Async GTL O PREQ# K4 0 Async GTL I PROC_SEL PROCHOT# H34 Async GTL I/O RESET# F36 CMOS I RSVD AB6 RSVD AB7 RSVD AD37 RSVD AE6 RSVD AF4 RSVD AG4 RSVD AJ11 RSVD AJ29 RSVD AJ30 RSVD AJ31 RSVD AN20 RSVD AP20 RSVD AT11 RSVD AT14 RSVD AU10 RSVD AV34 RSVD AW34 RSVD AY10 RSVD C38 RSVD C39

K32 N/A O

96 Datasheet, Volume 1

Processor Land and Signal Information

Table 8-1. Processor Land List by

Land Name

Land Name Land # Buffer Type Dir.

RSVD D38 RSVD H7 RSVD H8 RSVD J33 RSVD J34 RSVD J9 RSVD K34 RSVD K9 RSVD L31 RSVD L33 RSVD L34 RSVD L9 RSVD M34 RSVD N33 RSVD N34 RSVD P35 RSVD P37 RSVD P39 RSVD R34 RSVD R36 RSVD R38 RSVD R40 RSVD RSVD RSVD RSVD RSVD_NCTF AV1 RSVD_NCTF AW2 RSVD_NCTF AY3 RSVD_NCTF B39 SA_BS[0] AY29 DDR3 O SA_BS[1] AW28 DDR3 O SA_BS[2] AV20 DDR3 O SA_CAS# AV30 DDR3 O SA_CK[0] AY25 DDR3 O SA_CK[1] AU24 DDR3 O SA_CK[2] AW27 DDR3 O SA_CK[3] AV26 DDR3 O SA_CK#[0] AW25 DDR3 O SA_CK#[1] AU25 DDR3 O SA_CK#[2] AY27 DDR3 O SA_CK#[3] AW26 DDR3 O SA_CKE[0] AV19 DDR3 O SA_CKE[1] AT19 DDR3 O SA_CKE[2] AU18 DDR3 O SA_CKE[3] AV18 DDR3 O SA_CS#[0] AU29 DDR3 O

J31 AD34 AD35

K31

Table 8-1. Processor Land List by

Land Name

Land Name Land # Buffer Type Dir.

SA_CS#[1] AV32 DDR3 O SA_CS#[2] AW30 DDR3 O SA_CS#[3] AU33 DDR3 O SA_DQ[0] AJ3 DDR3 I/O SA_DQ[1] AJ4 DDR3 I/O SA_DQ[2] AL3 DDR3 I/O SA_DQ[3] AL4 DDR3 I/O SA_DQ[4] AJ2 DDR3 I/O SA_DQ[5] AJ1 DDR3 I/O SA_DQ[6] AL2 DDR3 I/O SA_DQ[7] AL1 DDR3 I/O SA_DQ[8] AN1 DDR3 I/O SA_DQ[9] AN4 DDR3 I/O SA_DQ[10] AR3 DDR3 I/O SA_DQ[11] AR4 DDR3 I/O SA_DQ[12] AN2 DDR3 I/O SA_DQ[13] AN3 DDR3 I/O SA_DQ[14] AR2 DDR3 I/O SA_DQ[15] AR1 DDR3 I/O SA_DQ[16] AV2 DDR3 I/O SA_DQ[17] AW3 DDR3 I/O SA_DQ[18] AV5 DDR3 I/O SA_DQ[19] AW5 DDR3 I/O SA_DQ[20] AU2 DDR3 I/O SA_DQ[21] AU3 DDR3 I/O SA_DQ[22] AU5 DDR3 I/O SA_DQ[23] AY5 DDR3 I/O SA_DQ[24] AY7 DDR3 I/O SA_DQ[25] AU7 DDR3 I/O SA_DQ[26] AV9 DDR3 I/O SA_DQ[27] AU9 DDR3 I/O SA_DQ[28] AV7 DDR3 I/O SA_DQ[29] AW7 DDR3 I/O SA_DQ[30] AW9 DDR3 I/O SA_DQ[31] AY9 DDR3 I/O SA_DQ[32] AU35 DDR3 I/O SA_DQ[33] AW37 DDR3 I/O SA_DQ[34] AU39 DDR3 I/O SA_DQ[35] AU36 DDR3 I/O SA_DQ[36] AW35 DDR3 I/O SA_DQ[37] AY36 DDR3 I/O SA_DQ[38] AU38 DDR3 I/O SA_DQ[39] AU37 DDR3 I/O SA_DQ[40] AR40 DDR3 I/O SA_DQ[41] AR37 DDR3 I/O SA_DQ[42] AN38 DDR3 I/O SA_DQ[43] AN37 DDR3 I/O

Datasheet, Volume 1 97

Processor Land and Signal Information

Table 8-1. Processor Land List by

Land Name

Land Name Land # Buffer Type Dir.

SA_DQ[44] AR39 DDR3 I/O SA_DQ[45] AR38 DDR3 I/O SA_DQ[46] AN39 DDR3 I/O SA_DQ[47] AN40 DDR3 I/O SA_DQ[48] AL40 DDR3 I/O SA_DQ[49] AL37 DDR3 I/O SA_DQ[50] AJ38 DDR3 I/O SA_DQ[51] AJ37 DDR3 I/O SA_DQ[52] AL39 DDR3 I/O SA_DQ[53] AL38 DDR3 I/O SA_DQ[54] AJ39 DDR3 I/O SA_DQ[55] AJ40 DDR3 I/O SA_DQ[56] AG40 DDR3 I/O SA_DQ[57] AG37 DDR3 I/O SA_DQ[58] AE38 DDR3 I/O SA_DQ[59] AE37 DDR3 I/O SA_DQ[60] AG39 DDR3 I/O SA_DQ[61] AG38 DDR3 I/O SA_DQ[62] AE39 DDR3 I/O SA_DQ[63] AE40 DDR3 I/O SA_DQS[0] AK3 DDR3 I/O SA_DQS[1] AP3 DDR3 I/O SA_DQS[2] AW4 DDR3 I/O SA_DQS[3] AV8 DDR3 I/O SA_DQS[4] AV37 DDR3 I/O SA_DQS[5] AP38 DDR3 I/O SA_DQS[6] AK38 DDR3 I/O SA_DQS[7] AF38 DDR3 I/O SA_DQS[8] AV13 DDR3 I/O SA_DQS#[0] AK2 DDR3 I/O SA_DQS#[1] AP2 DDR3 I/O SA_DQS#[2] AV4 DDR3 I/O SA_DQS#[3] AW8 DDR3 I/O SA_DQS#[4] AV36 DDR3 I/O SA_DQS#[5] AP39 DDR3 I/O SA_DQS#[6] AK39 DDR3 I/O SA_DQS#[7] AF39 DDR3 I/O SA_DQS#[8] AV12 DDR3 I/O SA_ECC_CB[0] AU12 DDR3 I/O SA_ECC_CB[1] AU14 DDR3 I/O SA_ECC_CB[2] AW13 DDR3 I/O SA_ECC_CB[3] AY13 DDR3 I/O SA_ECC_CB[4] AU13 DDR3 I/O SA_ECC_CB[5] AU11 DDR3 I/O SA_ECC_CB[6] AY12 DDR3 I/O SA_ECC_CB[7] AW12 DDR3 I/O SA_MA[0] AV27 DDR3 O

Table 8-1. Processor Land List by

Land Name

Land Name Land # Buffer Type Dir.

SA_MA[1] AY24 DDR3 O SA_MA[2] AW24 DDR3 O SA_MA[3] AW23 DDR3 O SA_MA[4] AV23 DDR3 O SA_MA[5] AT24 DDR3 O SA_MA[6] AT23 DDR3 O SA_MA[7] AU22 DDR3 O SA_MA[8] AV22 DDR3 O SA_MA[9] AT22 DDR3 O SA_MA[10] AV28 DDR3 O SA_MA[11] AU21 DDR3 O SA_MA[12] AT21 DDR3 O SA_MA[13] AW32 DDR3 O SA_MA[14] AU20 DDR3 O SA_MA[15] AT20 DDR3 O SA_ODT[0] AV31 DDR3 O SA_ODT[1] AU32 DDR3 O SA_ODT[2] AU30 DDR3 O SA_ODT[3] AW33 DDR3 O SA_RAS# AU28 DDR3 O SA_WE# AW29 DDR3 O SB_BS[0] AP23 DDR3 O SB_BS[1] AM24 DDR3 O SB_BS[2] AW17 DDR3 O SB_CAS# AK25 DDR3 O SB_CK[0] AL21 DDR3 O SB_CK[1] AL20 DDR3 O SB_CK[2] AL23 DDR3 O SB_CK[3] AP21 DDR3 O SB_CK#[0] AL22 DDR3 O SB_CK#[1] AK20 DDR3 O SB_CK#[2] AM22 DDR3 O SB_CK#[3] AN21 DDR3 O SB_CKE[0] AU16 DDR3 O SB_CKE[1] AY15 DDR3 O SB_CKE[2] AW15 DDR3 O SB_CKE[3] AV15 DDR3 O SB_CS#[0] AN25 DDR3 O SB_CS#[1] AN26 DDR3 O SB_CS#[2] AL25 DDR3 O SB_CS#[3] AT26 DDR3 O SB_DQ[0] AG7 DDR3 I/O SB_DQ[1] AG8 DDR3 I/O SB_DQ[2] AJ9 DDR3 I/O SB_DQ[3] AJ8 DDR3 I/O SB_DQ[4] AG5 DDR3 I/O SB_DQ[5] AG6 DDR3 I/O

98 Datasheet, Volume 1

Processor Land and Signal Information

Table 8-1. Processor Land List by

Land Name

Land Name Land # Buffer Type Dir.

SB_DQ[6] AJ6 DDR3 I/O SB_DQ[7] AJ7 DDR3 I/O SB_DQ[8] AL7 DDR3 I/O SB_DQ[9] AM7 DDR3 I/O SB_DQ[10] AM10 DDR3 I/O SB_DQ[11] AL10 DDR3 I/O SB_DQ[12] AL6 DDR3 I/O SB_DQ[13] AM6 DDR3 I/O SB_DQ[14] AL9 DDR3 I/O SB_DQ[15] AM9 DDR3 I/O SB_DQ[16] AP7 DDR3 I/O SB_DQ[17] AR7 DDR3 I/O SB_DQ[18] AP10 DDR3 I/O SB_DQ[19] AR10 DDR3 I/O SB_DQ[20] AP6 DDR3 I/O SB_DQ[21] AR6 DDR3 I/O SB_DQ[22] AP9 DDR3 I/O SB_DQ[23] AR9 DDR3 I/O SB_DQ[24] AM12 DDR3 I/O SB_DQ[25] AM13 DDR3 I/O SB_DQ[26] AR13 DDR3 I/O SB_DQ[27] AP13 DDR3 I/O SB_DQ[28] AL12 DDR3 I/O SB_DQ[29] AL13 DDR3 I/O SB_DQ[30] AR12 DDR3 I/O SB_DQ[31] AP12 DDR3 I/O SB_DQ[32] AR28 DDR3 I/O SB_DQ[33] AR29 DDR3 I/O SB_DQ[34] AL28 DDR3 I/O SB_DQ[35] AL29 DDR3 I/O SB_DQ[36] AP28 DDR3 I/O SB_DQ[37] AP29 DDR3 I/O SB_DQ[38] AM28 DDR3 I/O SB_DQ[39] AM29 DDR3 I/O SB_DQ[40] AP32 DDR3 I/O SB_DQ[41] AP31 DDR3 I/O SB_DQ[42] AP35 DDR3 I/O SB_DQ[43] AP34 DDR3 I/O SB_DQ[44] AR32 DDR3 I/O SB_DQ[45] AR31 DDR3 I/O SB_DQ[46] AR35 DDR3 I/O SB_DQ[47] AR34 DDR3 I/O SB_DQ[48] AM32 DDR3 I/O SB_DQ[49] AM31 DDR3 I/O SB_DQ[50] AL35 DDR3 I/O SB_DQ[51] AL32 DDR3 I/O SB_DQ[52] AM34 DDR3 I/O

Table 8-1. Processor Land List by

Land Name

Land Name Land # Buffer Type Dir.

SB_DQ[53] AL31 DDR3 I/O SB_DQ[54] AM35 DDR3 I/O SB_DQ[55] AL34 DDR3 I/O SB_DQ[56] AH35 DDR3 I/O SB_DQ[57] AH34 DDR3 I/O SB_DQ[58] AE34 DDR3 I/O SB_DQ[59] AE35 DDR3 I/O SB_DQ[60] AJ35 DDR3 I/O SB_DQ[61] AJ34 DDR3 I/O SB_DQ[62] AF33 DDR3 I/O SB_DQ[63] AF35 DDR3 I/O SB_DQS[0] AH7 DDR3 I/O SB_DQS[1] AM8 DDR3 I/O SB_DQS[2] AR8 DDR3 I/O SB_DQS[3] AN13 DDR3 I/O SB_DQS[4] AN29 DDR3 I/O SB_DQS[5] AP33 DDR3 I/O SB_DQS[6] AL33 DDR3 I/O SB_DQS[7] AG35 DDR3 I/O SB_DQS[8] AN16 DDR3 I/O SB_DQS#[0] AH6 DDR3 I/O SB_DQS#[1] AL8 DDR3 I/O SB_DQS#[2] AP8 DDR3 I/O SB_DQS#[3] AN12 DDR3 I/O SB_DQS#[4] AN28 DDR3 I/O SB_DQS#[5] AR33 DDR3 I/O SB_DQS#[6] AM33 DDR3 I/O SB_DQS#[7] AG34 DDR3 I/O SB_DQS#[8] AN15 DDR3 I/O SB_ECC_CB[0] AL16 DDR3 I/O SB_ECC_CB[1] AM16 DDR3 I/O SB_ECC_CB[2] AP16 DDR3 I/O SB_ECC_CB[3] AR16 DDR3 I/O SB_ECC_CB[4] AL15 DDR3 I/O SB_ECC_CB[5] AM15 DDR3 I/O SB_ECC_CB[6] AR15 DDR3 I/O SB_ECC_CB[7] AP15 DDR3 I/O SB_MA[0] AK24 DDR3 O SB_MA[1] AM20 DDR3 O SB_MA[2] AM19 DDR3 O SB_MA[3] AK18 DDR3 O SB_MA[4] AP19 DDR3 O SB_MA[5] AP18 DDR3 O SB_MA[6] AM18 DDR3 O SB_MA[7] AL18 DDR3 O SB_MA[8] AN18 DDR3 O SB_MA[9] AY17 DDR3 O

Datasheet, Volume 1 99

Processor Land and Signal Information

Table 8-1. Processor Land List by

Land Name

Land Name Land # Buffer Type Dir.

SB_MA[10] AN23 DDR3 O SB_MA[11] AU17 DDR3 O SB_MA[12] AT18 DDR3 O SB_MA[13] AR26 DDR3 O SB_MA[14] AY16 DDR3 O SB_MA[15] AV16 DDR3 O SB_ODT[0] AL26 DDR3 O SB_ODT[1] AP26 DDR3 O SB_ODT[2] AM26 DDR3 O SB_ODT[3] AK26 DDR3 O SB_RAS# AP24 DDR3 O SB_WE# AR25 DDR3 O SKTOCC# AJ33 Analog O SM_DRAMPWROK AJ19 Async CMOS I SM_DRAMRST# AW18 DDR3 O SM_VREF AJ22 Analog I TCK M40 TAP I TDI L40 TAP I TDO L39 TAP O THERMTRIP# G35 Asynch CMOS O TMS L38 TAP I TRST# J39 TAP I UNCOREPWRGOOD J40 Async CMOS I VCC A12 PWR VCC A13 PWR VCC A14 PWR VCC A15 PWR VCC A16 PWR VCC A18 PWR VCC A24 PWR VCC A25 PWR VCC A27 PWR VCC A28 PWR VCC B15 PWR VCC B16 PWR VCC B18 PWR VCC B24 PWR VCC B25 PWR VCC B27 PWR VCC B28 PWR VCC B30 PWR VCC B31 PWR VCC B33 PWR VCC B34 PWR VCC C15 PWR VCC C16 PWR VCC C18 PWR

Table 8-1. Processor Land List by

Land Name

Land Name Land # Buffer Type Dir.

VCC C19 PWR VCC C21 PWR VCC C22 PWR VCC C24 PWR VCC C25 PWR VCC C27 PWR VCC C28 PWR VCC C30 PWR VCC C31 PWR VCC C33 PWR VCC C34 PWR VCC C36 PWR VCC D13 PWR VCC D14 PWR VCC D15 PWR VCC D16 PWR VCC D18 PWR VCC D19 PWR VCC D21 PWR VCC D22 PWR VCC D24 PWR VCC D25 PWR VCC D27 PWR VCC D28 PWR VCC D30 PWR VCC D31 PWR VCC D33 PWR VCC D34 PWR VCC D35 PWR VCC D36 PWR VCC E15 PWR VCC E16 PWR VCC E18 PWR VCC E19 PWR VCC E21 PWR VCC E22 PWR VCC E24 PWR VCC E25 PWR VCC E27 PWR VCC E28 PWR VCC E30 PWR VCC E31 PWR VCC E33 PWR VCC E34 PWR VCC E35 PWR VCC F15 PWR VCC F16 PWR

100 Datasheet, Volume 1

Intel BX80637G2010 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Revision History

1 Introduction

1.1 Processor Feature Details

1.1.1 Supported Technologies

1.2 Interfaces

1.2.1 System Memory Support

1.2.2 PCI Express*

1.2.3 Direct Media Interface (DMI)

1.2.4 Platform Environment Control Interface (PECI)

1.2.5 Processor Graphics

1.2.6 Intel® Flexible Display Interface (Intel® FDI)

1.3 Power Management Support

1.3.1 Processor Core

1.3.2 System

1.3.3 Memory Controller

1.3.4 PCI Express*

1.3.5 Direct Media Interface (DMI)

1.3.6 Processor Graphics Controller (GT)

1.3.7 Thermal Management Support

1.4 Processor SKU Definitions

1.5 Package

1.6 Processor Compatibility

1.7 Terminology

1.8 Related Documents

2 Interfaces

2.1 System Memory Interface

2.1.1 System Memory Technology Supported

2.1.2 System Memory Timing Support

2.1.3 System Memory Organization Modes

2.1.3.1 Single-Channel Mode

2.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode

2.1.4 Rules for Populating Memory Slots

2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

2.1.5.1 Just-in-Time Command Scheduling

2.1.5.2 Command Overlap

2.1.5.3 Out-of-Order Scheduling

2.1.6 Data Scrambling

2.1.7 DDR3 Reference Voltage Generation

2.2 PCI Express* Interface

2.2.1 PCI Express* Architecture

2.2.1.1 Transaction Layer

2.2.1.2 Data Link Layer

2.2.1.3 Physical Layer

2.2.2 PCI Express* Configuration Mechanism

2.2.3 PCI Express* Port

2.2.3.1 PCI Express* Lanes Connection

2.3 Direct Media Interface (DMI)

2.3.1 DMI Error Flow

2.3.2 Processor / PCH Compatibility Assumptions

2.3.3 DMI Link Down

2.4 Processor Graphics Controller (GT)

2.4.1 3D and Video Engines for Graphics Processing

2.4.1.1 3D Engine Execution Units

2.4.1.2 3D Pipeline

2.4.1.3 Video Engine

2.4.1.4 2D Engine

2.4.2 Processor Graphics Display

2.4.2.1 Display Planes

2.4.2.2 Display Pipes

2.4.2.3 Display Ports

2.4.3 Intel® Flexible Display Interface (Intel® FDI)

2.4.4 Multi Graphics Controllers Multi-Monitor Support

2.5 Platform Environment Control Interface (PECI)

2.6 Interface Clocking

2.6.1 Internal Clocking Requirements

3 Technologies

3.1 Intel® Virtualization Technology (Intel® VT)

3.2 Intel® Trusted Execution Technology (Intel® TXT)

3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)

3.4 Intel® Turbo Boost Technology

3.4.1 Intel® Turbo Boost Technology Frequency

3.4.2 Intel® Turbo Boost Technology Graphics Frequency

3.5 Intel® Advanced Vector Extensions (Intel® AVX)

3.6 Security and Cryptography Technologies

3.6.1 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)

3.6.2 PCLMULQDQ Instruction