Intel BX80637G2010 User Manual

Desktop 3rd Generation Intel® Core™ Processor Family, Desktop

Intel and Desktop Intel

Pentium® Processor Family,

Celeron®

Processor Family

Datasheet – Volume 1 of 2

November 2013

Document Number: 326764-008

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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained

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Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor

Intel (VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configur ations and may re quire a BIOS update. S oftware applicatio ns may not be compatible

Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code

Tru sted Ex ecution Technology (Intel® TXT) requires

with all operating systems. Please check with your application vendor.

Active Management Technology requires the computer system to have an Intel(R) AMT-enabled chipset, network hardware

Intel and software, as well as connection with a power source and a corporate network connection. Setup requires configuration by the purchaser and may require scripting with the management console or further integration into existing security frameworks to enable certain functionality. It may also require modifications of implementation of new business processes. With regard to notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see http://www.intel.com/technology/

platform-technology/intel-amt/

Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technologyenabled chipset, BIOS and operating system. Performance will va ry de pe ndi ng on the specific hardware and software y ou use. For more information including details on which processors support HT Technology, see http://www.intel.com/info/hyperthreading.

“Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology.For more information, see http://www.intel.com/

technology/turboboost.”

Enhanced Intel SpeedStep

Technology See the Processor Spec Finder or contact your Intel representative for more information.

Intel processor numbers are not a measure of performance. Processor numb ers differentia te features withi n each processo r family, not across different processor families. See www.intel.com/products/processor_number for details.

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information.

Intel, Pentium, Celeron, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2013, Intel Corporation. All rights reserved.

Datasheet, Volume 1



Contents

1Introduction..............................................................................................................9

1.1 Processor Feature Details ...................................................................................11

1.1.1 Supported Technologies..........................................................................11

1.2 Interfaces ........................................................................................................11

1.2.1 System Memory Support.........................................................................11

1.2.2 PCI Express*.........................................................................................12

1.2.3 Direct Media Interface (DMI)....................................................................14

1.2.4 Platform Environment Control Interface (PECI)...........................................14

1.2.5 Processor Graphics.................................................................................14

1.2.6 Intel

1.3 Power Management Support...............................................................................15

1.3.1 Processor Core.......................................................................................15

1.3.2 System.................................................................................................15

1.3.3 Memory Controller.......................................... ............................ ............15

1.3.4 PCI Express*.........................................................................................16

1.3.5 Direct Media Interface (DMI)....................................................................16

1.3.6 Processor Graphics Controller (GT) ...........................................................16

1.3.7 Thermal Management Support .................................................................16

1.4 Processor SKU Definitions...................................................................................16

1.5 Package...........................................................................................................17

1.6 Processor Compatibility......................................................................................18

1.7 Terminology .....................................................................................................19

1.8 Related Documents ...........................................................................................22

2Interfaces................................................................................................................23

2.1 System Memory Interface ..................................................................................23

2.1.1 System Memory Technology Supported... .. .. .. .. .. .. .. ... ............................. ....23

2.1.2 System Memory Timing Support...................................... .. .. .....................24

2.1.3 System Memory Organization Modes.........................................................25

2.1.4 Rules for Populating Memory Slots............................................................26

2.1.5 Technology Enhancements of Intel

2.1.6 Data Scrambling ....................................................................................27

2.1.7 DDR3 Reference Voltage Generation................... .. ... .. ........................... .. ..27

2.2 PCI Express* Interface.......................................................................................28

2.2.1 PCI Express* Architecture .......................................................................28

2.2.2 PCI Express* Configuration Mechanism .....................................................30

2.2.3 PCI Express* Port...................................................................................31

2.3 Direct Media Interface (DMI)...............................................................................32

2.3.1 DMI Error Flow....................................... ................................................32

2.3.2 Processor / PCH Compatibility Assumptions................................................ 32

2.3.3 DMI Link Down ................... .. ......................... .. .. .......................... .. .. ......32

2.4 Processor Graphics Controller (GT) ......................................................................33

Flexible Display Interface (Intel® FDI)................ .............................15

2.1.3.1 Single-Channel Mode.................................................................25

2.1.3.2 Dual-Channel Mode – Intel

2.1.5.1 Just-in-Time Command Scheduling......................... .. .. ... .. ............27

2.1.5.2 Command Overlap....................................................................27

2.1.5.3 Out-of-Order Scheduling............................................................27

2.2.1.1 Transaction Layer .....................................................................29

2.2.1.2 Data Link Layer ........................................................................29

2.2.1.3 Physical Layer ..........................................................................29

2.2.3.1 PCI Express* Lanes Connection ..................................................31

Flex Memory Technology Mode ........... 25

Fast Memory Access (Intel® FMA)..........27

Datasheet, Volume 1 3

2.4.1 3D and Video Engines for Graphics Processing ............................................33

2.4.1.1 3D Engine Execution Units..........................................................33

2.4.1.2 3D Pipeline................................. ......................... .. .. .................34

2.4.1.3 Video Engine ............................................................................34

2.4.1.4 2D Engine ................................................. ......................... ......35

2.4.2 Processor Graphics Display ......................................................................36

2.4.2.1 Display Planes .......................... .. ......................... .. .. .................36

2.4.2.2 Display Pipes................... .......................... .. .. ......................... ..37

2.4.2.3 Display Ports ........................................ .......................... .. .. ......37

2.4.3 Intel

Flexible Display Interface (Intel® FDI) .............................................37

2.4.4 Multi Graphics Controllers Multi-Monitor Support.........................................37

2.5 Platform Environment Control Interface (PECI)......................................................38

2.6 Interface Clocking....................................... .......................... .. .. .........................38

2.6.1 Internal Clocking Requirements......................................... .......................38

3 Technologies............................................................................................................39

3.1 Intel® Virtualization Technology (Intel® VT)..........................................................39

3.1.1 Intel® Virtualization Technology (Intel® VT) for

3.1.2 Intel® Virtualization Technology (Intel® VT) for

3.1.3 Intel

3.1.4 Intel

3.1.5 Intel

3.2 Intel

IA-32, Intel (Intel

I/O (Intel

Trusted Execution Technology (Intel® TXT) ................................ .. ...............42

Virtualization Technology (Intel® VT) for Directed Virtualization Technology (Intel® VT) for Directed Virtualization Technology (Intel® VT) for Directed

64 and Intel® Architecture 

VT-x) Objectives.................................... .. .. .......................... .. .. ....39

64 and Intel® Architecture 

VT-x) Features ..................... .. .......................... .. .. .......................40

VT-d) Objectives ....................................................................40

VT-d) Features.......................................................................41

VT-d) Features Not Supported..................................................41

3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)....................................42

3.4 Intel® Turbo Boost Technology............................................................................43

3.4.1 Intel

Turbo Boost Technology Frequency............................................ .. .. ..43

3.4.2 Intel® Turbo Boost Technology Graphics Frequency.....................................43

3.5 Intel® Advanced Vector Extensions (Intel® AVX)....................................................44

3.6 Security and Cryptography Technologies...............................................................44

3.6.1 Intel

Advanced Encryption Standard New Instructions (Intel® AES-NI) ........44

3.6.2 PCLMULQDQ Instruction ..........................................................................44

3.6.3 RDRAND Instruction................................................................................45

3.7 Intel

64 Architecture x2APIC.............................................................................45

3.8 Supervisor Mode Execution Protection (SMEP) .......................................................46

3.9 Power Aware Interrupt Routing (PAIR)..................................................................46

4 Power Management .................................................................................................47

4.1 Advanced Configuration and Power Interface

(ACPI) States Supported.....................................................................................48

4.1.1 System States................................................................. .. .. ...................48

4.1.2 Processor Core / Package Idle States.........................................................48

4.1.3 Integrated Memory Controller States............................ .. ...........................48

4.1.4 PCI Express* Link States.........................................................................49

4.1.5 Direct Media Interface (DMI) States ..........................................................49

4.1.6 Processor Graphics Controller States .........................................................49

4.1.7 Interface State Combinations....................... ............................................49

4.2 Processor Core Power Management......................................................................50

4.2.1 Enhanced Intel

SpeedStep® Technology ..................................................50

4.2.2 Low-Power Idle States.............................................................................50

4.2.3 Requesting Low-Power Idle States ................................................ ............52

Datasheet, Volume 1



4.2.4 Core C-states ......................................................... .. .. ......................... ..52

4.2.4.1 Core C0 State...........................................................................52

4.2.4.2 Core C1 / C1E State..................................................................53

4.2.4.3 Core C3 State...........................................................................53

4.2.4.4 Core C6 State...........................................................................53

4.2.4.5 C-State Auto-Demotion .............................. .. .. .. .........................53

4.2.5 Package C-States.......... .. .. ......................... .. .. .......................... .. .. ..........54

4.2.5.1 Package C0..............................................................................55

4.2.5.2 Package C1/C1E .......................................................................55

4.2.5.3 Package C3 State......................................................................56

4.2.5.4 Package C6 State......................................................................56

4.3 Integrated Memory Controller (IMC) Power Management ........................................56

4.3.1 Disabling Unused System Memory Outputs ............................... ... .. .. .. .. ......56

4.3.2 DRAM Power Management and Initialization...............................................57

4.3.2.1 Initialization Role of CKE............................................................58

4.3.2.2 Conditional Self-Refresh ............................................................58

4.3.2.3 Dynamic Power Down Operation .................................................59

4.3.2.4 DRAM I/O Power Management....................................................59

4.3.3 DDR Electrical Power Gating (EPG) ...........................................................59

4.4 PCI Express* Power Management........................................................................60

4.5 DMI Power Management...................... ...............................................................60

4.6 Graphics Power Management..............................................................................60

4.6.1 Intel

4.6.2 Intel

4.6.3 Graphics Render C-State.........................................................................60

4.6.4 Intel

Rapid Memory Power Management (Intel® RMPM) 

(also known as CxSR).............................................................................60

Graphics Performance Modulation Technology (Intel® GPMT)..............60

Smart 2D Display Technology (Intel® S2DDT) .................................. 61

4.6.5 Intel® Graphics Dynamic Frequency..........................................................61

4.7 Graphics Thermal Power Management..................................................................61

5 Thermal Management..............................................................................................63

6 Signal Description ...................................................................................................65

6.1 System Memory Interface Signals............................ .. ............................ .. .. ..........66

6.2 Memory Reference and Compensation Signals.......................................................67

6.3 Reset and Miscellaneous Signals..........................................................................68

6.4 PCI Express*-based Interface Signals ..................................................................69

6.5 Intel

Flexible Display (Intel® FDI) Interface Signals.............................................69

6.6 Direct Media Interface (DMI) Signals....................................................................70

6.7 Phase Lock Loop (PLL) Signals ............................................................................70

6.8 Test Access Points (TAP) Signals .........................................................................70

6.9 Error and Thermal Protection Signals ...................................................................71

6.10 Power Sequencing Signals..................................................................................72

6.11 Processor Power Signals.....................................................................................73

6.12 Sense Signals............... .. .. ......................... ... .. ......................... .. .......................73

6.13 Ground and Non-Critical to Function (NCTF) Signals...............................................74

6.14 Processor Internal Pull-Up / Pull-Down Resistors....................................................74

7 Electrical Specifications...........................................................................................75

7.1 Power and Ground Lands....................................................................................75

7.2 Decoupling Guidelines........................................................................................75

7.2.1 Voltage Rail Decoupling...........................................................................75

7.3 Processor Clocking (BCLK[0], BCLK#[0])...................................................... .. .. ....76

7.3.1 Phase Lock Loop (PLL) Power Supply.........................................................76

7.4 VCC Voltage Identification (VID)..........................................................................76

7.5 System Agent (SA) V

VID................................................................................80

7.6 Reserved or Unused Signals................................................................................80

Datasheet, Volume 1 5

7.7 Signal Groups ...................................................................................................80

7.8 Test Access Port (TAP) Connection.................. ... .. .. ........................... .. .................82

7.9 Storage Conditions Specifications.........................................................................83

7.10 DC Specifications.................................. .. .. .......................... .. .. ......................... ..84

7.10.1 Voltage and Current Specifications... ............................ .. .. .. .......................84

7.11 Platform Environmental Control Interface (PECI) DC Specifications...........................90

7.11.1 PECI Bus Architecture..............................................................................90

7.11.2 DC Characteristics ........................... .. ... ........................... .......................91

7.11.3 Input Device Hysteresis....................................... .. ... .. .............................91

8 Processor Land and Signal Information....................................................................93

8.1 Processor Land Assignments ...............................................................................93

9 DDR Data Swizzling................................................................................................ 109

Figures

1-1 Desktop Processor Platform........................................................... ...........................10

1-2 Desktop Processor Compatibility Diagram ..................................................................18

2-1 Intel

2-2 PCI Express* Layering Diagram................................................................................28

2-3 Packet Flow Through the Layers ...............................................................................29

2-4 PCI Express* Related Register Structures in the Processor ...........................................30

2-5 PCI Express* Typical Operation 16 Lanes Mapping ......................................................31

2-6 Processor Graphics Controller Unit Block Diagram .......................................................33

2-7 Processor Display Block Diagram ..............................................................................36

4-1 Processor Power States ...........................................................................................47

4-2 Idle Power Management Breakdown of the Processor Cores..........................................51

4-3 Thread and Core C-State Entry and Exit.....................................................................51

4-4 Package C-State Entry and Exit ................................................... ........................... ..55

7-1 Example for PECI Host-Clients Connection..................................................................90

7-2 Input Device Hysteresis...........................................................................................91

8-1 LGA Socket Land Map..............................................................................................94

Flex Memory Technology Operation .................................................................26

Tables

1-1 Desktop 3rd Generation Intel® Core™ Processor Family, Desktop Intel® 

Pentium

1-2 Terminology...........................................................................................................19

1-3 Related Documents.................................................................................................22

2-1 Processor DIMM Support Summary by Product ...........................................................23

2-2 Supported UDIMM Module Configurations...................................................................24

2-3 Supported SO-DIMM Module Configurations (AIO Only)................................................24

2-4 System Memory Timing Support................ .. ..................................................... ........25

2-5 Reference Clock.................................................... .. ......................... .. .....................38

4-1 System States........................................................................................................48

4-2 Processor Core / Package State Support ....................................................................48

4-3 Integrated Memory Controller States.........................................................................48

4-4 PCI Express* Link States.........................................................................................49

4-5 Direct Media Interface (DMI) States ..........................................................................49

4-6 Processor Graphics Controller States .........................................................................49

4-7 G, S, and C State Combinations................................................................................49

4-8 Coordination of Thread Power States at the Core Level................................................51

4-9 P_LVLx to MWAIT Conversion...................................................................................52

4-10 Coordination of Core Power States at the Package Level ..............................................54

6-1 Signal Description Buffer Types ................................................................................65

Processor Family, and Desktop Intel® Celeron® Processor Family SKUs...........16

Datasheet, Volume 1



6-2 Memory Channel A Signals ......................................................................................66

6-3 Memory Channel B Signals ......................................................................................67

6-4 Memory Reference and Compensation.......................................................................67

6-5 Reset and Miscellaneous Signals...............................................................................68

6-6 PCI Express* Graphics Interface Signals....................................................................69

6-7 Intel

Flexible Display (Intel® FDI) Interface.............................................................69

6-8 Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface .......................70

6-9 Phase Lock Loop (PLL) Signals .................................................................................70

6-10 Test Access Points (TAP) Signals ..............................................................................70

6-11 Error and Thermal Protection Signals ........................................................................71

6-12 Power Sequencing Signals.......................................................................................72

6-13 Processor Power Signals..........................................................................................73

6-14 Sense Signals........................................................................................................73

6-15 Ground and Non-Critical to Function (NCTF) Signals....................................................74

6-16 Processor Internal Pull-Up / Pull-Down Resistors.........................................................74

7-1 VR 12.0 Voltage Identification Definition....................................................................77

7-2 Signal Groups 1 .....................................................................................................81

7-3 Storage Condition Ratings .......................................................................................83

7-4 Processor Core Active and Idle Mode DC Voltage and Current Specifications...................84

7-5 Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications........... 86

7-6 Processor Graphics VID based (V

) Supply DC Voltage and Current Specifications........87

AXG

7-7 DDR3 Signal Group DC Specifications........................................................................87

7-8 Control Sideband and TAP Signal Group DC Specifications ...........................................89

7-9 PCI Express* DC Specifications ................................................................................89

7-10 PECI DC Electrical Limits .........................................................................................91

8-1 Processor Land List by Land Name............................................................................95

9-1 DDR Data Swizzling Table – Channel A.................................................................... 110

9-2 DDR Data Swizzling table – Channel B .................................................................... 111

Datasheet, Volume 1 7

Revision History

Revision

Number

001 • Initial release April 2012 002

003

004

005

006

007

008 • Added Desktop Intel Pentium Processor A1018 November 2013

• Added Desktop 3rd Generation Intel i5-3475S, i5-3570, i5-3570S processors

• Updated Section 1.2.2, PCI Express*

• Updated Section 2.1.1, System Memory Technology Supported

• Updated Table 7-4, “Processor Core Active and Idle Mode DC Voltage and Current Specifications”. Added 65 W to 2011C.

• Minor edits throughout for clarity

• Added Intel Pentium G2120 and G2100T processors

• Added Desktop 3rd Generation Intel 3240, i3-3240T, i5-3330, i5-3330S, i5-3335S, i5-3350P processors

• Added Desktop 3rd Generation Intel

• Added Desktop Intel

• Added Desktop 3rd Generation Intel processor

• Added Desktop Intel

• Added Desktop 3rd Generation Intel

• Added Desktop Intel

Pentium® G2130, G2020, G2020T, G2010 processor

Celeron® G1620, G1610, G1610T processor

Pentium® G2140, G2120T, G2030, G2030T processor

Celeron® G1630, G1620, G1620T processor

Description Revision Date

Core™ i5-3470T, i5-3470, i5-3470S,

Core™ i3-3220, i3-3220T, i3-3225, i3-

Core™ i3-3210 processor

Core™ i3-3250, i3-3250T, i3-3245

Core™ i5-3340, i5-3340S processor

June 2012

September 2012

January 2013

June 2013

September 2013

§ §

Datasheet, Volume 1

Introduction

1 Introduction

The Desktop 3rd Generation Intel® Core™ processor family, Desktop Intel® Pentium® processor family , and Desktop Intel® Celeron® processor family are the next generation of 64-bit, multi-core processors built on 22-nanometer process technology. The processors are designed for a two-chip platform. The two-chip platform consists of a processor and a Platform Controller Hub (PCH) and enables higher performance, lower cost, easier validation, and improved x-y footprint. The processor includes an Integrated Display Engine, Processor Graphics, PCI Express ports, and an Integrated Memory Controller. The processor is designed for desktop platforms. The processor offers either 6 or 16 graphic execution units (EUs). The number of EU engines supported may vary between processor SKUs. The processor is offered in an 1155-land LGA package (H2). Figure 1-1 shows an example desktop platform block diagram.

The Datasheet provides DC specifications, pinout and signal definitions, interface functional descriptions, and additional feature information pertinent to the implementation and operation of the processor on its respective platform.

Note: Throughout this document, the Intel® 6 / 7 Series Chipset Platform Controller Hub may

Note: Throughout this document, the Desktop 3rd Generation Intel® Core™ processor family ,

Note: Some processor features are not available on all platforms. Refer to the processor

Note: The term “DT” refers to desktop platforms.

be referred to as “PCH”.

Desktop Intel family may be referred to simply as “processor”.

Desktop Intel family refer to the processor SKUs listed in

specification update for details.

Pentium® processor family, and Desktop Intel® Celeron® processor

Table 1-1.

Datasheet, Volume 1 9

Figure 1-1. Desktop Processor Platform

DMI2 x4

Discrete

Graphics (PEG)

Analog CRT

Gigabit

Network Connection

USB 2.0 / USB 3.0

Intel®HD Audio

FWH

Super I/O

Serial ATA

DDR3

PCI Express* 3.0

1 x16 or 2x8

8 PCI Express* 2.0

x1 Ports

(5 GT/s)

SPI

Digital Display x 3

PCI Express*

SPI Flash x 2

LPC

SMBUS 2.0

GPIO

WiFi / WiMax

Controller Link 1

PECI

Intel®6/7 Series

Chipset Families

Intel

Management

Engine

Intel

Processor

Note:

1. USB 3.0 is supported on the Intel

7 Series Chipset family only.

Introduction

10 Datasheet, Volume 1

Introduction

1.1 Processor Feature Details

• Four or two execution cores

• A 32-KB instruction and 32-KB data first-level cache (L1) for each core

• A 256-KB shared instruction / data second-level cache (L2) for each core

• Up to 8-MB shared instruction / data third-level cache (L3), shared among all cores

1.1.1 Supported Technologies

•Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d)

•Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Intel® Active Management Technology (Intel® AMT) 8.0

•Intel® Trusted Execution Technology (Intel® TXT)

•Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)

•Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)

•Intel® Hyper-Threading Technology (Intel® HT Technology)

•Intel® 64 Architecture

• Execute Disable Bit

•Intel® Turbo Boost Technology

•Intel® Advanced Vector Extensions (Intel® AVX)

•Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)

• PCLMULQDQ Instruction

• RDRAND instruction for random number generation

• SMEP – Supervisor Mode Execution Protection

• PAIR – Power Aware Interrupt Routing

1.2 Interfaces

1.2.1 System Memory Support

• T wo channels of DDR3 Unbuffered Dual In-Line Memory Modules (UDIMM) or DDR3 Unbuffered Small Outline Dual In-Line Memory Modules (SO-DIMM) with a maximum of two DIMMs per channel

• Single-channel and dual-channel memory organization modes

• Data burst length of eight for all memory organization modes

• Memory DDR3 data transfer rates of 1333 MT/s and 1600 MT/s. The DDR3 data transfer rates supported by the processor is dependent on the PCH SKU in the target platform:

— Desktop PCH platforms support 1333 MT/s and 1600 MT/s for One DIMM and

Two DIMMs per channel

— All In One platforms (AIO) support 1333 MT/s and 1600 MT/s for One DIMM

and Two DIMMs per channel

• 64-bit wide channels

• System Memory Interface I/O Voltage of 1.5 V

• DDR3 and DDR3L DIMMs/DRAMs running at 1.5 V

• No support for DDR3L DIMMs/DRAMS running at 1.35 V

Datasheet, Volume 1 11

Introduction

• Support memory configurations that mix DDR3 DIMMs/DRAMs with DDR3L DIMMs/DRAMs running at 1.5 V

• The type of the DIMM modules supported by the processor is dependent on the PCH SKU in the target platform:

— Desktop PCH platforms support non-ECC UDIMMs only — All In One platforms (AIO) support SO-DIMMs

• Theoretical Maximum Memory Bandwidth:

— 10.6 GB/s in single-channel mode or 21.3 GB/s in dual-channel mode assuming

DDR3 1333 MT/s

— 12.8 GB/s in single-channel mode or 25.6 GB/s in dual-channel mode assuming

DDR3 1600 MT/s

• Processor on-die Reference Voltage (VREF) generation for both DDR3 Read (RDVREF) and Write (VREFDQ)

• 1Gb, 2Gb, and 4Gb DDR3 DRAM device technologies are supported

— Using 4Gb DRAM device technologies, the largest memory capacity possible is

GB, assuming Dual Channel Mode with four x8 dual ranked DIMM memory

configuration

• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank devices)

• Command launch modes of 1N/2N

• On-Die Termination (ODT)

• Asynchronous ODT

•Intel® Fast Memory Access (Intel® FMA):

— Just-in-Time Command Scheduling —Command Overlap — Out-of-Order Scheduling

1.2.2 PCI Express*

• The PCI Express* lanes (PEG[15:0] TX and RX) are fully-compliant to the PCI Express Base Specification, Revision 3.0, including support for 8.0 GT/s transfer

speeds.

• Processor with Desktop PCH Supports (may vary depending on PCH SKUs)

12 Datasheet, Volume 1

• PCI Express* supported configurations in desktop products

Configuration Organization Desktop

2 2x8 Graphics, I/O 3 1x16 Graphics, I/O

1x8 2x4

Graphics, I/O

• The port may negotiate down to narrower widths

— Support for x16/x8/x4/x2/x1 widths for a single PCI Express* mode

• 2.5 GT/s, 5.0 GT/s and 8.0 GT/s PCI Express* frequencies are supported

• Gen1 Raw bit-rate on the data pins Gen 2 Raw bit -rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per pair of 500 MB/s given the 8b/10b encoding used

Introduction

to transmit data across this interface. This also does not account for packet overhead and link maintenance.

• Maximum theoretical bandwidth on the interface of 8 GB/s in each direction simultaneously, for an aggregate of 16 GB/s when x16 Gen 2

• Gen 3 raw bit-rate on the data pins of 8.0 GT/s, resulting in a real bandwidth per pair of 984 MB/s using 128b/130b encoding to transmit data across this interface. This also does not account for packet overhead and link maintenance.

• Maximum theoretical bandwidth on the interface of 16 GB/s in each direction simultaneously, for an aggregate of 32 GB/s when x16 Gen 3

• Hierarchical PCI-compliant configuration mechanism for downstream devices

• Traditional PCI style traffic (asynchronous snooped, PCI ordering)

• PCI Express* extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space.

• PCI Express* Enhanced Access Mechanism. Accessing the device configuration space in a flat memory mapped fashion.

• Automatic discovery, negotiation, and training of link out of reset

• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)

• Peer segment destination posted write traffic (no peer-to-peer read traffic) in Virtual Channel 0:

— DMI -> PCI Express* Port 0

• 64-bit downstream address format; however, the processor never generates an address above 64 GB (Bits 63:36 will always be zeros)

• 64-bit upstream address format; however, the processor responds to upstream read transactions to addresses above 64 GB (address e s wh ere any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64

GB will be dropped.

• Re-issues Configuration cycles that have been previously completed with the Configuration Retry status

• PCI Express* reference clock is 100-MHz differential clock

• Power Management Event (PME) functions

• Dynamic width capability

• Message Signaled Interrupt (MSI and MSI-X) messages

• Polarity inversion

Note: The processor does not support PCI Express* Hot-Plug.

Datasheet, Volume 1 13

1.2.3 Direct Media Interface (DMI)

• DMI 2.0 support

• Four lanes in each direction

• 5 GT/s point-to-point DMI interface to PCH is supported

• Raw bit-rate on the data pins of 5.0 Gb/s, resulting in a real bandwidth per pair of 500 MB/s given the 8b/10b encoding used to transmit data across this interface. Does not account for packet overhead and link maintenance.

• Maximum theoretical bandwidth on interface of 2 GB/s in each direction simultaneously, for an aggregate of 4 GB/s when DMI x4

• Shares 100-MHz PCI Express* reference clock

• 64-bit downstream address format; however, the processor never generates an address above 64 GB (Bits 63:36 will always be zeros)

• 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped.

• Supports the following traffic types to or from the PCH:

—DMI -> DRAM — DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only) — Processor core -> DMI

• APIC and MSI interrupt messaging support:

— Message Signaled Interrupt (MSI and MSI-X) messages

• Downstream SMI, SCI and SERR error indication

• Legacy support for ISA regime protocol (PHOLD / PHOLDA) required for parallel port DMA, floppy drive, and LPC bus masters

• DC coupling – no capacitors between the processor and the PCH

• Polarity inversion

• PCH end-to-end lane reversal across the link

• Supports Half Swing “low-power / low-voltage”

Introduction

1.2.4 Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between a PECI client (the processor) and a PECI master. The processor supports the PECI 3.0 Specification.

1.2.5 Processor Graphics

• The Processor Graphics contains a refresh of the seventh generation graphics core enabling substantial gains in performance and lower power consumption. Up to

EU support.

• Next Generation Intel Clear Video Technology HD Support is a collection of video playback and enhancement features that improve the end user’s viewing experience

— Encode / transcode HD content — Playback of high definition content including Blu-ray Disc* — Superior image quality with sharper, more colorful images — Playback of Blu-ray Disc* S3D content using HDMI* (V.1.4 with 3D)

14 Datasheet, Volume 1

Introduction

• DirectX* Video Acceleration (DXVA) support for accelerating video processing — Full AVC/VC1/MPEG2 HW Decode

• Advanced Scheduler 2.0, 1.0, XPDM support

• Windows* 7, Windows* XP, OSX, Linux OS Support

• DirectX* 11, DirectX* 10.1, DirectX* 10, DirectX* 9 support

•OpenGL* 3.0 support

• Switchable Graphics support on Desktop AIO platforms with MxM solutions only

1.2.6 Intel® Flexible Display Interface (Intel® FDI)

• For SKUs with graphics, carries display traffic from the Processor Graphics in the

processor to the legacy display connectors in the PCH

• Based on DisplayPort standard

• The two Intel FDI links are capable of being configured to support three

independent channels, one for each display pipeline

• There are two Intel FDI channels, each one consists of four unidirectional

downstream differential transmitter pairs:

— Scalable down to 3X, 2X, or 1X based on actual display bandwidth

requirements

— Fixed frequency 2.7 GT/s data rate

• Two sideband signals for display synchronization: — FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization)

• One Interrupt signal used for various interrupts from the PCH: — FDI_INT signal shared by both Intel FDI Links

• PCH supports end-to-end lane reversal across both links

• Common 100-MHz reference clock

1.3 Power Management Support

1.3.1 Processor Core

• Full support of ACPI C-states as implemented by the following processor C-states: — C0, C1, C1E, C3, C6

• Enhanced Intel SpeedStep Technology

1.3.2 System

• S0, S3, S4, S5

1.3.3 Memory Controller

• Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM))

• Dynamic power down

1.3.4 PCI Express*

• L0s and L1 ASPM power management capability

Datasheet, Volume 1 15

1.3.5 Direct Media Interface (DMI)

• L0s and L1 ASPM power management capability

1.3.6 Processor Graphics Controller (GT)

•Intel® Rapid Memory Power Management (Intel® RMPM) – CxSR

•Intel® Graphics Performance Modulation Technology (Intel® GPMT)

•Intel® Smart 2D Display Technology (Intel® S2DDT)

• Graphics Render C-State (RC6)

1.3.7 Thermal Management Support

• Digital Thermal Sensor

• Intel Adaptive Thermal Monitor

• THERMTRIP# and PROCHOT# support

• On-Demand Mode

• Memory Thermal Throttling

• External Thermal Sensor (TS-on-DIMM and TS-on-Board)

• Render Thermal Throttling

• Fan speed control with DTS

Introduction

1.4 Processor SKU Definitions

Table 1-1. Desktop 3rd Generation Intel® Core™ Processor Family, Desktop Intel® 

Pentium SKUs (Sheet 1 of 2)

Processor

Processor Family, and Desktop Intel® Celeron® Processor Family

Number

i7-3770T 45 1600 MHz 2.5 GHz up to 3.7 GHz 650 MHz up to 1150 MHz 94 i7-3770S 65 1600 MHz 3.1 GHz up to 3.9 GHz 650 MHz up to 1150 MHz 103 i7-3770K 77 1600 MHz 3.5 GHz up to 3.9 GHz 650 MHz up to 1150 MHz 105

i7-3770 77 1600 MHz 3.4 GHz up to 3.9 GHz 650 MHz up to 1150 MHz 105 i5-3570T 45 1600 MHz 2.3 GHz up to 3.3 GHz 650 MHz up to 1150 MHz 94 i5-3570S 65 1600 MHz 3.1 GHz up to 3.8 GHz 650 MHz up to 1150 MHz 103 i5-3570K 77 1600 MHz 3.4 GHz up to 3.8 GHz 650 MHz up to 1150 MHz 105

i5-3570 77 1600 MHz 3.4 GHz up to 3.8 GHz 650 MHz up to 1150 MHz 105 i5-3550S 65 1600 MHz 3 GHz up to 3.7 GHz 650 MHz up to 1150 MHz 103

i5-3550 77 1600 MHz 3.3 GHz up to 3.7 GHz 650 MHz up to 1150 MHz 105 i5-3475S 65 1600 MHz 2.9 GHz up to 3.6 GHz 650 MHz up to 1100 MHz 103 i5-3470S 65 1600 MHz 2.9 GHz up to 3.6 GHz 650 MHz up to 1100 MHz 103 i5-3470T 35 1600 MHz 2.9 GHz up to 3.6 GHz 650 MHz up to 1100 MHz, 91

i5-3470 77 1600 MHz 3.2 GHz up to 3.6 GHz 650 MHz up to 1100 MHz 105 i5-3450S 65 1600 MHz 2.8 GHz up to 3.5 GHz 650 MHz up to 1100 MHz 103

i5-3450 77 1600 MHz 3.1 GHz up to 3.5 GHz 650 MHz up to 1100 MHz 105 i5-3350P 69 1600 MHz 3.1 GHZ up to 3.3 GHZ N/A 105

i5-3340 77 1600 MHz 3.1 GHZ up to 3.3 GHZ 650 MHz up to 1050 MHz 105

TDP (W)

IA LFM

Frequency

IA Frequency range GT Frequency range

jMAX

(°C)

16 Datasheet, Volume 1

Introduction

Table 1-1. Desktop 3rd Generation Intel® Core™ Processor Family, Desktop Intel® 

Pentium

Processor Family, and Desktop Intel® Celeron® Processor Family

SKUs (Sheet 2 of 2)

Processor

Number

i5-3340S 65 1600 MHz 3.0 GHZ up to 3.3 GHZ 650 MHz up to 1050 MHz 103 i5-3335S 65 1600 MHz 2.7 GHz up to 3.2 GHz 650 MHz up to 1050 MHz 103 i5-3330S 65 1600 MHz 2.7 GHz up to 3.2 GHz 650 MHz up to 1050 MHz 103

i3-3250T 35 1600 MHz N/A 650 MHz up to 1050 MHz 91

i3-3250 55 1600 MHz N/A 650 MHz up to 1050 MHz 105 i3-3245 55 1600 MHz N/A 650 MHz up to 1050 MHz 105 i5-3330 77 1600 MHz 3 GHz up to 3.2 GHz 650 MHz up to 1050 MHz 105

i3-3240T 35 1600 MHz Up to 3.0 GHz 650 MHz up to 1050 MHz 91

i3-3240 55 1600 MHz Up to 3.4 GHz 650 MHz up to 1050 MHz 105 i3-3225 55 1600 MHz Up to 3.3 GHz 650 MHz up to 1050 MHz 105

i3-3220T 35 1600 MHz Up to 2.8 GHz 650 MHz up to 1050 MHz 91

i3-3220 55 1600 MHz Up to 3.3 GHz 650 MHz up to 1050 MHz 105 i3-3210 55 1600 MHz Up to 3.2 GHz 650 MHz up to 1050 MHz 105

G2140 55 1600 MHz N/A 650 MHz up to 1050 MHz 105 G2130 55 1600 MHz Up to 3.2 GHz 650 MHz up to 1050 MHz 105

G2120T 3 5 1600 MHz N/A 650 MHz up to 1050 MHz 91

G2120 55 1600 MHz 3.1 GHZ 650 MHZ up to 1.05 GHZ 105 G2100T 35 1600 MHz 2.6 GHZ 650 MHZ up to 1.05 GHZ 91 G2030T 3 5 1600 MHz N/A 650 MHz up to 1050 MHz 91

G2030 35 1600 MHz N/A 650 MHz up to 1050 MHz 105

G2020 55 1600 MHz 2.9 GHZ 650 MHZ up to 1050 MHz 105 G2020T 3 5 1600 MHz 2.5 GHZ 650 MHZ up to 1050 MHz 91

G2010 55 1600 MHz 2.8 GHZ 650 MHZ up to 1050 MHz 105

G1630 55 1600 MHz 2.8 GHZ 650 MHZ up to 1050 MHz 105

G1620 55 1600 MHz 2.7 GHZ 650 MHZ up to 1050 MHz 105 G1620T 3 5 1600 MHz 2.4 GHZ 650 MHZ up to 1050 MHz 91

G1610 55 1600 MHz 2.6 GHZ 650 MHZ up to 1050 MHz 105 G1610T 3 5 1600 MHz 2.3 GHZ 650 MHZ up to 1050 MHz 91

A1018 35 1600 MHz 2.1 GHz 650 MHz up to 1 GHz 105

TDP (W)

IA LFM

Frequency

IA Frequency range GT Frequency range

jMAX

(°C)

1.5 Package

The processor socket type is noted as LGA 1155. The package is a 37.5 x 37.5 mm Flip Chip Land Grid Array (FCLGA 1155). See the Desktop 3rd Generation Intel

Processor Family, Desktop Intel

Pentium® Processor Family, Desktop Intel® Celeron® Processor Family, and LGA1155 Socket Thermal / Mechanical Specifications and Design Guidelines for complete details on the package.

Datasheet, Volume 1 17

Core™

1.6 Processor Compatibility

2 x 330 µF

2 x 330 µF + 1 placeholder

VCCIO

VDDQ

VCore

VCCSA

VAXG

DDR3

G2_Core: 1.5 V

G3_Core: 1.5 V

G2_Core: 1.05 V

G3_Core: 1.05 V

VCCIO_SEL#

G2_Core: ‘1’

G3_Core: ‘1’

Processor

PCH

VCCSA_VID

G2_Core: ‘0’

G3_Core: ‘0’

G2_Core: 0.925 V

G3_Core: 0.925 V

PEG AC Decoupling

PEG Gen 1,2 – 100 nF

PEG Gen 1,2,3 – 220 nF

*VAXG: 2 ph required for some of the SKUs

SVID

PROC_SELECT#

G2_Core: ‘1’

G3_Core: ‘0’

Controls DMI And FDI termination

DF_TVS

The Desktop 3rd Generation Intel® Core™ processor family, Desktop Intel® Pentium® processor family, Desktop Intel requirements that differentiate it from a 2nd Generation Intel® Core™ processor family Desktop, Intel

Pentium® processor family Desktop, Intel® Celeron® processor Family Desktop processor. Platforms intending to support both processor families need to address the platform compatibility requirements detailed in Figure 1-2.

Figure 1-2. Desktop Processor Compatibility Diagram

Celeron® processor Family has specific platform

Introduction

18 Datasheet, Volume 1

Notes:

1. G2_Core = 2nd Generation Intel

2. G3_Core = Desktop 3rd Generation Intel

family Desktop, Intel

processor, Desktop Intel

Celeron® processor family Desktop,

Core™ processor family Desktop, Intel® Pentium® processor

Celeron® processor family

Core™ processor family, Desktop Intel® Pentium®

Introduction

1.7 Terminology

Table 1-2. Terminology (Sheet 1 of 3)

Term Description

ACPI Advanced Configuration and Power Interface ADB Automatic Display Brightness APD Active Power Down ASPM Active State Power Management BGA Ball Grid Array BLT Block Level Transfer CLTT Closed Loop T hermal Throttling CRT Cathode Ray Tube cTDP Configurable Thermal Design Power DDDR3L-RS DDR3L Reduced Standby Power DDR3 Third-generation Double Data Rate SDRAM memory technology DDR3L DDR3 Low Voltage DMA Direct Memory Access DMI Direct Media Interface DP DisplayPort* DPST Display Power Savings Technology DTS Digital Thermal Sensor EC Embedded Controller ECC Error Correction Code eDP* Embedded DisplayPort* Enhanced Intel

SpeedStep Technology

EPG Electrical Power Gating EU Execution Unit

Execute Disable Bit

HDMI* High Definition Multimedia Interface HFM High Frequency Mode IMC Integrated Memory Controller

Intel

64 Technology 64-bit memory extensions to the IA-32 architecture

Intel

DPST Intel® Display Power Saving Technology

Intel

FDI Intel® Flexible Display Interface

Intel

TXT Intel® Trusted Execution Technology

Intel

Virtualization

Technology

Technology that provides power management capabilities to laptops.

The Execute Disable bit allows memory to be marked as executable or non-executable, when combined with a supporting operating system. If code attempts to run in nonexecutable memory the processor r aises an error t o the operat ing system. This featu re can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the

Intel

64 and IA-32 Architectures Software Developer's Manuals for more detailed

information.

Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform.

Datasheet, Volume 1 19

Table 1-2. Terminology (Sheet 2 of 3)

Term Description

Virtualization T echnology (Intel® VT) for Directed I/O. Intel VT -d is a hardware

Intel

VT-d

IOV I/O Virtualization

ISA

ITPM Integrated Trusted Platform Module LCD Liquid Crystal Display LFM Low Frequency Mode LPC Low Pin Count LPM Low Power Mode

LVDS

MLE Measured Launched Environment MSI Message Signaled Interrupt

NCTF

ODT On-Die Termination PAIR Power Aware Interrupt Routing

PCH

PECI Platform Environment Control Interface.

PEG

PGA Pin Grid Array PLL Phase Lock Loop PME Power Management Event PPD Precharged Power Down Processor The 64-bit, single-core or multi-core component (package).

Processor Core

Processor Graphics Intel Processor Graphics

Rank

SCI System Control Interrupt. Used in ACPI protocol. Intel SDRRS

Technology SMEP Supervis or Mode Execution Protection

assist, under system software (Virtual Machine Manager or operating system) control, for enabling I/O device virtualization. Intel VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d.

Industry Standard Architecture. Th is is a legacy computer bus standard for IBM PC compatible computers.

Low Voltage Differential Signaling. A high speed, low power data transmission standard used for display connections to LCD panels.

Non-Critical to Function. NCTF locations are typically redundant ground or non-critical reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality.

Platform Controller Hub. The chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security and storage features.

PCI Express* Graphics. External Graphics using PCI Express* Architecture. A highspeed serial interface whose configuration is software compatible with the existing PCI specifications.

The term “processor core” refers to Si die itself that can contain multiple execution cores. Each execution core has an ins truction cache, data cache , and 256-KB L2 cache. All execution cores share the L3 cache.

A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a SO-DIMM.

Intel Seamless Display Refresh Rate Switching Technology

Introduction

20 Datasheet, Volume 1

Introduction

Table 1-2. Terminology (Sheet 3 of 3)

Term Description

A non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these

Storage Conditions

SVID Serial Voltage IDentification interface TAC Thermal Averaging Constant TAP Test Access Point TCC Thermal Control Circuit TDC Thermal Design Current TDP Thermal Design Power TLP Transaction Layer Packet V

AXG

CCIO

CCPLL

CCSA

DDQ

VGA Video Graphics Array VID Voltage Identification VLD Variable Length Decoding VLW Virtual Legacy Wire VR Voltage Regulator V

VTS Virtual Temperature Sensor x1 Refers to a Link or Port with one Physical Lane. x16 Refers to a Link or Port with sixteen Physical Lanes. x4 Refers to a Link or Port with four Physical Lanes. x8 Refers to a Link or Port with eight Physical Lanes.

conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (that is, unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.

Graphics core power supply Processor core power supply High Frequency I/O logic power supply PLL power supply System Agent (memory controller, DMI, PCIe controllers, and display engine) power

supply DDR3 power supply

Processor ground

Datasheet, Volume 1 21

1.8 Related Documents

Table 1-3. Related Documents

Introduction

Document

Desktop 3rd Generation Intel

Pentium Datasheet, Volume 2

Desktop 3rd Generation Intel Pentium Specification Update

Desktop 3rd Generation Intel Pentium LGA1155 Socket Thermal / Mechanical Specifications and Design Guidelines

Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info/ PCI Local Bus Specification 3.0 http://www.pcisig.com/speci

PCI Express* Base Specification 2.0 http://www.pcisig.com DDR3 SDRAM Specification http://www.jedec.org DisplayPort* Specification http://www.vesa.org Intel

Processor Family, and Desktop Intel® Celeron® Processor Family

Processor Family, Desktop Intel® Celeron® Processor Family, and

64 and IA-32 Architectures Software Developer's Manuals http://www.intel.com/produ

Volume 1: Basic Architecture 253665 Volume 2A: Instruction Set Reference, A-M 253666 Volume 2B: Instruction Set Reference, N-Z 253667 Volume 3A: System Programming Guide 253668 Volume 3B: System Programming Guide 253669

Core™ Processor Family, Desktop Intel®

Document Number /

Location

326765

326766

326767

fications

cts/processor/manuals/inde

x.htm

Note: Contact your Intel representative for the latest revision of this item.

§ §

22 Datasheet, Volume 1

Interfaces

2 Interfaces

This chapter describes the interfaces supported by the processor.

2.1 System Memory Interface

2.1.1 System Memory Technology Supported

The Integrated Memory Controller (IMC) supports DDR3 / DDR3L protocols with two independent, 64-bit wide channels, each accessing one or two DIMMs. The type of memory supported by the processor is dependant on the PCH SKU in the target platform. Refer to Chapter 1 for supported memory configuration details.

Note: The processor supports only JEDEC approved memory modules and devices. Note: The IMC supports a maximum of two DIMMs per channel; thus, allowing up to four

device ranks per channel.

Note: The supported memory interface frequencies and number of DIMMs per channel are

SKU dependent.

Table 2-1. Processor DIMM Support Summary by Product

Processor

cores

Dual Core, Quad Core

Note: There is no support for DDR3L DIMMs/DRAMS running at 1.35 V.

Package

uLGA

DIMM per

channel

1 DPC 2 DPC 1333,1600 1333/1600 1 DPC 2 DPC 1333/1600 1333/1600

DIMM type DDR3 DDR3L at 1.5 V

SO-DIMM

UDIMM

1333/1600 1333/1600

• DDR3 / DDR3L at 1.5 V Data Transfer Rates — 1333 MT/s (PC3-10600), 1600 MT/s (PC3-12800)

• DDR3 / DDR3L at 1.5 V SO-DIMM Modules — Raw Card A – Dual Ranked x16 unbuffered non-ECC — Raw Card B – Single Ranked x8 unbuffered non-ECC

— Raw Card C – Single Ranked x16 unbuffered non-ECC — Raw Card F – Dual Ranked x8 (planar) unbuffered non-ECC

• Desktop platform DDR3/DDR3L at 1.5 V UDIMM Modules — Raw Card A – Single Ranked x8 unbuffered non-ECC

— Raw Card B – Dual Ranked x8 unbuffered non-ECC — Raw Card C – Single Ranked x16 unbuffered non-ECC

Note: The processor supports memory configurations that mix DDR3 DIMMs / DRAMs with

DDR3L DIMMs / DRAMs running at 1.5

Datasheet, Volume 1 23

Table 2-2. Supported UDIMM Module Configurations

Raw

Card

Version

DIMM

Capacity

DRAM

Device

Technology

DRAM

Organization

# of

DRAM

Devices

# of

Physical

Device

Ranks

# of

Row/Col

Address

Bits

Interfaces

# of Banks Inside DRAM

Page

Size

Unbuffered/Non-ECC Supported DIMM Module Configurations

1 GB 1 Gb 128 M X 8 8 1 14/10 8 8K

C 1 GB 2 Gb 128 M X 16 4 1 14/10 8 16K

Note:

1. DIMM module support is based on availability and is subject to change.

2 GB 2 Gb 128 M X 16 8 1 1510 8 8K 4 GB 4 Gb 512 M X 8 8 1 15/10 8 8K 2 GB 1 Gb 128 M X 8 16 2 14/10 8 8K 4 GB 2 Gb 256 M X 8 16 2 15/10 8 8K 8 GB 4 Gb 512 M X 8 16 2 16/10 8 8K

Desktop Platforms:

Table 2-3. Supported SO-DIMM Module Configurations (AIO Only)

Raw

Card

Version

DIMM

Capacity

2 GB 2 Gb 128 M x 16 8 2 14/10 8 8K 4 GB 4 Gb 256 M x 16 8 2 15/10 8 8K 1 GB 1 Gb 128 M x 8 8 1 14/10 8 8K 2 GB 2 Gb 256 M x 8 8 1 15/10 8 8K 4 GB 4 Gb 512 M x 8 8 1 16/10 8 8K 1 GB 2 Gb 128 M x 16 4 1 14/10 8 8K 2 GB 4 Gb 256 M x 16 4 1 15/10 8 8K 2 GB 1 Gb 128 M x 8 16 2 14/10 8 8K 4 GB 2 Gb 256 M x 8 16 2 15/10 8 8K 8 GB 4 Gb 512 M x 8 16 2 16/ 10 8 8K

DRAM

Device

Technology

DRAM

Organization

# of

DRAM

Devices

# of

Physical

Device

Ranks

# of

Row/Col

Address

Bits

# of

Banks

Inside

DRAM

Page

Size

Note:

1. System memory configurations are based on availability and are subject to change.

2.1.2 System Memory Timing Support

The IMC supports the following Speed Bins, CAS Write Latency (CWL), and command signal mode timings on the main memory interface:

• tCL = CAS Latency

• tRCD = Activate Command to READ or WRITE Command delay

• tRP = PRECHARGE Command Period

• CWL = CAS Write Latency

• Command Signal modes = 1N indicates a new command may be issued every clock and 2N indicates a new command may be issued every 2 clocks. Command launch mode programming depends on the transfer rate and memory configuration.

24 Datasheet, Volume 1

Interfaces

Table 2-4. System Memory Timing Support

Segment

Desktop

AIO

Note:

1. System memory timing support is based on availability and is subject to change.

Transfer

Rate

(MT/s)

1333 9 9 9 7

1600 11 11 11 8

1333 9 9 9 7

1600 11 11 11 8 1 1N/2N

tCL

(tCK)

tRCD

(tCK)

tRP

(tCK)

2.1.3 System Memory Organization Modes

The IMC supports two memory organization modes, single-channel and dual-channel. Depending upon how the DIMM Modules are populated in each memory channel, a number of different configurations can exist.

2.1.3.1 Single-Channel Mode

In this mode, all memory cycles are directed to a single-channel. Single-channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order, but not both.

CWL

(tCK)

DPC

11N/2N 22N 11N/2N 22N 11N/2N 22N

CMD

Mode

Notes

2.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode

The IMC supports Intel Flex Memory Technology Mode. Memory is divided into a symmetric and a asymmetric zone. The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached. In this mode, the system runs with one zone of dual-channel mode and one zone of single-channel mode, simultaneously, across the whole memory array.

Note: Channels A and B can be mapped for physical channel 0 and 1 respectively or vice

versa; however, channel A size must be greater or equal to channel B size.

Datasheet, Volume 1 25

Figure 2-1. Intel® Flex Memory Technology Operation

CH BCH A

B B

Non interleaved access

Dual channel interleaved access

TOM

CH A and C H B can be configured to be physical channels 0 or 1 B – The largest physical mem ory amount of the sm aller size me m ory module C – The rema ining physical m em ory amoun t of the larger size m em ory mod ule

Interfaces

2.1.3.2.1 Dual-Channel Symmetric Mode

Note: The DRAM device technology and width may vary from one channel to the other.

2.1.4 Rules for Populating Memory Slots

Note: In a Two DIMM Per Channel (2DPC) daisy chain layout memory configuration, the

Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum performance on real world applications. Addresses are ping-ponged between the channels after each cache line (64-byte boundary). If there are two requests, and the second request is to an address on the opposite channel from the first, that request can be sent before data from the first request has returned. If two consecutive cache lines are requested, both may be retrieved simultaneously, since they are ensured to be on opposite channels. Use Dual-Channel Symmetric mode when both Channel A and Channel B DIMM connectors are populated in any order, with the total amount of memory in each channel being the same.

When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory, the IMC operates completely in Dual-Channel Symmetric mode.

In all System Memory Organization Modes, the frequency and latency timings of the system memory is the lowest supported frequency and slowest supported latency timings of all memory DIMM modules placed in the system, as determined through the SPD registers.

furthest DIMM from the processor of any given channel must always be populated first.

26 Datasheet, Volume 1

Interfaces

2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements.

2.1.5.1 Just-in-Time Command Scheduling

The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next. The most efficient request is picked from all pending requests and issued to system memory Just-in-Time to make optimal use of Command Overlapping. Thus, instead of having all memory access requests go individually through an arbitration mechanism forcing requests to be executed one at a time, they can be started without interfering with the current request allowing for concurrent issuing of requests. This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol.

2.1.5.2 Command Overlap

Command Overlap allows the insertion of the DRAM commands between the Activate, Precharge, and Read/Write commands normally used, as long as the inserted commands do not affect the currently executing command. Multiple commands can be issued in an overlapping manner, increasing the efficiency of system memory protocol.

2.1.5.3 Out-of-Order Scheduling

While leveraging the Just-in-Time Scheduling and Command Overlap enhancements, the IMC continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency. If there are multiple requests to the same open page, these requests would be launched in a back to back manner to make optimum use of the open memory page. This ability to reorder requests on the fly allows the IMC to further reduce latency and increase bandwidth efficiency.

2.1.6 Data Scrambling

The memory controller incorporates a DDR3 Data Scrambling feature to minimize the impact of excessive di/dt on the platform DDR3 VRs due to successive 1s and 0s on the data bus. Past experience has demonstrated that traffic on the data bus is not r andom. Rather, it can have energy concentrated at specific spectral harmonics creating high di/dt that is generally limited by data patterns that excite resonance between the package inductance and on die capacitances. As a result the memory controller uses a data scrambling feature to create pseudo-random patterns on the DDR3 data bus to reduce the impact of any excessive di/dt.

2.1.7 DDR3 Reference Voltage Generation

The processor memory controller has the capability of generating the DDR3 Reference Voltage (VREF) internally for both read (RDVREF) and write (VREFDQ) operations. The generated VREF can be changed in small steps, and an optimum VREF value is determined for both during a cold boot through advanced DDR3 training procedures in order to provide the best voltage and signal margins.

Datasheet, Volume 1 27

2.2 PCI Express* Interface

Transaction

Data Link

Physical

Logical Sub-block

Electrical Sub-block

RX TX

Transaction

Data Link

Physical

Logical Sub-block

Electrical Sub-block

RX TX

This section describes the PCI Express interface capabilities of the processor. See the PCI Express Base Specification for details of PCI Express.

The number of PCI Express controllers is dependent on the platform. Refer to Chapter 1 for details.

2.2.1 PCI Express* Architecture

Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers may operate unchanged.

The PCI Express configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification. The processor external graphics ports support Gen 3 speed as well. At 8 GT/s, Gen 3 operation results in twice as much bandwidth per lane as compared to Gen 2 operation. The 16-lane PCI Express* graphics port can operate at either 2.5 GT/s, 5 GT/s, or 8 GT/s.

PCI Express* Gen 3 uses a 128/130b encoding scheme, eliminating nearly all of the overhead of the 8b/10b encoding scheme used in Gen 1 and Gen 2 operation.

Interfaces

The PCI Express architecture is specified in three layers – Transaction Layer, Data Link Layer, and Physical Layer. The partitioning in the component is not necessarily along these same boundaries. Refer to Figure 2-2 for the PCI Express layering diagram.

Figure 2-2. PCI Express* Layering Diagram

PCI Express uses packets to communicate information between components. Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side, the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device.

28 Datasheet, Volume 1

Interfaces

Sequence

Number

Framing Header Data ECRC LCRC Framing

Transaction Layer

Data Link Layer

Physical Layer

Figure 2-3. Packet Flow Through the Layers

2.2.1.1 Transaction Layer

The upper layer of the PCI Express* architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events. The Transaction Layer also manages flow control of TLPs.

2.2.1.2 Data Link Layer

The middle layer in the PCI Express stack, the Data Link Layer, serves as an intermediate stage between the Transaction Layer and the Physical Layer. Responsibilities of Data Link Layer include link management, error detection, and error correction.

The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer, calculates and applies data protection code and TLP sequence number, and submits them to Physical Layer for transmission across the Link. The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the T ransaction Layer for further processing. On detection of TLP error(s), this layer is responsible for requesting retransm ission of TLPs until information is correctly received, or the Link is determined to have failed. The Data Link Layer also generates and consumes packets which are used for Link management functions.

2.2.1.3 Physical Layer

The Physical Layer includes all circuitry for interface operation, including driver and input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), clock recovery circuits and impedance matching circuitry. It also includes logical functions related to interface initialization and maintenance. The Physical Layer exchanges data with the Data Link Layer in an implementation-specific format, and is responsible for converting this to an appropriate serialized format and transmitting it across the PCI Express Link at a frequency and width compatible with the remote device.

Datasheet, Volume 1 29

2.2.2 PCI Express* Configuration Mechanism

PCI-PCI Bridge

representing

root PCI

Express* ports

(Device 1 and

Device 6)

PCI Compatible

Host Bridge

Device

(Device 0)

PCI

Express*

Device

PEG0

DMI

The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure.

Figure 2-4. PCI Express* Related Register Structures in the Processor

Interfaces

PCI Express extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express configuration space is divided into a PCI-compatible region (that consists of the first 256 bytes of a logical device's configuration space) and an extended PCI Express region (that consists of the remaining configuration space). The PCI-compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express configuration access mechanism described in the PCI Express Enhanced Configuration Mechanism section.

The PCI Express Host Bridge is required to translate the memory-mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is recommended that system software access the enhanced configuration space using 32-bit operations (32-bit aligned) only. See the PCI Express Base Specification for details of both the PCI-compatible and PCI Express Enhanced configuration mechanisms and transaction rules.

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+ 82 hidden pages

Intel BX80637G2010 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Revision History

1 Introduction

1.1 Processor Feature Details

1.1.1 Supported Technologies

1.2 Interfaces

1.2.1 System Memory Support

1.2.2 PCI Express*

1.2.3 Direct Media Interface (DMI)

1.2.4 Platform Environment Control Interface (PECI)

1.2.5 Processor Graphics

1.2.6 Intel® Flexible Display Interface (Intel® FDI)

1.3 Power Management Support

1.3.1 Processor Core

1.3.2 System

1.3.3 Memory Controller

1.3.4 PCI Express*

1.3.5 Direct Media Interface (DMI)

1.3.6 Processor Graphics Controller (GT)

1.3.7 Thermal Management Support

1.4 Processor SKU Definitions

1.5 Package

1.6 Processor Compatibility

1.7 Terminology

1.8 Related Documents

2 Interfaces

2.1 System Memory Interface

2.1.1 System Memory Technology Supported

2.1.2 System Memory Timing Support

2.1.3 System Memory Organization Modes

2.1.3.1 Single-Channel Mode

2.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode

2.1.4 Rules for Populating Memory Slots

2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

2.1.5.1 Just-in-Time Command Scheduling

2.1.5.2 Command Overlap

2.1.5.3 Out-of-Order Scheduling

2.1.6 Data Scrambling

2.1.7 DDR3 Reference Voltage Generation

2.2 PCI Express* Interface

2.2.1 PCI Express* Architecture

2.2.1.1 Transaction Layer

2.2.1.2 Data Link Layer

2.2.1.3 Physical Layer

2.2.2 PCI Express* Configuration Mechanism