The Intel® Desktop Board DP35DP may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current
characterized errata are documented in the Intel Desktop Board DP35DP Specification Update.
May 2007
Order Number: D88103-001US
Revision History
Revision Revision History Date
-001 First release of the Intel® Desktop Board DP35DP Technical Product
Specification.
This product specification applies to only the standard Intel® Desktop Board DP35DP with BIOS
identifier DPP3510J.86A.
Changes to this specification will be published in the Intel Desktop Board DP35DP Specification
Update before being incorporated into a revision of this document.
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May 2007
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved”
or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to them.
®
desktop boards may contain design defects or errors known as errata, which may cause the product
Intel
to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your
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Copies of documents which have an ordering number and are referenced in this document, or other Intel
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This Technical Product Specification (TPS) specifies the board layout, components,
connectors, power and environmental requirements, and the BIOS for the Intel
Desktop Board DP35DP. It describes the standard product and available
manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the Desktop Board
DP35DP and its components to the vendors, system integrators, and other engineers
and technicians who need this level of information. It is specifically not intended for
general audiences.
What This Document Contains
®
Chapter Description
1 A description of the hardware used on the board
2 A map of the resources of the board
3 The features supported by the BIOS Setup program
4 A description of the BIOS error messages, beep codes, and POST
codes
5 Regulatory compliance and battery disposal information
Typographical Conventions
This section contains information about the conventions used in this specification. Not
all of these symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
Notes call attention to important information.
INTEGRATOR’S NOTES
#
Integrator’s notes are used to call attention to information that may be useful to
system integrators.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
# Used after a signal name to identify an active-low signal (such as USBP0#)
GB Gigabyte (1,073,741,824 bytes)
GB/sec Gigabytes per second
Gbit Gigabit (1,073,741,824 bits)
KB Kilobyte (1024 bytes)
Kbit Kilobit (1024 bits)
kbits/sec 1000 bits per second
MB Megabyte (1,048,576 bytes)
MB/sec Megabytes per second
Mbit Megabit (1,048,576 bits)
Mbit/sec Megabits per second
xxh An address or data value ending with a lowercase h indicates a hexadecimal value.
x.x V Volts. Voltages are DC unless otherwise specified.
* This symbol is used to indicate third-party brands and names that are the property of their
Audio 8-channel (7.1) audio subsystem using the IDT* STAC9271D audio codec and
Video Video support provided via PCI Express* graphics via add-in card.
Legacy I/O Control Legacy I/O controller for serial port and Consumer Infrared (CIR)
Peripheral
Interfaces
LAN Support Gigabit (10/100/1000 Mbits/sec) LAN subsystem using the Intel
BIOS
®
• Intel
Core™2 Quad processor in an LGA775 socket with a 1066 MHz
system bus
®
• Intel
Core™2 Duo processor in an LGA775 socket with a 1066 or 800 MHz
system bus
®
• Intel
Pentium® Dual-Core processor in an LGA775 socket with an 800 MHz
system bus
®
• Intel
Celeron® processor in an LGA775 socket with an 800 MHz system bus
Figure 1 shows the location of the major components.
Figure 1. Major Board Components
Table 2 lists the components identified in Figure 1.
12
Table 2. Board Components Shown in Figure 1
Item/callout
from
Figure 1 Description
A PCI Conventional bus add-in card connector
B Auxiliary rear chassis fan header
C PCI Express x1 connector
D PCI Express x1 connector
E High Definition Audio Link header
F PCI Conventional bus add-in card connector
G Front panel audio header
H PCI Conventional bus add-in card connector
I PCI Express x1 connector
J Speaker
K PCI Express x16 connector
L Back panel connectors
M Processor core power connector (2 X 2)
N Back panel CIR emitter (output) header
O Rear chassis fan connector
P LGA775 processor socket
Q Intel 82P35 MCH
R Processor fan header
S DIMM Channel A sockets
T Serial port header
U DIMM Channel B sockets
V Front panel CIR receiver (input) header
W Main Power connector (2 X 12)
X Chassis intrusion header
Y Battery
Z Front chassis fan header
AA Intel 82801IR I/O Controller Hub (ICH9R)
BB BIOS Setup configuration jumper block
CC Auxiliary front panel power LED header
DD Front panel header
EE Serial ATA connectors [5]
FF Parallel ATA IDE connector
GG Front panel USB headers [3]
HH External Serial ATA (eSATA) connector
Figure 2 is a block diagram of the major functional areas.
14
Figure 2. Block Diagram
Product Description
1.2 Legacy Considerations
This board differs from other Intel Desktop Board products, with specific changes
including (but not limited to) the following:
• No parallel port
• The location of the floppy drive connector has moved
• No serial port on the back panel
• The serial port header is located between the memory sockets and may require a
specialized chassis or cabling solution to use
1.3 Online Support
To find information about… Visit this World Wide Web site:
Intel® Desktop Board DP35DP http://www.intel.com/products/motherboard/DP35DP/index.htm
Desktop Board Support http://support.intel.com/support/motherboards/desktop
Available configurations for the
Desktop Board DP35DP
Supported processors http://www.intel.com/go/findcpu
Chipset information http://www.intel.com/products/desktop/chipsets/index.htm
BIOS and driver updates http://downloadcenter.intel.com
The board is designed to support the following processors:
• Intel Core 2 Quad processor in an LGA775 socket with a 1066 MHz system bus
• Intel Core 2 Duo processor in an LGA775 socket with a 1066 or 800 MHz
system bus
•Intel Pentium Dual-Core processor in an LGA775 socket with an 800 MHz
system bus
•Intel Celeron processor in an LGA775 socket with an 800 MHz system bus
Other processors may be supported in the future. This board is designed to support
processors with a maximum wattage of 105 W. The processors listed above are only
supported when falling within the wattage requirements of the DP35DP board. See
the Intel web site listed below for the most up-to-date list of supported processors.
The board has four DIMM sockets and support the following memory features:
• 1.8 V (only) DDR2 SDRAM DIMMs with gold-plated contacts
• Unbuffered, single-sided or double-sided DIMMs with the following restriction:
Double-sided DIMMS with x16 organization are not supported.
•8 GB maximum total system memory using DDR2 800 or DDR2 667 DIMMs; refer
to Section
2.1.1 on page 37 for information on the total amount of addressable
memory.
• Minimum total system memory: 256 MB
• Non-ECC DIMMs
• Serial Presence Detect
• DDR2 800 or DDR2 667 MHz SDRAM DIMMs
• DDR2 667 DIMMs with SPD timings of only 5-5-5 (tCL-tRCD-tRP)
• DDR2 800 DIMMs with SPD timings of only 5-5-5 or 6-6-6 (tCL-tRCD-tRP)
NOTE
To be fully compliant with all applicable DDR SDRAM memory specifications, the board
should be populated with DIMMs that support the Serial Presence Detect (SPD) data
structure. This allows the BIOS to read the SPD data and program the chipset to
accurately configure memory settings for optimum performance. If non-SPD memory
is installed, the BIOS will attempt to correctly configure the memory settings, but
performance and reliability may be impacted or the DIMMs may not function under the
determined frequency.
The Intel 82P35 MCH supports the following types of memory organization:
•Dual channel (Interleaved) mode. This mode offers the highest throughput for
real world applications. Dual channel mode is enabled when the installed memory
capacities of both DIMM channels are equal. Technology and device width can vary
from one channel to the other but the installed memory capacity for each channel
must be equal. If different speed DIMMs are used between channels, the slowest
memory timing will be used.
•Single channel (Asymmetric) mode. This mode is equivalent to single channel
bandwidth operation for real world applications. This mode is used when only a
single DIMM is installed or the memory capacities are unequal. Technology and
device width can vary from one channel to the other. If different speed DIMMs are
used between channels, the slowest memory timing will be used.
•Flex mode. This mode provides the most flexible performance characteristics.
The bottommost DRAM memory (the memory that is lowest within the system
memory map) is mapped to dual channel operation; the topmost DRAM memory
(the memory that is nearest to the 8 GB address space limit), if any, is mapped to
single channel operation. Flex mode results in multiple zones of dual and single
channel operation across the whole of DRAM memory. To use flex mode, it is
necessary to populate both channels.
Figure 3 illustrates the memory channel and DIMM configuration.
NOTE
The DIMM 0 sockets of both channels are blue. The DIMM 1 sockets of both channels
are black.
Figure 3. Memory Channel and DIMM Configuration
INTEGRATOR’S NOTE
#
Regardless of the memory configuration used (dual channel, single channel, or flex
mode), DIMM 0 of Channel A must always be populated. This is a requirement of the
Intel Management Engine in ICH9R.
18
Product Description
1.6 Intel® P35 Express Chipset
The Intel P35 Express chipset consists of the following devices:
• Intel 82P35 Memory Controller Hub (MCH)
• Intel 82801IR I/O Controller Hub (ICH9R)
The MCH component provides interfaces to the CPU, memory, and PCI Express. The
ICH9R is a centralized controller for the board’s I/O paths.
For information about Refer to
The Intel P35 Express chipset http://www.intel.com/products/desktop/chipsets/index.htm
Resources used by the chipset Chapter 2
The chipset supports the following features:
• USB
• Serial ATA
• Parallel IDE
1.6.1Intel® Viiv™ Processor Technology
This Intel desktop board supports Intel® Viiv™ processor technology. To be eligible for
the Intel Viiv processor technology brand, a system must meet certain hardware and
software requirements. To get the list of requirements for Intel Viiv processor
technology branding as well as all the features supported by Intel Viiv processor
technology, refer to
http://www.intel.com/products/viiv/index.htm
1.6.2 USB
The board supports up to 12 USB 2.0 ports, supports UHCI and EHCI, and uses UHCIand EHCI-compatible drivers.
The ICH9R provides the USB controller for all ports. The port arrangement is as
follows:
• Six ports are implemented with stacked back panel connectors
• Six ports are routed to three separate front panel USB headers
For information about Refer to
The location of the USB connectors on the back panel Figure 9, page 41
The location of the front panel USB headers Figure 10, page 42
The board provides five Serial ATA (SATA) connectors, which support one device per
connector. The board also provides one red-colored external Serial ATA (eSATA)
connector.
1.6.3.1 Serial ATA Support
The DP35DP Desktop Board’s Serial ATA controller offers six independent Serial ATA
ports with a theoretical maximum transfer rate of 3 Gbits/sec per port. One device
can be installed on each port for a maximum of six Serial ATA devices. A point-topoint interface is used for host to device connections, unlike Parallel ATA IDE which
supports a master/slave configuration and two devices per channel.
For compatibility, the underlying Serial ATA functionality is transparent to the
operating system. The Serial ATA controller can operate in both legacy and native
modes. In legacy mode, standard IDE I/O and IRQ resources are assigned (IRQ 14
and 15). In Native mode, standard PCI Conventional bus resource steering is used.
Native mode is the preferred mode for configurations using the Windows* XP and
Windows Vista operating systems.
NOTE
Many Serial ATA drives use new low-voltage power connectors and require adapters or
power supplies equipped with low-voltage power connectors.
For more information, see:
For information about Refer to
The location of the Serial ATA connectors Figure 10, page 42
http://www.serialata.org/
1.6.3.2 Serial ATA RAID
The DP35DP Desktop Board supports the following RAID (Redundant Array of
Independent Drives) levels:
• RAID 0 - data striping
• RAID 1 - data mirroring
• RAID 0+1 (or RAID 10) - data striping and mirroring
• RAID 5 - distributed parity
20
Product Description
1.7 Parallel IDE Controller
The Parallel ATA IDE controller has one bus-mastering Parallel ATA IDE interface. The
Parallel ATA IDE interface supports the following modes:
• Programmed I/O (PIO): processor controls data transfer.
• 8237-style DMA: DMA offloads the processor, supporting transfer rates of up to
16 MB/sec.
•Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and
transfer rates of up to 33 MB/sec.
•ATA-66: DMA protocol on IDE bus supporting host and target throttling and
transfer rates of up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is
device driver compatible.
•ATA-100: DMA protocol on IDE bus allows host and target throttling. The ATA-100
logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up
to 88 MB/sec.
•ATA-133: DMA protocol on IDE bus allows host and target throttling. The ATA-133
logic is designed to achieve read transfer rates up to 133 MB/sec and write transfer
rates in excess of 100 MB/sec.
NOTE
ATA-66, ATA-100, and ATA-133 are faster timings and require a specialized cable to
reduce reflections, noise, and inductive coupling.
The Parallel ATA IDE interface also supports ATAPI devices (such as CD-ROM drives)
and ATA devices. The BIOS supports Logical Block Addressing (LBA) and Extended
Cylinder Head Sector (ECHS) translation modes. The drive reports the transfer rate
and translation mode to the BIOS.
For information about Refer to
The location of the Parallel ATA IDE connector Figure 10, page 42
1.8 Real-Time Clock Subsystem
A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When
the computer is not plugged into a wall socket, the battery has an estimated life of
three years. When the computer is plugged in, the standby current from the power
supply extends the life of the battery. The clock is accurate to ± 13 minutes/year at
25 ºC with 3.3 VSB applied.
NOTE
If the battery and AC power fail, custom defaults, if previously saved, will be loaded
into CMOS RAM at power-on.
When the voltage drops below a certain level, the BIOS Setup program settings stored
in CMOS RAM (for example, the date and time) might not be accurate. Replace the
battery with an equivalent one.
Figure 1 on page 12 shows the location of the battery.
The I/O controller provides the following features:
• Consumer Infrared (CIR) headers
• One serial port header
• Serial IRQ interface compatible with serialized IRQ support for PCI systems
• PS/2-style mouse and keyboard interfaces
• Intelligent power management, including a programmable wake-up event interface
• PCI power management support
The BIOS Setup program provides configuration options for the I/O controller.
1.9.1 Consumer Infrared (CIR)
The Consumer Infrared (CIR) feature is designed to comply with Microsoft Consumer
Infrared usage models. Microsoft Windows Vista is the supported operating system.
The CIR feature is made up of two separate pieces: the receiving (receiver) header,
and the output (emitter) header. The receiving header consists of a filtered translated
infrared input compliant with Microsoft CIR specifications, and also a “learning”
infrared input. This learning input is simply a high pass input which the computer can
use to “learn” to speak the infrared communication language of other user remotes.
The emitter header consists of two output ports which the PC can use to emulate
“learned” infrared commands in order to control external electronic hardware.
Customers are required to buy or create their own interface modules to plug into Intel
Desktop Boards for this feature to work. These interface modules may be included in
some boxed versions of DP35DP boards.
1.9.2 Serial Port
The board has one serial port header located on the component side of the board. The
serial port supports data transfers at speeds up to 115.2 kbits/sec with BIOS support.
For information about Refer to
The location of the serial port header Figure 10, page 42
The signal names of the serial port header Table 14, page 44
22
Product Description
1.10 Audio Subsystem
The onboard audio subsystem consists of the following:
• Intel 82801IR (ICH9R)
• IDT STAC9271 audio codec
• Back panel audio connectors
• Component-side audio headers:
⎯ Intel
⎯ HD audio link header
The audio subsystem supports the following features:
• Dolby Home Theater support
• A signal-to-noise (S/N) ratio of 95 dB
• Independent multi-streaming 7.1 audio (using the back panel audio connectors)
and stereo (using the Intel High Definition Audio front panel header)
•ADAT support from the back panel optical S/PDIF port
NOTE
Systems built with AC 97 front panel will not be able to obtain the Microsoft Windows
Vista* logo after June 2007.
®
High Definition Audio front panel header
Table 4 lists the supported functions of the front panel and back panel audio jacks.
Table 4. Audio Jack Retasking Support
Audio Jack
Front panel – Green No Yes No Yes
Front panel – Pink No No Yes No
Back panel – Blue Yes Yes No No
Back panel – Green No Yes No Yes
Back panel – Pink No No Yes No
Back panel – Black No Yes No No
Back panel - Orange No Yes No No
Supports
Line in?
Supports
Line out?
Supports
Microphone?
Headphones?
1.10.1 Audio Subsystem Software
Audio software and drivers are available from Intel’s World Wide Web site.
The board contains audio connectors on the back panel and audio headers on the
component side of the board. The front panel audio header provides mic in and line
out signals for the front panel. Microphone bias is supported for both the front and
back panel microphone connectors.
The front/back panel audio connectors are configurable through the audio device
drivers. The available configurable audio ports are shown in
Figure 4.
Item Description
A Surround left/right channel audio out/Retasking Jack
B Center channel and LFE (subwoofer) audio out
C Line in
D Line out
E Mic in
F S/PDIF Digital Audio Out (Optical)
Figure 4. Back Panel Audio Connector Options
For information about Refer to
The location of the front panel audio header Figure 10, page 42
The signal names of the front panel audio header Table 12, page 44
The location of the HD Audio Link header Figure 10, page 42
The signal names of the HD Audio Link header Table 11, on page 44
The back panel audio connectors Section 2.2.1, page 41
LAN software and drivers are available from Intel’s World Wide Web site.
For information about Refer to
Obtaining LAN software and drivers Section
1.2, page 15
1.11.3 RJ-45 LAN Connector with Integrated LEDs
Two LEDs are built into the RJ-45 LAN connector (shown in Figure 5 below).
Item Description
A Link LED (Green)
B Data Rate LED (Green/Yellow)
Figure 5. LAN Connector LED Locations
Table 5 describes the LED states when the board is powered up and the LAN
subsystem is operating.
Table 5. LAN Connector LED States
LED LED Color LED State Condition
Off LAN link is not established.
Link Green
Data Rate Green/Yellow
On LAN link is established.
Blinking LAN activity is occurring.
Off 10 Mbits/sec data rate is selected.
Green 100 Mbits/sec data rate is selected.
Yellow 1000 Mbits/sec data rate is selected.
26
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