The Intel® Desktop Boards D845HV/D845WN may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current
characterized errata are documented in the Intel Desktop Board D845HV/D845WN Specification Update.
August 2001
Order Number: A65136-001
Page 2
Revision History
Revision Revision History Date
-001 First release of the Intel® Desktop Board D845HV/D845WN Technical
Product Specification.
This product specification applies to only standard D845HV and D845WN boards with BIOS
identifier HV84510A.86A.
Changes to this specification will be published in the Intel Desktop Board D845HV/D845WN
Specification Update before being incorporated into a revision of this document.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS
PROVIDED IN INTEL’S TERM S AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTE L ASSUMES NO LIABILITY
WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE
OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRA NT IES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANT ABILITY, OR INFRINGEMENT OF ANY PA T ENT, COPYRIGHT, OR OTHE R INTELLECTUAL
PROPERTY RIGHT.
Intel Corporation may have patents or pending patent applicati ons , trademarks, copyri ghts, or other intellect ual property
rights that relate to t he pres ented subject matter. The f urni shing of documents and other materials and information does
not provide any license, express or implied, by es toppel or otherwise, to any s uch patents, trademarks , copyrights, or other
intellectual property rights.
Intel products are not int ended f or use in medical, life s aving, or life sustai ni ng appl i cations or for any other application in
which the failure of the Intel product could create a si tuation where personal injury or death may occur.
Intel may make changes t o specifications, product descriptions, and plans at any time, wi thout notice.
The Intel
product to deviate from publi shed specifications. Current characterized errat a are available on request.
Contact your local Int el sales office or your dis tributor to obtain the lates t specifications before placing your product order.
Copies of documents whic h hav e an orderi ng number and are referenced in this document , or other Intel literature, m ay be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
Intel and Pentium are trademark s or registered trademarks of Intel Corporation or its subsidiaries in the United St ates and
other countries.
†
Copyright 2001, Intel Corporation. All rights reserved.
®
Desktop Boards D845HV and D845WN may contain design defects or errors known as errata that may cause the
Other names and brands may be claim ed as the property of others.
August 2001
Page 3
Preface
This Technical Product Specification (TPS) specifies the board layout, components, connectors,
®
power and environmental requirements, and the BIOS for these Intel
and D845WN. It describes the standard product and available manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the D845HV and D845WN
boards and their components to the vendors, system integrators, and other engineers and
technicians who need this level of information. It is specifically not intended for general
audiences.
What This Document Contains
Desktop Boards: D845HV
Chapter Description
1 A description of the hardware used on the D845HV and D845WN boards
2 A map of the resources of the boards
3 The features supported by the BIOS Setup program
4 The contents of the BIOS Setup program’s menus and submenus
5 A description of the BIOS error messages, beep codes, and POST codes
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these
symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
✏
Notes call attention to important information.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
WARNING
Warnings indicate conditions, which if not observed, can cause personal injury.
# Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX) When used in the description of a component, N indicates component type, xn are the relative
coordinates of its location on the D845HV and D845WN boards, and X is the instance of the
particular part at that general location. For example, J5J1 is a connector, located at 5J. It is
the first connector in the 5J area.
GB Gigabyte (1,073,741,824 bytes)
GB/sec Gigabytes per second
KB Kilobyte (1024 bytes)
Kbit Kilobit (1024 bits)
kbits/sec 1000 bits per second
MB Megabyte (1,048,576 bytes)
MB/sec Megabytes per second
Mbit Megabit (1,048,576 bits)
Mbit/sec Megabits per second
xxh An address or data value ending with a lowercase h indicates a hexadecimal value.
x.x V Volts. Voltages are DC unless otherwise specified.
†
This symbol is used to indicate third-party brands and names that are the property of their
1.14 Power Management ...................................................................................................37
1.1 Board Differences
This TPS describes these Intel® Desktop boards: D845HV and D845WN. The boards are identical
with the exception of the items listed below. Table 1 summarizes the differences between these
boards.
Table 1. Summary of Board Differences
D845HV
D845WN
NOTE
✏
Most of the illustrations in this document show only the D845HV board. When there are
significant differences between the two boards, illustrations of both boards are provided.
• microATX Form Factor (9.60 inches by 9.60 inches)
• Three PCI bus connectors
Refer also to Table 3, page 13 for a list of manufacturing options specific to D845HV
board only
Table 2 summarizes the D845HV and D845WN boards’ major features.
Table 2. Feature Summary
Form Factor
Processor
Memory
(Refer also to
Table 3, page 13)
Chipset
Video
I/O Control
(Refer also to
Table 3, page 13)
Peripheral
Interfaces
(Refer also to
Table 3, page 13)
Expansion
Capabilities
BIOS
D845HV: microATX (9.60 inches by 9.60 inches)
D845WN: ATX (12.00 inches by 9.60 inches)
• Support for an Intel
• 400 MHz system bus
• Three 168-pin SDRAM Dual Inline Memory Module (DIMM) sockets
• Support for single-sided or double-sided DIMMs (PC133 only)
• Support for up to 3 GB system memory
NOTE:
The D845HV/D845WN boards have been designed to support DIMMs
®
Pentium® 4 processor in an mPGA478 socket
based on 512 Mbit technology for a maximum onboard capacity of up to 3
GB, but this technology has not been validated on this board. Please refer
to the following Intel web sites. For the D845HV board:
AGP connector supporting 1.5 V 4X AGP cards
SMSC LPC47M142 LPC Bus I/O controller
• Up to seven Universal Serial Bus (USB) ports
• Two serial ports
• One parallel port
• IrDA
• Two IDE interfaces with UDMA 33, ATA-66/100 support
• One diskette drive interface
• PS/2
• Three fan connectors
• D845HV: Three PCI bus add-in card connectors (SMBus routed to PCI bus
• D845WN: Six PCI bus add-in card connectors (SMBus routed to PCI bus
• Intel/AMI BIOS (resident in the Intel 82802AB 4 Mbit FWH)
• Support for Advanced Configuration and Power Interface (ACPI), Plug and Play,
82845 Memory Controller Hub (MCH)
®
82801BA I/O Controller Hub (ICH2)
®
82802AB 4 Mbit Firmware Hub (FWH)
†
-compliant infrared port
†
keyboard and mouse ports
connector 1)
connector 1)
and SMBIOS
continued
12
Page 13
Table 2. Feature Summary (continued)
Instantly Available
PC Technology
• Support for PCI Local Bus Specification Revision 2.2
• Suspend to RAM support
• Wake on PCI, CNR, RS-232, front panel, PS/2 devices, and USB ports
For information about Refer to
The board’s compliance level with ACPI, Plug and Play, and SMBIOS. Section 1.4, page 17
1.2.2 Manufacturing Options
Table 3 describes the D845HV and D845WN boards’ manufacturing options. Not every
manufacturing option is available in all marketing channels. Please contact your Intel
representative to determine which manufacturing options are available to you.
Table 3. Manufacturing Options
Audio
CNR
LAN
Hardware Monitor
Subsystem
The items listed below are component changes for an alternate configuration of the D845HV board
• Delete the auxiliary front panel power/sleep/message-waiting LED connector (shown on page 68)
• Delete the front chassis fan connector (shown on page 58)
• Delete the Mic-in pre-amp for boards equipped with the audio subsystem (described on page 32)
• Delete the SCSI hard drive activity LED connector (shown on pages 61 and 62)
• Delete the serial port B connector (shown on page 68)
• Delete the standby power indicator LED (shown on page 44)
• Delete the third DIMM socket (shown on pages 14 and 15)
• Delete the two USB connectors adjacent to the PS/2 connectors on the back panel (shown on page 52)
• Delete the 47 Ω inductive speaker (described on page 126)
• Replace I/O controller with SMSC LPC47M132 LPC bus I/O controller (functionally equivalent to SMSC
LPC47M142 LPC bus I/O controller but without an integrated USB hub) (described on page 31)
Audio subsyst em for AC 97 processing usi ng the Analog Devices AD1885 codec
One Communication and Networking Riser (CNR) connector (slot shared with
PCI bus connector 3 on the D845HV board and with PCI bus connector 6 on the
D845WN board)
®
Intel
82562ET 10/100 Mbit/sec Platform LAN Connect (PLC) device
• Voltage sense to detect out of range power supply voltages
• Thermal sense to detect out of range thermal values
• Two fan sense inputs used to monitor fan activity
Product Description
For information about Refer to
Available configurations of the D845HV and D845WN boards Section 1.3, page 17
NOTE
✏
The LAN and the CNR manufacturing options are mutually exclusive.
Figure 1 shows the location of the major components on the D845HV board.
CA
B
D
S
R
Q
P
O
N
A Audio codec (optional) K Diskette drive connector
B Intel 82562ET PLC Device (optional) L IDE connectors
C AGP connector M Speaker (optional)
D Back panel connectors N Intel 82801BA I/O Controller Hub (ICH2)
E +12V power connector (ATX12V) O Intel 82802AB 4 Mbit Firmware Hub (FWH)
F Intel 82845 Memory Controller Hub (MCH) P Front panel connector
G mPGA478 processor socket Q Battery
H DIMM sockets R PCI bus add-in card connectors
I I/O Controller S CNR connector (optional)
J Power Connector
L
J
KM
OM11427
E
F
G
H
I
14
Figure 1. D845HV Board Components
Page 15
Figure 2 shows the location of the major components on the D845WN board.
Product Description
CA
B
D
S
R
Q
P
O
N
A Audio codec (optional) K Diskette drive connector
B Intel 82562ET PLC Device (optional) L IDE connectors
C AGP connector M Speaker (optional)
D Back panel connectors N Intel 82801BA I/O Controller Hub (ICH2)
E +12V power connector (ATX12V) O Intel 82802AB 4 Mbit Firmware Hub (FWH)
F Intel 82845 Memory Controller Hub (MCH) P Front panel connector
G mPGA478 processor socket Q Battery
H DIMM sockets R PCI bus add-in card connectors
I I/O Controller S CNR connector (optional)
J Power Connector
Table 4 lists the specifications applicable to the D845HV and D845WN boards.
Table 4. Specifications
Reference
Name
AC ’97
ACPI
AGP
AMI BIOS
ATA/
ATAPI-5
ATX
ATX12V
CNR
Specification
Title
Audio Codec ’97
Advanced Configuration
and Power Interface
Specification
Accelerated Graphics Port
Interface Specification
American Megatrends
BIOS Specification
Information Technology-AT
Attachment with Packet
Interface - 5
(
ATA/ATAPI-5)
ATX Specification
ATX / ATX12V Power
Supply Design Guide
Communication and
Network Riser (CNR)
Specification
Version, Revision Date,
and Ownership
Revision 2.2,
September 2000,
Intel Corporation.
Version 2.0,
July 27, 2000,
Compaq Computer
Corporation,
Intel Corporation,
Microsoft Corporation,
Phoenix Technologies
Limited, and
Toshiba Corporation.
Revision 2.0,
May 4, 1998,
Intel Corporation.
AMIBIOS 99,
1999,
American Megatrends, Inc.
Revision 3,
February 29, 2000,
Contact: T13 Chair,
Seagate Technology.
Version 2.03,
December 1998,
Intel Corporation.
Version 1.1,
August 2000,
Intel Corporation.
Revision 1.1,
October 18, 2000,
Intel Corporation.
Version 2.3.1,
March 16, 1999,
American Megatrends
Incorporated,
Award Software International
Incorporated,
Compaq Computer Corporation,
Dell Computer Corporation,
Hewlett-Packard Company,
Intel Corporation,
International Business Machines
Corporation,
Phoenix Technologies Limited,
and SystemSoft Corporation.
Revision 1.1,
March 1996,
Intel Corporation.
Version 1.1,
September 23, 1998,
Compaq Computer Corporation,
Intel Corporation,
Microsoft Corporation, and
NEC Corporation.
Version 2.0,
December 18, 1998,
Intel Corporation.
Use only the processors listed below. Use of unsupported processors can damage the board, the
®
processor, and the power supply. See the Intel
Update for the most up-to-date list of supported processors for these boards.
The D845HV and D845WN boards support a single Pentium 4 processor (in an mPGA478 socket)
with a system bus of 400 MHz. The D845HV and D845WN boards support the processors listed
in Table 5. All supported onboard memory can be cached, up to the cachability limit of the
processor. See the processor’s data sheet for cachability limits.
Table 5. Supported Processors
Type Designation System Bus L2 Cache Size
Pentium 4 processor 1.4, 1.5, 1.6, 1.7, 1.8,
1.9, and 2.0 GHz
Desktop Board D845HV/D845WN Specification
400 MHz 256 KB
NOTE
✏
Use only ATX12V- or SFX12V-compliant power supplies with the D845HV and D845WN boards.
ATX12V and SFX12V power supplies have an additional power lead that provides required
supplemental power for the Intel Pentium
4
processor. Always connect the 20-pin and 4-pin leads
of ATX12V and SFX12V power supplies to the corresponding connectors on the D845HV and
D845WN boards, otherwise the board will not boot.
Do not use a standard ATX power supply. The board will not boot with a standard ATX power
supply.
For information about Refer to
Processor support Section 1.3, page 17
Processor usage Section 1.3, page 17
Power supply connectors Section 2.8.2.3, page 58
Before installing or removing memory, make sure that AC power is disconnected by unplugging
the power cord from the computer. Failure to do so could damage the memory and the board.
NOTE
✏
Remove the AGP video card before installing or upgrading memory to avoid interference with the
memory retention mechanism.
NOTE
✏
The D845HV/D845WN boards have been designed to support DIMMs based on 512 Mbit
technology for a maximum onboard capacity of up to 3 GB, but this technology has not been
validated on this board. Please refer to the following Intel web sites for the latest lists of tested
memory.
For the D845HV board:
To be fully compliant with all applicable Intel® SDRAM memory specifications, the board should
be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. This
allows the BIOS to read the SPD data and program the chipset to accurately configure memory
settings for optimum performance. If non-SPD memory is installed, the BIOS will attempt to
correctly configure the memory settings, but performance and reliability may be impacted or the
DIMMs may not function under the determined frequency.
The D845HV and D845WN boards both have three DIMM sockets and support the following
memory features:
• 3.3 V (only) 168-pin SDRAM DIMMs with gold-plated contacts
• Unbuffered single-sided or double-sided DIMMs
• Maximum total system memory: 3 GB; minimum total system memory: 32 MB
• 133 MHz SDRAM DIMMs only
• Serial Presence Detect (SPD)
• Suspend to RAM
• Non-ECC and ECC DIMMs
NOTE
✏
For ECC functionality, all installed DIMMs must be ECC. If both ECC and non-ECC DIMMs are
used, ECC will not function.
22
Page 23
Product Description
For information about Refer to
Obtaining the
PC Serial Presence Detect (SPD) Specification
Section 1.5, page 18
Table 6 lists the supported DIMM configurations.
Table 6. Supported Memory Configurations
DIMM
Capacity
32 MB SS 64 Mbit 4 M x 16/empty 4
64 MB DS 64 Mbit 4 M x 16/4 M x 16 8
64 MB SS 64 Mbit 8 M x 8/empty 8
64 MB SS 128 Mbit 8 M x 16/empty 4
96 MB DS 64 Mbit 8 M x 8/4 M x 16 12
96 MB DS 128/64 Mbit 8 M x 16/4 M x 16 8
128 MB DS 64 Mbit 8 M x 8/8 M x 8 16
128 MB DS 128 Mbit 8 M x 16/8 M x 16 8
128 MB SS 128 Mbit 16 M x 8/empty 8
128 MB SS 256 Mbit 16 M x 16/empty 4
192 MB DS 128 Mbit 16 M x 8/8 M x 16 12
192 MB DS 128/64 Mbit 16 M x 8/8 M x 8 16
256 MB DS 128 Mbit 16 M x 8/16 M x 8 16
256 MB DS 256 Mbit 16 M x 16/16 M x 16 8
256 MB SS 256 Mbit 32 M x 8/empty 8
512 MB DS 256 Mbit 32 M x 8/32 M x 8 16
Notes:
1. If the number of SDRAM devices is greater than nine, the DIMM will be double sided.
2. Front side population/back s i de popul ation indicated for SDRAM dens i ty and SDRAM organization.
3. In the second column, “DS” refers to double-sided memory m odul es (containing two rows of SDRAM ) and “S S” refers
to single-sided memory modul es (containing one row of SDRAM).
Number of
Sides
SDRAM
Density
SDRAM Organization
Front-side/Back-side
Number of
SDRAM devices
(Notes 1 and 2)
(Notes 1 and 2)
(Note 1)
(Notes 1 and 2)
(Notes 1 and 2)
(Notes 1 and 2)
(Notes 1 and 2)
(Notes 1 and 2)
(Notes 1 and 2)
NOTE
✏
For D845HV boards with two DIMM sockets, the maximum total system memory is 2 GB.
The Intel 845 chipset consists of the following devices:
• Intel 82845 Memory Controller Hub (MCH) with Accelerated Hub Architecture (AHA) bus
• Intel 82801BA I/O Controller Hub (ICH2) with AHA bus
• Intel 82802AB Firmware Hub (FWH)
The MCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the
Accelerated Hub Architecture interface. The ICH2 is a centralized controller for the board’s I/O
paths. The FWH provides the nonvolatile storage of the BIOS. The component combination
provides the chipset interfaces as shown in Figure 4.
UDMA 33
ATA-66/100
System Bus
Network
USB
845 Chipset
82845
Memory Controller
Hub (MCH)
AGP
Interface
SDRAM
Bus
AHA
Bus
82801BA
I/O Controller Hub
(ICH2)
82802AB 4 Mbit
Firmware Hub
(FWH)
LPC Bus
AC LinkPCI BusSMBus
OM12275
Figure 4. Intel 845 Chipset Block Diagram
For information about Refer to
The Intel 845 chipset http://developer.intel.com
Resources used by the chipset Chapter 2
24
Page 25
Product Description
1.8.1 AGP
NOTE
✏
The AGP connector is keyed for 1.5 V AGP cards only. Do not attempt to install a legacy 3.3 V
AGP card. The AGP connector is not mechanically compatible with legacy 3.3 V AGP cards.
The AGP connector supports AGP add-in cards with 1.5 V Switching Voltage Level (SVL).
Legacy 3.3 V AGP cards are not supported.
For information about Refer to
The location of the AGP connector Figure 1, page 14
The signal names of the AGP connector Table 37, page 65
AGP is a high-performance interface for graphics-intensive applications, such as 3D applications.
While based on the PCI Local Bus Specification, Rev. 2.1, AGP is independent of the PCI bus and
is intended for exclusive use with graphical display devices. AGP overcomes certain limitations of
the PCI bus related to handling large amounts of graphics data with the following features:
• Pipelined memory read and write operations that hide memory access latency
• Demultiplexing of address and data on the bus for nearly 100 percent efficiency
For information about Refer to
Obtaining the
Accelerated Graphics Port Interface Specification
Section 1.5, page 18
1.8.2 USB
There are two USB configurations, depending on which I/O controller is used on the board, as
follows:
• The USB configuration for boards with the SMSC LPC47M142 I/O controller is described in
Section 1.8.2.1
• The USB configuration for boards with the SMSC LPC47M132 I/O controller is described in
Section 1.8.2.2
The D845HV and D845WN boards fully support UHCI and use UHCI-compatible software
drivers.
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device is attached to the cable. Use shielded cable that meets the
requirements for full-speed devices.
1.8.2.1 USB Configuration for Boards with the SMSC LPC47M142 I/O Controller
The D845HV/D845WN boards support up to seven USB ports, as shown in Figure 5. The ICH2
provides three external ports: two ports are implemented with stacked back panel connectors and
the other port is accessible through a CNR add-in card. The SMSC LPC47M142 I/O controller
provides four external ports: two ports implemented with stacked back panel connectors and two
ports routed to the front panel USB connector.
For more than seven USB devices, an external hub can be connected to any of the ports.
Back panel USB c onnectors
adjacent to the audio c onnectors
USB port accessible through a USB
connector on an optional CNR add-in card
Back panel USB c onnectors
adjacent to the PS/2 connectors
Front panel USB connector
OM12388
82801BA
I/O Controller Hub
(ICH2)
USB
SMSC LPC47M142
LPC Bus
I/O Controller
USB ports (2)
USB
CNR connector
USB ports (2)
USB
USB ports (2)
Figure 5. USB Port Configuration for Boards with the SMSC LPC47M142 I/O Controller
For information about Refer to
The location of the USB connectors on the back panel Figure 10, page 52
The signal names of the back panel USB connectors Table 19, page 53
The location of the front panel USB connector Figure 15, page 68
The signal names of the front panel USB connector Table 43, page 69
The USB specification and UHCI Section 1.5, page 18
1.8.2.2 USB Configuration for Boards with the SMSC LPC47M132 I/O Controller
D845HV boards equipped with the optional SMSC LPC47M132 I/O controller support up to four
USB ports, as shown in Figure 6. The ICH2 provides four external ports: two ports are
implemented with stacked back panel connectors and two are accessible through the front panel
USB connector.
For more than four USB devices, an external hub can be connected to any of the ports.
26
Page 27
Product Description
82801BA
I/O Controller Hub
(ICH2)
Figure 6. USB Port Configuration for Boards with the SMSC LPC47M132 I/O Controller
For information about Refer to
The location of the USB connectors on the back panel Figure 10, page 52
The signal names of the back panel USB connectors Table 19, page 53
The location of the front panel USB connector Figure 15, page 68
The signal names of the front panel USB connector Table 43, page 69
The USB specification and UHCI Section 1.5, page 18
USB
USB ports (2)
USB ports (2)Front panel USB connector
Back panel USB connectors
adjacent to the audio connectors
1.8.3 IDE Support
1.8.3.1 IDE Interfaces
The ICH2’s IDE controller has two independent bus-mastering IDE interfaces that can be
independently enabled. The IDE interfaces support the following modes:
• Programmed I/O (PIO): processor controls data transfer.
• 8237-style DMA: DMA offloads the processor, supporting transfer rates of up to 16 MB/sec.
• Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates
of up to 33 MB/sec.
• ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of
up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible.
• ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH2’s ATA-100
logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to
88 MB/sec.
OM12389
✏ NOTE
ATA-66 and ATA-100 are faster timings and require a specialized cable to reduce reflections,
noise, and inductive coupling.
The IDE interfaces also support ATAPI devices (such as CD-ROM drives) and ATA devices using
the transfer modes listed in Section 4.4.4.1 on page 105.
The BIOS supports Logical Block Addressing (LBA) and Extended Cylinder Head Sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
The D845HV and D845WN boards support Laser Servo (LS-120) diskette technology through the
IDE interfaces. An LS-120 drive can be configured as a boot device by setting the BIOS Setup
program’s Boot menu to one of the following:
• ARMD-FDD (ATAPI removable media device – floppy disk drive)
• ARMD-HDD (ATAPI removable media device – hard disk drive)
For information about Refer to
The location of the IDE connectors Figure 13, page 61
The signal names of the IDE connectors Table 39, page 67
BIOS Setup program’s Boot menu Table 75, page 113
1.8.3.2 SCSI Hard Drive Activity LED Connector (Optional)
The SCSI hard drive activity LED connector is a 1 x 2-pin connector that allows an add-in
SCSI controller to use the same LED as the onboard IDE controller. For proper operation, this
connector should be wired to the LED output of the add-in SCSI controller. The LED indicates
when data is being read from, or written to, both the add-in SCSI controller and the IDE controller.
For information about Refer to
The location of the SCSI hard drive activity LED connector Figure 13, page 61, or
Figure 14, page 62
The signal names of the SCSI hard drive activity LED connector Table 40, page 67
1.8.4 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock provides a time-of-day clock and a multicentury calendar with alarm features.
The real-time clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are
reserved for BIOS use.
A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the standby current from the power supply extends the life of the battery.
The clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
The time, date, and CMOS values can be specified in the BIOS Setup program. The CMOS values
can be returned to their defaults by using the BIOS Setup program.
✏ NOTE
If the battery and AC power fail, custom defaults, if previously saved, will be loaded into CMOS
RAM at power-on.
For information about Refer to
Proper date access in systems with D845HV and D845WN boards Section 1.3, page 17
28
Page 29
®
1.8.5 Intel
The FWH provides the following:
• System BIOS program
• Logic that enables protection for storing and updating of platform information
82802AB 4 Mbit Firmware Hub (FWH)
1.9 I/O Controller
The SMSC LPC47M142 I/O controller provides the following features:
• Two serial ports
• One parallel port with Extended Capabilities Port (ECP) and Enhanced Parallel Port
(EPP) support
• Serial IRQ interface compatible with serialized IRQ support for PCI systems
• PS/2-style mouse and keyboard interfaces
• Interface for one 1.2 MB or 1.44 MB diskette drive
• Intelligent power management, including a programmable wake-up event interface
• PCI power management support
• Two fan tachometer inputs
• Integrated USB hub
• IrDA compliant infrared port
Product Description
The BIOS Setup program provides configuration options for the I/O controller.
NOTE
✏
For the D845HV board only, there is a manufacturing option for an SMSC LPC47M132 I/O
controller. This optional I/O controller provides identical functionality to the standard I/O
controller, minus the integrated USB hub.
For information about Refer to
SMSC LPC47M142 I/O controller http://www.smsc.com
1.9.1 Serial Ports
The D845HV and D845WN boards have two serial port connectors. Serial port A is located on the
back panel. Serial port B is accessible using a connector located near the main power connector.
The serial ports’ NS16C550-compatible UART supports data transfers at speeds up to
115.2 kbits/sec with BIOS support. The serial ports can be assigned as COM1 (3F8h),
COM2 (2F8h), COM3 (3E8h), or COM4 (2E8h).
NOTE
✏
The operation of serial port B and the infrared port are mutually exclusive. When serial port B is
enabled in the BIOS Setup program, the IR option is disabled.
For the D845HV board only, there is a manufacturing option that omits the connector for Serial
port B.
For information about Refer to
The location of the serial port A connector Figure 10, page 52
The signal names of the serial port A connector Table 21, page 54
The location of the serial port B connector Figure 15, page 68
The signal names of the serial port B connector Table 42, page 69
1.9.2 Infrared Support
On the front panel connector, there are four pins that support devices compliant with the IrDA
Serial Infrared Physical Layer Specification, version 1.3. In the BIOS Setup program, infrared
support is disabled by default. The IR connection can be used to transfer files to or from portable
devices like laptops, PDAs, and printers. The Infrared Data Association (IrDA) specification
supports data transfers of up to 115.2 kbits/sec at a distance of 1 meter.
NOTE
✏
The infrared port operates in half duplex mode only.
NOTE
✏
The operation of the infrared port and serial port B are mutually exclusive. When the IR option is
enabled in the BIOS Setup program, serial port B is disabled.
For information about Refer to
The location of the front panel connector Figure 15, page 68
The signal names of the infrared port on the front panel connector Table 45, page 70
The IrDA specification Section 1.5, page 18
1.9.3 Parallel Port
The 25-pin D-Sub parallel port connector is located on the back panel. In the BIOS Setup
program, the parallel port can be set to the following modes:
†
• Output only (PC AT
• Bi-directional (PS/2 compatible)
• EPP
• ECP
For information about Refer to
The location of the parallel port connector Figure 10, page 52
The signal names of the parallel port connector Table 20, page 53
Setting the parallel port’s mode Table 66, page 102
-compatible mode)
30
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Product Description
1.9.4 Diskette Drive Controller
The I/O controller supports one diskette drive that is compatible with the 82077 diskette drive
controller and supports both PC-AT and PS/2 modes.
For information about Refer to
The location of the diskette drive connector Figure 13, page 61
The signal names of the diskette drive connector Table 38, page 66
The supported diskette drive capacities and sizes Table 69, page 107
1.9.5 Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel. The +5 V lines to these
†
connectors are protected with a PolySwitch
connection after an overcurrent condition is removed.
NOTE
✏
The keyboard is supported in the bottom PS/2 connector and the mouse is supported in the top
PS/2 connector. Power to the computer should be turned off before a keyboard or mouse is
connected or disconnected.
circuit that, like a self-healing fuse, reestablishes the
The keyboard controller contains the AMI keyboard and mouse controller code, provides the
keyboard and mouse control functions, and supports password protection for power-on/reset. A
power-on/reset password can be specified in the BIOS Setup program.
For information about Refer to
The location of the keyboard and mouse connectors Figure 10, page 52
The signal names of the keyboard and mouse connectors Table 18, page 53
1.9.6 I/O Controller Option
For the D845HV board only, there is a manufacturing option for an SMSC LPC47M132 I/O
controller. This optional I/O controller provides identical functionality to the standard I/O
controller, minus the integrated USB hub.
The optional audio subsystem includes these features:
• Split digital/analog architecture for improved S/N (signal-to-noise) ratio: ≥ 85 dB
• Power management support for ACPI 1.0 (driver dependant)
• 3-D stereo enhancement
• Mic in pre-amp that supports dynamic, condenser, and electret microphones
The audio subsystem supports the following audio interfaces:
• ATAPI-style connectors:
Telephony
Auxiliary line in
CD-ROM
• Front panel audio connector, including pins for:
Line out
Mic in
• Back panel audio connectors:
Line out
Line in
Mic in
The audio subsystem consists of the following devices:
• Intel 82801BA I/O Controller Hub (ICH2)
• Analog Devices AD1885 audio codec
Figure 7 is a block diagram of the audio subsystem.
82801BA
I/O Controller Hub
(ICH2)
Figure 7. Audio Subsystem Block Diagram
For information about Refer to
Upgrading the onboard audio subsystem using a CNR audio card Section 1.12, page 35
The front panel audio connector Section 2.8.3, page 68
The back panel audio connectors Section 2.8.1, page 52
AC ’97
Link
AD1885
Audio Codec
Line In
Line Out
Mic In
Auxiliary Line In
CD-ROM
Telephony
OM12276
32
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Product Description
1.10.1 Audio Connectors
1.10.1.1 Front Panel Audio Connector
A 2 x 5-pin connector provides Mic in and line out signals for front panel audio connectors.
For information about Refer to
The location of the connector Section 2.8.3, page 68
The signal names of the front panel audio connector Table 41, page 69
NOTE
✏
The front panel audio connector is alternately used as a jumper block for routing audio signals.
Refer to Section 2.9.1 on page 72 for more information.
1.10.1.2 Telephony Connector
A 1 x 4-pin ATAPI-style connector connects the monaural audio signals of an internal telephony
device to the audio subsystem. A monaural audio-in and audio-out signal interface is necessary for
telephony applications such as speakerphones, fax/modems, and answering machines.
For information about Refer to
The location of the telephony connector Figure 11, page 56
The signal names of the telephony connector Table 26, page 57
1.10.1.3 Auxiliary Line In Connector
A 1 x 4-pin ATAPI-style connector connects the left and right channel signals of an internal audio
device to the audio subsystem.
For information about Refer to
The location of the auxiliary line in connector Figure 11, page 56
The signal names of the auxiliary line in connector Table 27, page 57
1.10.1.4 ATAPI CD-ROM Audio Connector
A 1 x 4-pin ATAPI-style connector connects an internal ATAPI CD-ROM drive to the audio
mixer.
For information about Refer to
The location of the ATAPI CD-ROM connector Figure 11, page 56
The signal names of the ATAPI CD-ROM connector Table 28, page 57
1.10.2 Audio Subsystem Software
Audio software and drivers are available from Intel’s World Wide Web site.
For information about Refer to
Obtaining audio software and drivers Section 1.3, page 17
The Network Interface Controller subsystem consists of the ICH2 (with integrated LAN Media
Access Controller) and a physical layer interface device. Features of the LAN subsystem include:
• PCI Bus Master interface
• CSMA/CD Protocol Engine
• Serial CSMA/CD unit interface that supports the 82562ET (10/100 Mbit/sec Ethernet) on the
CNR bus
• PCI Power Management
Supports ACPI technology
Supports LAN wake capabilities
1.11.1 Intel® 82562ET Platform LAN Connect Device
The Intel 82562ET component provides an interface to the back panel RJ-45 connector with
integrated LEDs. This physical interface may alternately be provided through the CNR connector.
The Intel 82562ET provides the following functions:
• Basic 10/100 Ethernet LAN connectivity
• Supports RJ-45 connector with status indicator LEDs on the back panel
• Full device driver compatibility
• ACPI support
• Programmable transit threshold
• Configuration EEPROM that contains the MAC address
1.11.2 RJ-45 LAN Connector with Integrated LEDs
Two LEDs are built into the RJ-45 LAN connector. Table 7 describes the LED states when the
board is powered up and the LAN subsystem is operating.
Table 7. LAN Connector LED States
LED Color LED State Condition
Off 10 Mbit/sec data rate is selected. Green
On 100 Mbit/sec data rate is selected.
Yellow
Off LAN link is not established.
On (steady state) LAN link is established.
On (brighter and pulsing) The computer is communicating with another computer on
the LAN.
34
Page 35
1.11.3 LAN Subsystem Software
LAN software and drivers are available from Intel’s World Wide Web site.
For information about Refer to
Obtaining LAN software and drivers Section 1.3, page 17
1.12 CNR (Optional)
The CNR connector provides an interface that supports the audio, modem, USB, and LAN
interfaces of the Intel 845 chipset. Figure 8 shows the signal interface between the riser and
the ICH2.
Product Description
Intel 82801BA
I/O Controller Hub
(ICH2)
AC ’97 Interface
LAN Interface
SMBus
USB
Communicat i on and
Networking Riser
(Up to two AC ’97 codecs
and one LAN device)
CNR Connector
OM12277
Figure 8. ICH2 and CNR Signal Interface
The interfaces supported by the CNR include the following:
• AC ’97 interface: supports audio and/or modem functions on the CNR board.
• LAN interfaces: an eight-pin interface for use with Platform LAN Connection (PLC) based
devices.
• SMBus interface: provides Plug-and-Play functionality for the CNR board.
• USB interface: provides a USB interface for the CNR board.
The CNR connector includes power signals required for power management and for CNR board
operation. To learn more about the CNR, refer to the CNR specification.
The onboard two-channel audio subsystem can be upgraded to four- or six-channel audio using a
CNR audio upgrade card in a slave configuration. CNR audio upgrade cards are available in
multiple configurations from several different vendors supporting analog or S/P-DIF digital
connections. A list of vendors supplying CNR audio upgrade cards compatible with the
D845HV/D845WN boards’ onboard audio subsystem, as well as an installation guide for these
cards with SoundMAX with SPX are available on the following web site:
If you install a CNR card that cannot support a multichannel audio upgrade, the D845HV and
D845WN boards’ integrated audio codec will be disabled. This only applies to D845HV and
D845WN boards that have both the onboard audio subsystem and a CNR.
NOTE
✏
The brand and type of audio codec used on the CNR card must match that of the
Obtaining the CNR specification Section 1.5, page 18
1.13 Hardware Management Subsystem
The hardware management features enable the boards to be compatible with the Wired for
Management (WfM) specification. The board has several hardware management features,
including the following:
• Fan monitoring
• Thermal and voltage monitoring
• Chassis intrusion detection
For information about Refer to
The WfM specification Section 1.5, page 18
1.13.1 Hardware Monitor Component (Optional)
The hardware monitor component provides low-cost instrumentation capabilities. The features of
the component include:
• Internal ambient temperature sensing
• Remote thermal diode sensing for direct monitoring of processor temperature
• Power supply monitoring (+5 V, +3.3 V, +1.5 V, 3.3 VSB, Vccp) to detect levels above or
below acceptable values
• SMBus interface
1.13.2 Fan Monitoring
The SMSC LPC47M142 I/O controller provides two fan tachometer inputs. Monitoring can be
implemented using third-party software.
For information about Refer to
The functions of the fan connectors Section 1.14.2.2, page 42
The location of the fan connectors Figure 12, page 58
The signal names of the fan connectors Section 2.8.2.2, page 56
36
Page 37
Product Description
1.13.3 Chassis Intrusion and Detection
The boards support a chassis security feature that detects if the chassis cover is removed. For the
chassis intrusion circuit to function, the chassis’ power supply must be connected to AC power.
The security feature uses a mechanical switch on the chassis that attaches to the chassis intrusion
connector. The mechanical switch is closed for normal computer operation.
For information about Refer to
The location of the chassis intrusion connector Figure 12, page 58
The signal names of the chassis intrusion connector Table 33, page 60
NOTE
✏
Chassis intrusion detection may be implemented using third-party software.
1.14 Power Management
Power management is implemented at several levels, including:
• Software support through Advanced Configuration and Power Interface (ACPI)
• Hardware support:
Power connector
Fan connectors
LAN wake capabilities
Instantly Available PC technology
Resume on Ring
Wake from USB
Wake from PS/2 devices
Power Management Event (PME#) wake-up support
1.14.1 ACPI
ACPI gives the operating system direct control over the power management and Plug and Play
functions of a computer. The use of ACPI with the D845HV and D845WN boards requires an
operating system that provides full ACPI support. ACPI features include:
• Plug and Play (including bus and device enumeration)
• Power management control of individual devices, add-in boards (some add-in boards may
require an ACPI-aware driver), video displays, and hard disk drives
• Methods for achieving less than 15-watt system operation in the power-on/standby
sleeping state
• A Soft-off feature that enables the operating system to power-off the computer
• Support for multiple wake-up events (see Table 10 on page 40)
• Support for a front panel power and sleep mode switch.
Table 8 lists the system states based on how long the power switch is pressed, depending on how
ACPI is configured with an ACPI-aware operating system.
The D845HV and D845WN boards’ compliance level with ACPI Section 1.5, page 18
…the system enters this state
(ACPI G0 – working state)
(ACPI G1 – sleeping state)
(ACPI G2/G5 – Soft off)
(ACPI G0 – working state)
(ACPI G2/G5 – Soft off)
38
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Product Description
1.14.1.1 System States and Power States
Under ACPI, the operating system directs all system and device power state transitions. The
operating system puts devices in and out of low-power states based on user preferences and
knowledge of how devices are being used by applications. Devices that are not being used can be
turned off. The operating system uses information from applications and user settings to put the
system as a whole into a low-power state.
Table 9 lists the power states supported by the D845HV and D845WN boards along with the
associated system power targets. See the ACPI specification for a complete description of the
various system and power states.
Table 9. Power States and Targeted System Power
Global States Sleeping States
G0 – working
state
G1 – sleeping
state
G1 – sleeping
state
G1 – sleeping
state
G2/S5 S5 – Soft off.
G3 –
mechanical off
AC power is
disconnected
from the
computer.
Notes:
1. Total system power is dependent on the system configuration, including add-in boards and peripherals powered
by the system chassis’ power supply.
2. Dependent on the standby power consumpt i on of wake-up devices used in t he system.
S0 – working C0 – working D0 – working
S1 – Processor
stopped
S3 – Suspend to
RAM. Context
saved to RAM.
S4 – Suspend to
disk. Context
saved to di sk.
Context not saved.
Cold boot is
required.
No power to the
system.
Processor
States
C1 – stop
grant
No power D3 – no power
No power D3 – no power
No power D3 – no power
No power D3 – no power for
Device States
state.
D1, D2, D3 –
device
specification
specific.
except for
wake-up logic.
except for
wake-up logic.
except for
wake-up logic.
wake-up logic,
except when
provided by
battery or external
source.
Targeted System
(Note 1)
Power
Full power > 30 W
5 W < power < 52.5 W
Power < 5 W
Power < 5 W
Power < 5 W
No power to t he system so
that service can be
performed.
Table 10 lists the devices or specific events that can wake the computer from specific states.
Table 10. Wake-up Devices and Events
These devices/events can wake up the computer… …from this state
Power switch S1, S3, S4, S5
RTC alarm S1, S3, S4, S5
LAN S1, S3, S4, S5
CNR S1, S3 , S4
PME# S1, S3, S4, S5
Modem (back panel Serial Port A) S1, S3
USB S1, S3
PS/2 devices S1, S3
Notes:
1. For LAN and PME#, S5 is disabled by default in the BIOS Setup program. Sett ing this option to Power On will
enable a wake-up event from LAN in the S 5 state.
2. Except from the CNR’s USB interface.
(Note 1)
(Note 2)
, S5
(Note 2)
NOTE
✏
The use of these wake-up events from an ACPI state requires an operating system that provides full
ACPI support. In addition, software, drivers, and peripherals must fully support ACPI wake
events.
1.14.1.3 Plug and Play
In addition to power management, ACPI provides control information so that operating systems
can facilitate Plug and Play. ACPI is used only to configure devices that do not use other hardware
configuration standards. PCI devices for example, are not configured by ACPI.
40
Page 41
Product Description
1.14.2 Hardware Support
CAUTION
Ensure that the power supply provides adequate +5 V standby current if LAN wake capabilities
and Instantly Available PC technology features are used. Failure to do so can damage the power
supply. The total amount of standby current required depends on the wake devices supported and
manufacturing options. Refer to Section 2.11.3 on page 79 for additional information.
The D845HV and D845WN boards provide several power management hardware features,
including:
• Power connector
• Fan connectors
• LAN wake capabilities
• Instantly Available PC technology
• Resume on Ring
• Wake from USB
• Wake from PS/2 keyboard
• PME# wake-up support
LAN wake capabilities and Instantly Available PC technology require power from the +5 V
standby line. The sections discussing these features describe the incremental standby power
requirements for each.
Resume on Ring enables telephony devices to access the computer when it is in a power-managed
state. The method used depends on the type of telephony device (external or internal).
NOTE
✏
The use of Resume on Ring and Wake from USB technologies from an ACPI state requires an
operating system that provides full ACPI support.
1.14.2.1 Power Connector
When used with an ATX12V- or SFX12V-compliant power supply that supports remote power
on/off, the D845HV and D845WN boards can turn off the system power through software control.
When the system BIOS receives the correct command from the operating system, the BIOS turns
off power to the computer.
With soft-off enabled, if power to the computer is interrupted by a power outage or a disconnected
power cord, when power resumes, the computer returns to the power state it was in before power
was interrupted (on or off). The computer’s response can be set using the After Power Failure
feature in the BIOS Setup program’s Boot menu.
For information about Refer to
The location of the power connector Figure 12, page 58
The signal names of the power connector Table 32, page 60
The BIOS Setup program’s Boot menu Table 75, page 113
The ATX specification Section 1.5, page 18
Table 11 summarizes the function/operation of the fan connectors.
Table 11. Fan Connector Function/Operation
Connector Description
Processor fan • +12 V DC connection for a processor fan or active fan heatsink.
• Fan is on in the S0 or S1 state.
Fan is off when the system is off or in the S3, S4, or S5 st ate.
• Wired to a fan tachometer input of the SMSC LPC47M142 I/O controller.
Front chassis fan
(optional)
Rear chassis fan • +12 V DC connection for a system or chassis fan.
• +12 V DC connection for a system or chassis fan.
• Fan is on in the S0 or S1 state.
Fan is off when the system is off or in the S3, S4, or S5 st ate.
• Fan is on in the S0 or S1 state.
Fan is off when the system is off or in the S3, S4, or S5 st ate.
• Wired to a fan tachometer input of the SMSC LPC47M142 I/O controller.
For information about Refer to
The location of the fan connectors Figure 12, page 58
The signal names of the fan connectors Section 2.8.2.2, page 56
1.14.2.3 LAN Wake Capabilities
CAUTION
For LAN wake capabilities, the 5-V standby line for the power supply must be capable of providing
adequate +5 V standby current. Failure to provide adequate standby current when implementing
LAN wake capabilities can damage the power supply. Refer to Section 2.11.3 on page 79 for
additional information.
LAN wake capabilities enable remote wake-up of the computer through a network. The LAN
subsystem PCI bus network adapter monitors network traffic at the Media Independent Interface.
†
Upon detecting a Magic Packet
up the computer. Depending on the LAN implementation, the D845HV and D845WN boards
support LAN wake capabilities with ACPI in the following ways:
• the PCI bus PME# signal for PCI 2.2 compliant LAN designs
• the onboard LAN subsystem
• a CNR-based LAN subsystem
frame, the LAN subsystem asserts a wake-up signal that powers
42
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Product Description
1.14.2.4 Instantly Available PC Technology
CAUTION
For Instantly Available PC technology, the +5 V standby line for the power supply must be
capable of providing adequate +5 V standby current. Failure to provide adequate standby current
when implementing Instantly Available PC technology can damage the power supply. Refer to
Section 2.11.3 on page 79 for additional information.
Instantly Available PC technology enables the D845HV and D845WN boards to enter the ACPI S3
(Suspend-to-RAM) sleep-state. While in the S3 sleep-state, the computer will appear to be off (the
power supply is off, and the front panel LED is amber if dual colored, or off if single colored.)
When signaled by a wake-up device or event, the system quickly returns to its last known wake
state. Table 10 on page 40 lists the devices and events that can wake the computer from the
S3 state.
The D845HV and D845WN boards support the PCI Bus Power Management Interface Specification. For information on the versions of this specification, see Section 1.5. Add-in
boards that also support this specification can participate in power management and can be used to
wake the computer.
The use of Instantly Available PC technology requires operating system support and PCI 2.2
compliant add-in cards and drivers.
The optional standby power indicator LED shows that power is still present even when the
computer appears to be off. Figure 9 shows the location of the optional standby power
indicator LED.
CAUTION
If AC power has been switched off and the standby power indicator is still lit, disconnect the power
cord before installing or removing any devices connected to the board. Failure to do so could
damage the board and any attached devices.
Sections 2.2 - 2.6 contain several standalone tables. Table 12 describes the system memory map,
Table 13 shows the I/O map, Table 14 lists the DMA channels, Table 15 defines the PCI
configuration space map, and Table 16 describes the interrupts. The remaining sections in this
chapter are introduced by text found with their respective section headings.
2.2 Memory Map
Table 12. System Memory Map
Address Range (decimal) Address Range (hex) Size Description
1024 K - 3145728 K 100000 - BFFFFFFF 3071 MB Extended memory
960 K - 1024 K F0000 - FFFFF 64 KB Runtime BIOS
896 K - 960 K E0000 - EFFFF 64 KB Reserved
800 K - 896 K C8000 - DFFFF 96 KB Available high DOS memory (open
to the PCI bus)
640 K - 800 K A0000 - C7FFF 160 KB Video memory and BIOS
639 K - 640 K 9FC00 - 9FFFF 1 KB Extended BIOS data (movable by
memory manager software)
512 K - 639 K 80000 - 9FBFF 127 KB Extended conventional memory
0 K - 512 K 00000 - 7FFFF 512 KB Conventional memory
0 8 or 16 bits Open
1 8 or 16 bits Parallel port
2 8 or 16 bits Diskette drive
3 8 or 16-bits Parallel port (for ECP or EPP)
4 8 or 16 bits DMA controller
5 16 bits Open
6 16 bits Open
7 16 bits Open
2.5 PCI Configuration Space Map
Table 15. PCI Configuration Space Map
Bus
Number (hex)
00 00 00 Memory controller of Intel 82845 component
00 01 00 PCI to AGP bridge
00 1E 00 Hub link to PCI bridge
00 1F 00 Intel 82801BA ICH2 PCI to LPC bridge
00 1F 01 IDE controller
00 1F 02 USB
00 1F 03 SMBus controller
00 1F 04 USB
00 1F 05 AC ’97 audio controller (optional)
00 1F 06 AC ’97 modem controller (optional)
01 00 00 Add-in AGP adapter card
02 08 00 LAN controller (optional)
02 09 00 PCI bus connector 1
02 0A 00 PCI bus connector 2
02 0B 00 PCI bus connector 3
02 0C 00 PCI bus connector 4
02 0D 00 PCI bus connector 5
02 0E 00 PCI bus connector 6
Note: D845WN board only.
Device
Number (hex)
Function
Number (hex) Description
(Note)
(Note)
(Note)
48
Page 49
2.6 Interrupts
Table 16. Interrupts
IRQ System Resource
NMI I/O channel check
0 Reserved, interval timer
1 Reserved, keyboard buffer full
2 Reserved, cascade interrupt from sl ave PIC
3 COM2
4 COM1
5 LPT2 (Plug and Play option) / Audio / User available
6 Diskette drive
7 LPT1
8 Real-time clock
9 Reserved for ICH2 system management bus
10 User available
11 User available
12 Onboard mouse port (if present, else user available)
13 Reserved, math coprocessor
14 Primary IDE (if present, else user available)
15 Secondary IDE (if present, else user available)
Note: Default, but can be changed to another IRQ.
(Note)
(Note)
(Note)
Technical Reference
2.7 PCI Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected between the
PCI bus connectors and onboard PCI devices. The PCI specification specifies how interrupts can
be shared between devices attached to the PCI bus. In most cases, the small amount of latency
added by interrupt sharing does not affect the operation or throughput of the devices. In some
special cases where maximum performance is needed from a device, a PCI device should not share
an interrupt with other PCI devices. Use the following information to avoid sharing an interrupt
with a PCI add-in card.
PCI devices are categorized as follows to specify their interrupt grouping:
• INTA: By default, all add-in cards that require only one interrupt are in this category. For
almost all cards that require more than one interrupt, the first interrupt on the card is also
classified as INTA.
• INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is
classified as INTB. (This is not an absolute requirement.)
• INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a
The ICH2 has eight programmable interrupt request (PIRQ) input signals. All PCI interrupt
sources either onboard or from a PCI add-in card connect to one of these PIRQ signals. Some PCI
interrupt sources are electrically tied together on the D845HV and D845WN boards and therefore
share the same interrupt. Table 17 shows an example of how the PIRQ signals are routed on the
D845HV and D845WN boards.
For example, using Table 17 as a reference, assume an add-in card using INTB is plugged into PCI
bus connector 3. In PCI bus connector 3, INTB is connected to PIRQB, which is already
connected to the SMBus. The add-in card in PCI bus connector 3 now shares interrupts with these
onboard interrupt sources.
Table 17. PCI Interrupt Routing Map
PCI Interrupt Source
AGP connector INTB INTA to PIRQA
ICH2 USB controller #1 INTD to PIRQD
SMBus controller INTB
ICH2 USB controller INTC to PIRQH
ICH2 Audio / Modem INTB
ICH2 LAN INTA to PIRQE
PCI Bus Connector 1 INTA INTB INTC INTD
PCI Bus Connector 2 INTD INTA INTB INTC
PCI Bus Connector 3 INTC INTD INTA INTB
PCI Bus Connector 4
PCI Bus Connector 5
PCI Bus Connector 6
Note: D845WN board only.
(Note)
INTB INTC INTD INTA
(Note)
INTA INTB INTC INTD
(Note)
INTB INTC INTD INTA
PIRQF PIRQG PIRQH PIRQB Other
ICH2 PIRQ Signal Name
NOTE
✏
The ICH2 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 9, 10, 11,
12, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt.
However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ
lines to be connected to the same IRQ signal.
50
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Technical Reference
2.8 Connectors
CAUTION
Only the back panel, the front panel audio, and the front panel USB connectors of the D845HV
and D845WN boards have overcurrent protection. The D845HV and D845WN boards’ internal
connectors are not overcurrent protected and should connect only to devices inside the computer’s
chassis, such as fans and internal peripherals. Do not use these connectors to power devices
external to the computer’s chassis. A fault in the load presented by the external devices could
cause damage to the computer, the interconnecting cable, and the external devices themselves.
This section describes the board’s connectors. The connectors can be divided into the following
groups:
• Back panel I/O connectors (see page 52)
PS/2 keyboard and mouse
USB
Parallel port
Serial port A
LAN
Audio (Line out, Line in, and Mic in)
• Internal I/O connectors (see page 55)
Audio (telephony, auxiliary line input, and ATAPI CD-ROM)
Fans
Power
Add-in boards (CNR, PCI, and AGP)
IDE
Diskette drive
SCSI LED
• External I/O connectors (see page 68)
Front panel audio
Front panel USB
Serial port B
Auxiliary front panel power/sleep/message-waiting LED
Front panel (power/sleep/message-waiting LED, power switch, hard drive activity LED,
reset switch, and auxiliary front panel power LED)
NOTE
✏
When installing the board in a microATX chassis, make sure that peripheral devices are installed
at least 1.5 inches above the main power connector, the diskette drive connector, the IDE
connector, and the DIMM sockets.
Figure 10 shows the location of the back panel connectors. The back panel connectors are
color-coded in compliance with PC 99 recommendations. The figure legend below lists the
colors used.
A
F
G
C
BEJIDH
Item Description Color For more information see:
A PS/2 mouse port Green Table 18
B PS/2 keyboard port Purple Table 18
C USB port (optional) Black Table 19
D USB port (optional) Black Table 19
E Serial port A Teal Table 21
F Parallel port Burgundy Table 20
G LAN (optional) Black Table 22
H USB port Black Table 19
I USB port Black Table 19
J Mic in (optional) Pink Table 25
K Audio line out (optional) Lime green Table 24
L Audio line in (optional) Light blue Table 23
KL
OM11429
Figure 10. Back Panel Connectors
NOTE
✏
The back panel audio line out connector is designed to power headphones or amplified speakers
only. Poor audio quality occurs if passive (non-amplified) speakers are connected to this output.
52
Page 53
Table 18. PS/2 Mouse/Keyboard Connector
Pin Signal Name
1 Data
2 Not connected
3 Ground
4 +5 V (Fused)
5 Clock
6 Not connected
Table 19. USB Connectors
Pin Signal Name
1 +5 V (Fused)
2 USB#
3 USB
4 Ground
Technical Reference
Table 20. Parallel Port Connector
Pin Standard Signal Name ECP Signal Name EPP Signal Name
Tip Audio left in
Ring Audio right in
Sleeve Ground
Table 24. Audio Line Out Connector (Optional)
Pin Signal Name
Tip Audio left out
Ring Audio right out
Sleeve Ground
Table 25. Mic In Connector (Optional)
Pin Signal Name
Tip Mono in
Ring Mic bias voltage
Sleeve Ground
54
Page 55
2.8.2 Internal I/O Connectors
The internal I/O connectors are divided into the following functional groups:
• Audio (see page 56)
Telephony
Auxiliary line in
ATAPI CD-ROM
• Power and hardware control (see page 58)
Fans
ATX12V
Main power
• Add-in boards and peripheral interfaces (see page 61)
CNR (communication and networking riser)
PCI bus (three on the D845HV board; six on the D845WN board)
AGP
IDE (two)
Diskette drive
SCSI LED
Technical Reference
2.8.2.1 Expansion Slots
The board has the following expansion slots:
• One AGP connector. The AGP connector is keyed for 1.5 V AGP cards only. Do not install a
legacy 3.3 V AGP card. The AGP connector is not mechanically compatible with legacy 3.3 V
AGP cards.
• PCI rev 2.2 compliant local bus slots (three on the D845HV board, six on the D845WN board).
The SMBus is routed to PCI bus connector 1 only (ATX expansion slot 6). PCI add-in cards
with SMBus support can access sensor data and other information residing on the board.
• One CNR (optional), shared with PCI bus connector 3 (ATX expansion slot 1) on the D845HV
board or with PCI bus connector 6 (ATX expansion slot 1) on the D845WN board.
NOTE
✏
This document references back-panel slot numbering with respect to processor location on the
board. The AGP slot is not numbered. PCI slots are identified as PCI slot #x, starting with the
slot closest to the processor. The CNR slot shares an ATX expansion; slot 3 on the D845HV board
and slot 6 on the D845WN. The ATX/MicroATX specifications identify expansion slot locations
with respect to the far edge of a full-sized ATX chassis. The ATX specification and the board’s
silkscreen are opposite and could cause confusion. The ATX numbering convention is made
without respect to slot type (PCI vs. AGP), but refers to an actual slot location on a chassis.
Figure 13 on page 61 illustrates the board’s PCI slot numbering.
Figure 12 shows the location of the power and hardware control connectors.
A
12
4
3
B
1
1
20
1
1
F
E
10
11
1
Item Description For more information see:
A ATX12V power Table 29
B Rear chassis fan Table 30
C Processor fan Table 31
D Main power Table 32
E Chassis intrusion Table 33
F Front chassis fan (optional) Table 34
Figure 12. Power and Hardware Control Connectors
C
D
OM11431
For information about Refer to
The power connector Section 1.14.2.1, page 41
The functions of the fan connectors Section 1.14.2.2, page 42
58
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Technical Reference
NOTE
✏
Use only ATX12V- or SFX12V-compliant power supplies with the D845HV and D845WN boards.
ATX12V and SFX12V power supplies have an additional power lead that provides required
supplemental power for the Intel Pentium
4
processor. Always connect the 20-pin and 4-pin leads
of ATX12V and SFX12V power supplies to the corresponding connectors on the D845HV and
D845WN boards, otherwise the board will not boot.
Do not use a standard ATX power supply. The board will not boot with a standard ATX power
supply.
Table 29. ATX12V Power Connector
Pin Signal Name Pin Signal Name
1 Ground 3 +12 V
2 Ground 4 +12 V
NOTE
✏
The board will not boot if the ATX12V power connector is not attached to the board.
1 +3.3 V 11 +3.3 V
2 +3.3 V 12 -12 V
3 Ground 13 Ground
4 +5 V 14 PS-ON# (power supply remote on/off)
5 Ground 15 Ground
6 +5 V 16 Ground
7 Ground 17 Ground
8 PWRGD (Power Good) 18 No connect
9 +5 V (Standby) 19 +5 V
10 +12 V 20 +5 V
Table 33. Chassis Intrusion Connector
Pin Signal Name
1 Intruder
2 Ground
Table 34. Front Chassis Fan Connector (Optional)
Pin Signal Name
1 Ground
2 +12 V
3 No connect
60
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Technical Reference
2.8.2.4 Add-in Board and Peripheral Interface Connectors
Figure 13 shows the location of the add-in board connector and peripheral connectors for the
D845HV board. Note the following considerations for the PCI bus connectors (for both boards):
• All of the PCI bus connectors are bus master capable.
• PCI bus connector 1 has SMBus signals routed to it. This enables PCI bus add-in boards with
SMBus support to access sensor data on the board. The specific SMBus signals are as follows:
The SMBus clock line is connected to pin A40
The SMBus data line is connected to pin A41
A
1
E
DCB
2
1
2
1
40
39
40
2
1
39
34
33
I
Item Description For more information see:
A Communication and networking riser (CNR) Table 35
B PCI bus connector 3 Table 36
C PCI bus connector 2 Table 36
D PCI bus connector 1 Table 36
E AGP connector Table 37
F Diskette drive Table 38
G Primary IDE Table 39
H Secondary IDE Table 39
I SCSI LED (Optional) Table 40
Figure 13. D845HV Add-in Board and Peripheral Interface Connectors
Figure 14 shows the location of the add-in board connector and peripheral connectors for the
D845WN board.
A
H
GFEBCD
2
1
1
L
2
1
J
40
39
40
2
1
39
IK
Item Description For more information see:
A Communication and networking riser (CNR) Table 35
B PCI bus connector 6 Table 36
C PCI bus connector 5 Table 36
D PCI bus connector 4 Table 36
E PCI bus connector 3 Table 36
F PCI bus connector 2 Table 36
G PCI bus connector 1 Table 36
H AGP connector Table 37
I Diskette drive Table 38
J Primary IDE Table 39
K Secondary IDE Table 39
L SCSI LED (Optional) Table 40
Figure 14. D845WN Add-in Board and Peripheral Interface Connectors
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
A1 Ground (TRST#)* B1 -12 V A32 AD16 B32 AD17
A2 +12 V B2 Ground (TCK)* A33 +3.3 V B33 C/BE2#
A3 +5 V (TMS)* B3 Ground A34 FRAME# B34 Ground
A4 +5 V (TDI)* B4 Not connected (TDO)* A35 Ground B35 IRDY#
A5 +5 V B5 +5 V A36 TRDY# B36 +3.3 V
A6 INTA# B6 +5 V A37 Ground B37 DEVSEL#
A7 INTC# B7 INTB# A38 STOP# B38 Ground
A8 +5 V B8 INTD# A39 +3.3 V B39 LOCK#
A9 Reserved B9 Not connected
(PRSNT1#)*
A10 +5 V (I/O) B10 Reserved A41 Reserved *** B41 +3.3 V
A11 Reserved B11 Not connected
(PRSNT2#)*
A12 Ground B12 Ground A43 PAR B43 +3.3 V
A13 Ground B13 Ground A44 AD15 B44 C/BE1#
A14 +3.3 V aux B14 Reserved A45 +3.3 V B45 AD14
A15 RST# B15 Ground A46 AD13 B46 Ground
A16 +5 V (I/O) B16 CLK A47 AD11 B47 AD12
A17 GNT# B17 Ground A48 Ground B48 AD10
A18 Ground B18 REQ# A49 AD09 B49 Ground
A19 PME# B19 +5 V (I/O) A50 Key B50 Key
A20 AD30 B20 AD31 A51 Key B51 Key
A21 +3.3 V B21 AD29 A52 C/BE0# B52 AD08
A22 AD28 B22 Ground A53 +3.3 V B53 AD07
A23 AD26 B23 AD27 A54 AD06 B54 +3.3 V
A24 Ground B24 AD25 A55 AD04 B55 AD05
A25 AD24 B25 +3.3 V A56 Ground B56 AD03
A26 IDSEL B26 C/BE3# A57 AD02 B57 Ground
A27 +3.3 V B27 AD23 A58 AD00 B58 AD01
A28 AD22 B28 Ground A59 +5 V (I/O) B59 +5 V (I/O)
A29 AD20 B29 AD21 A60 REQ64# B60 ACK64#
A30 Ground B30 AD19 A61 +5 V B61 +5 V
A31 AD18 B31 +3.3 V A62 +5 V B62 +5 V
* These signals (in parentheses) are optional in the PCI specificati on and are not currently implemented.
** On PCI bus c onnector 1, this pin is c onnected to the SMBus c l ock line.
*** On PCI bus connector 1, this pin is connected to the SMBus data line.
A40 Reserved ** B40 PERR#
A42 Ground B42 SERR#
64
Page 65
Table 37. AGP Connector
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
The AGP connector is keyed for 1.5 V AGP cards only. Do not attempt to install a legacy 3.3 V
AGP card. The AGP connector is not mechanically compatible with legacy 3.3 V AGP cards.
The front panel audio connector is alternately used as a jumper block for routing audio signals.
Refer to Section 2.9.1 on page 72 for more information.
Table 42. Serial Port B Connector (Optional)
Pin Signal Name Pin Signal Name
1 DCD (Data Carrier Detect) 2 RXD# (Receive Data)
3 TXD# (Transmit Data) 4 DTR (Data Terminal Ready)
5 Ground 6 DSR (Data Set Ready)
7 RTS (Request to Send) 8 CTS (Clear to Send)
9 RI (Ring Indicator) 10 Not connected
This section describes the functions of the front panel connector. Table 45 lists the signal names
of the front panel connector.
Table 45. Front Panel Connector
Pin Signal In/Out Description Pin Signal In/Out Description
Hard Drive Activity LED Power LED
1 HD_PWR Out Hard disk LED
pull-up (330 Ω) to +5
V
3 HAD# Out Hard disk active LED 4 HDR_BLNK_
Reset Switch On/Off Switch
5 Ground Ground 6 FPBUT_IN In Power switch
7 FP_RESET# In Reset switch 8 Ground Ground
Infrared Port Miscellaneous
9 +5 V Out Power 10 N/C
11 IRRX In IrDA serial input 12 Ground Ground
13 Ground Ground 14 (pin removed) Not connected
15 IRTX Out IrDA serial output 16 +5 V Out Power
2 HDR_BLNK_
GRN
YEL
Out Front panel green
LED
Out Front panel yellow
LED
2.8.3.2.1 Hard Drive Activity LED Connector
Pins 1 and 3 can be connected to an LED to provide a visual indicator that data is being read from
or written to a hard drive. For the LED to function properly, an IDE drive must be connected to
the onboard IDE interface. The LED will also show activity for devices connected to the optional
SCSI hard drive activity LED connector.
For information about Refer to
The SCSI hard drive activity LED connector Section 1.8.3.2, page 28
2.8.3.2.2 Reset Switch Connector
Pins 5 and 7 can be connected to a momentary SPST type switch that is normally open. When the
switch is closed, the D845HV/D845WN board resets and runs the POST.
2.8.3.2.3 Infrared Port Connector
Pins 9, 11, 13, and 15 can be connected to an IrDA module. After the IrDA interface is configured
in the BIOS Setup program, files can be transferred to or from portable devices such as laptops,
PDAs, and printers using application software.
NOTE
✏
The infrared port operates in half duplex mode only.
70
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Technical Reference
NOTE
✏
The operation of the infrared port and serial port B are mutually exclusive. When the IR option is
enabled in the BIOS Setup program, serial port B is disabled.
2.8.3.2.4 Power/Sleep/Message Waiting LED Connector
Pins 2 and 4 can be connected to a one- or two-color LED. Table 46 shows the possible states for
a one-color LED. Table 47 shows the possible states for a two-color LED.
Table 46. States for a One-Color Power LED
LED State Description
Off Power off/sleeping
Steady Green Running
Blinking Green Running/message waiting
Table 47. States for a Two-Color Power LED
LED State Description
Off Power off
Steady Green Running
Blinking Green Running/message waiting
Steady Yellow Sleeping
Blinking Yellow Sleeping/message waiting
✏ NOTE
To use the message waiting function, ACPI must be enabled in the operating system and a
message-capturing application must be invoked.
2.8.3.2.5 Power Switch Connector
Pins 6 and 8 can be connected to a front panel momentary-contact power switch. The switch must
pull the SW_ON# pin to ground for at least 50 ms to signal the power supply to switch on or off.
(The time requirement is due to internal debounce circuitry on the D845HV/D845WN board.) At
least two seconds must pass before the power supply will recognize another on/off signal.
Do not move any jumpers with the power on. Always turn off the power and unplug the power
cord from the computer before changing a jumper setting. Otherwise, the board could be
damaged.
Figure 16 shows the location of the jumper blocks on the D845HV and D845WN boards.
2
1
4
3
6
5
A
7
10
9
1
B
Item Description Reference Designator
A Front panel audio connector / jumper block J8B4 (D845HV board)
B BIOS Setup configuration jumper block J9G1 (D845HV board)
3
OM11435
J7B2 (D845WN board)
J7G1 (D845WN board)
Figure 16. Location of the Jumper Block
2.9.1 Front Panel Audio Connector/Jumper Block
This connector has two functions:
• With jumpers installed, the audio line out signals are routed to the back panel audio line out
connector.
• With jumpers removed, the connector provides audio line out and mic in signals for front panel
audio connectors.
Table 48 describes the two configurations of this connector/jumper block.
72
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Technical Reference
CAUTION
Do not place jumpers on this block in any configuration other than the one described in Table 48.
Other jumper configurations are not supported and could damage the board.
Table 48. Front Panel Audio Connector / Jumper Block
Jumper Setting Configuration
1
34
5
7
9
1
34
5
7
9
2
6
10
2
6
10
5 and 6
9 and 10
No jumpers
installed
Audio line out signals are routed to the back panel audio line out
connector. The back panel audio line out connector is shown in Figure 10
on page 52.
Audio line out and mic in signals are available for front panel audio
connectors. Table 41 on page 69 lists the names of the signals available
on this connector when no jumpers are installed.
NOTE
✏
When the jumpers are removed and this connector is used for front panel audio, the back panel
audio line out and mic in connectors are disabled.
2.9.2 BIOS Setup Configuration Jumper Bl ock
The 3-pin jumper block determines the BIOS Setup program’s mode. Table 49 describes the
jumper settings for the three modes: normal, configure, and recovery. When the jumper is set to
configuration mode and the computer is powered-up, the BIOS compares the processor version and
the microcode version in the BIOS and reports if the two match.
The BIOS uses current configuration information and
passwords for booting.
After the POST runs, Setup runs automatically. The
maintenance menu is displayed.
The BIOS attempts to recover the BIOS configuration. A
recovery diskette is required.
For information about Refer to
How to access the BIOS Setup program Section 4.1, page 95
The maintenance menu of the BIOS Setup program Section 4.2, page 96
BIOS recovery Section 3.7, page 91
The D845HV board is designed to fit into either a microATX or an ATX-form-factor chassis.
Figure 17 illustrates the mechanical form factor for the D845HV board. Dimensions are given in
inches [millimeters]. The outer dimensions are 9.60 inches by 9.60 inches [243.84 millimeters by
243.84 millimeters]. Location of the I/O connectors and mounting holes are in compliance with
the ATX specification (see Section 1.4).
NOTE
✏
When installing the board in a microATX chassis, make sure that peripheral devices are installed
at least 1.5 inches above the main power connector, the diskette drive connector, and the IDE
connector, and the DIMM sockets.
6.50[165.10]
6.10[154.94]
0.00
2.85[72.39]
3.10[78.74]
0.55[13.97]
0.00
0.80
[20.32]
2.60
[66.04]
8.80
[223.52]
5.20[132.08]
9.05[229.87]
OM11436
74
Figure 17. D845HV Board Dimensions
Page 75
Technical Reference
2.10.2 D845WN Form Factor
The D845WN board is designed to fit into an ATX-form-factor chassis. Figure 18 illustrates the
mechanical form factor for the D845WN board. Dimensions are given in inches [millimeters].
The outer dimensions are 12.00 inches by 9.60 inches [304.48 millimeters by 243.84 millimeters].
Location of the I/O connectors and mounting holes are in compliance with the ATX specification
(see Section 1.4).
The back panel I/O shield for D845HV and D845WN boards must meet specific dimension and
material requirements. Systems based on this board need the back panel I/O shield to pass
certification testing. Figure 19 shows the critical dimensions of the chassis-dependent I/O shield
for boards with the onboard LAN subsystem. Figure 20 shows the critical dimensions of the I/O
for boards without the onboard LAN subsystem. Dimensions are given in inches to a tolerance of
±0.02 inches.
The figure also indicates the position of each cutout. Additional design considerations for I/O
shields relative to chassis requirements are described in the ATX specification. See Section 1.4 for
information about the ATX specification.
NOTE
✏
The I/O shield drawings in this document are for reference only. An I/O shield compliant with the
ATX chassis specification 2.01 is available from Intel.
6.390 Ref
[162.300]
0.063±0.005
[1.600±0.120]
0.884
[22.450]
0.276
[7.012]
0.00
0.465
[11.811]
0.567
[14.400]
0.039 Dia. [1.000]
0.00
0.447
[11.345]
0.787±0.010 TYP [20±0.254]
2.079
1.807
1.195
[30.360]
[45.892]
[52.804]
3x Dia 0.330 [8.380]
5.010
5.732
[127.250]
0.621
[15.770]
[145.584]
Pictorial
View
8X R0.5 MIN
0.519
[13.190]
0.027
[0.690]
0.465
[11.811]
0.567
[14.400]
1.89
Ref
Figure 19. I/O Shield Dimensions (for boards with the LAN Subsystem)
76
OM12352
Page 77
6.390 Ref
[162.300]
0.787±0.010 TYP [20±0.254]
Technical Reference
0.063±0.005
[1.600±0.120]
0.884
[22.450]
0.276
[7.012]
0.00
0.465
[11.811]
0.567
[14.400]
0.039 Dia. [1.000]
0.00
0.447
[11.345]
1.195
[30.360]
1.807
[45.892]
2.079
[52.804]
3x Dia 0.330 [8.380]
5.010
5.732
[127.250]
0.621
[15.770]
[145.584]
Pictorial
View
8X R0.5 MIN
0.519
[13.190]
0.027
[0.690]
0.465
[11.811]
0.567
[14.400]
1.89
Ref
OM12353
Figure 20. I/O Shield Dimensions (for boards without the LAN Subsystem)
Table 50 lists voltage and current measurements for a computer that contains the
D845HV/D845WN board and the following:
• 1.7 GHz Intel Pentium 4 processor with a 256 KB cache
• 256 MB SDRAM
• 3.5-inch diskette drive
• 20 GB IDE hard disk drive
• 32X IDE CD-ROM drive
This information is provided only as a guide for calculating approximate power usage with
additional resources added.
Values for the Windows 98SE desktop mode are measured at 640 x 480 x 256 colors and 60 Hz
refresh rate. AC watts are measured with the computer is connected to a typical 250 W power
supply, at nominal input voltage and frequency, with a true RMS wattmeter at the line input.
✏ NOTE
Actual system power consumption depends upon system configuration. The power supply should
comply with the recommendations found in the ATX / ATX12V Power Supply Design Guide,
Version 1.1 (see Section 1.5 on page 18 for specification information).
Table 50. Power Usage
DC Current at:
Mode AC Power +3.3 V +5 V +12 V -12 V +5 VSB
ACPI S0 163 W 11.5 A 4.0 A 7.6 A 1.0 A 0.200 A
ACPI S1 26 W 4.7 A 0.008 A 0.750 A 0.038 A 0.164 A
ACPI S3 2 W 0.0 A 0.0 A 0.0 A 0.0 A 0.394 A
2.11.2 Add-in Board Considerations
The D845HV and D845WN boards are designed to provide 2 A (average) of +5 V current for each
add-in board. The total +5 V current draw for add-in boards is as follows:
• For a fully loaded D845HV board (all four expansion slots filled), the total +5 V current draw
must not exceed 8 A.
• For a fully loaded D845WN board (all seven expansion slots filled), the total +5 V current
draw must not exceed 14 A.
78
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Technical Reference
2.11.3 Standby Current Requirements
CAUTION
If the standby current necessary to support multiple wake events from the PCI and/or USB buses
exceeds power supply capacity, the D845HV and D845WN boards may lose register settings stored
in memory, etc. Calculate the standby current requirements using the steps described below.
Power supplies used with the D845HV and D845WN boards must be able to provide enough
standby current to support the Instantly Available PC (ACPI S3 sleep state) configuration as
outlined in Table 51 below.
Values are determined by specifications such as PCI 2.2. Actual measured values may vary.
To estimate the amount of standby current required for a particular system configuration, standby
current requirements of all installed components must be added to determine the total standby
current requirement. Refer to the descriptions in Table 51 and review the following steps.
1. Note the total D845HV or D845WN board standby current requirement.
2. Add to that the total PS/2 port standby current requirement if a wake-enabled device is
connected.
3. Add, from the PCI 2.2 slots (wake enabled) row, the total number of wake-enabled devices
installed (PCI and AGP) and multiply by the standby current requirement.
4. Add, from the PCI 2.2 slots (nonwake enabled) row, the total number of wake-enabled devices
installed (PCI and AGP) and multiply by the standby current requirement.
5. Add all additional wake-enabled devices’ and nonwake-enabled devices’ standby current
requirements as applicable.
6. Add all the required current totals from steps 1 through 5 to determine the total estimated
standby current power supply requirement.
Table 51. Standby Current Requirements
Instantly Available PC Current
Support (Estimated for
Integrated Board Components)
Instantly Available PC Stand-by
Current Support
• Estimated for add-on
components
• Add to Instantly Available
PC total current
requirement
(See instructions above)
Note: Dependent upon system configuration
Description
Total for D845HV board 394
PS/2 ports
PCI 2.2 slots (wake enabled) 375
PCI 2.2 slots (nonwake enabled) 20
PCI/AGP requirements are calculated by totaling the following:
• One wake-enabled device @ 375 mA, plus
• Five nonwake-enabled devices @ 20 mA each, plus
USB requirements are calculated as:
• One wake-enabled device @ 500 mA
• USB hub @ 100 mA
• Three USB nonwake-enabled devices connected @ 2.5 mA each
NOTE
✏
Both USB ports are capable of providing up to 500 mA during normal G0/S0 operation. Only one
USB port will support up to 500 mA of stand-by-current (wake-enabled device) during G1/S3
suspended operation. The other port may provide up to 7.5 mA (three nonwake-enabled devices.)
during G1/S3 suspended operation.
2.11.4 Fan Connector Current Capability
Table 52 lists the current capability of the fan connectors on the D845HV and D845WN boards.
Table 52. Fan Connector Current Capability
Fan Connector Maximum Available Current
Processor fan 1.20 A
Front chassis fan (optional) 0.50 A
Rear chassis fan 0.35 A
2.11.5 Power Supply Considerations
CAUTION
The +5 V standby line for the power supply must be capable of providing adequate +5 V standby
current. Failure to do so can damage the power supply. The total amount of standby current
required depends on the wake devices supported and manufacturing options. Refer to
Section 2.11.3 on page 78 for additional information.
System integrators should refer to the power usage values listed in Table 50 when selecting a
power supply for use with the D845HV or D845WN boards.
Measurements account only for current sourced by the D845HV or D845WN boards while running
in idle modes of the started operating systems.
Additional power required will depend on configurations chosen by the integrator.
80
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Technical Reference
The power supply must comply with the following recommendations found in the indicated
sections of the ATX form factor specification.
• The potential relation between 3.3 VDC and +5 VDC power rails (Section 4.2)
• The current capability of the +5 VSB line (Section 4.2.1.2)
• All timing parameters (Section 4.2.1.3)
• All voltage tolerances (Section 4.2.2)
For information about Refer to
The ATX form factor specification
Section 1.5, page 18
2.12 Thermal Considerations
CAUTION
Ensure that the ambient temperature does not exceed the board’s maximum operating temperature.
Failure to do so could cause components to exceed their maximum case temperature and
malfunction. For information about the maximum operating temperature, see the environmental
specifications in Section 2.14.
CAUTION
Ensure that proper airflow is maintained in the processor voltage regulator circuit. Failure to do
so may result in damage to the voltage regulator circuit. The processor voltage regulator area
(item A in Figure 21) can reach a temperature of up to 85
Figure 21 shows the locations of the localized high temperature zones.
A Processor voltage regulator area
B Processor
C Intel 82845 MCH
D Intel 82801BA ICH2
Figure 21. Localized High Temperature Zones
Table 53 provides maximum case temperatures for D845HV/D845WN board components that are
sensitive to thermal changes. The operating temperature, current load, or operating frequency
could affect case temperatures. Maximum case temperatures are important when considering
proper airflow to cool the D845HV/D845WN boards.
Table 53. Thermal Considerations for Components
Component Maximum Case Temperature
Intel Pentium 4 processor For processor case temperature, see processor datasheets and
The mean time between failures (MTBF) prediction is calculated using component and
subassembly random failure rates. The calculation is based on the Bellcore Reliability Prediction
Procedure, TR-NWT-000332, Issue 4, September 1991. The MTBF prediction is used to estimate
repair rates and spare parts requirements.
The Mean Time Between Failures (MTBF) data is calculated from predicted data at 55 ºC. The
MTBF calculations for the boards are as follows:
• D845HV board MTBF: 147370.4687 hours
• D845WN board MTBF: 126077.3308 hours
2.14 Environmental
Table 54 lists the environmental specifications for the D845HV and D845WN boards.
This section describes the D845HV and D845WN boards’ compliance with U.S. and international
safety and electromagnetic compatibility (EMC) regulations.
2.15.1 Safety Regulations
Table 55 lists the safety regulations the D845HV and D845WN boards comply with when
correctly installed in a compatible host system.
Table 55. Safety Regulations
Regulation Title
UL 1950/CSA C22.2 No. 950, 3rd
edition
EN 60950, 2nd Edition, 1992
(with Amendments 1, 2, 3, and 4)
EMKO-TSE (74-SEC) 207/94 Summary of Nordic deviations to EN 60950. (Norway, Sweden,
Bi-National Standard for Safety of Information Technology Equipment
including Electrical Business Equipment. (USA and Canada)
The Standard for Safety of Information Technology Equipment including
Electrical Business Equipment. (European Union)
The Standard for Safety of Information Technology Equipment including
Electrical Business Equipment. (International)
Denmark, and Finland)
2.15.2 EMC Regulations
Table 56 lists the EMC regulations the D845HV and D845WN boards comply with when correctly
installed in a compatible host system.
Table 56. EMC Regulations
Regulation Title
FCC (Class B) Title 47 of the Code of Federal Regulations, Parts 2 and 15, Subpart B,
Radiofrequency Devices. (USA)
ICES-003 (Class B) Interference-Causing Equipment Standard, Digital Apparatus. (Canada)
EN55022: 1998 (Class B) Limits and methods of measurement of Radio Interference
Characteristics of Information Technology Equipment. (European
Union)
EN55024: 1998 Information Technology Equipment – Immunity Characteristics Limits
and methods of measurement. (European Union)
AS/NZS 3548 (Class B) Australian Communications Authority, Standard for Electromagnetic
Compatibility. (Australia and New Zealand)
CISPR 22, 3rd Edition (Class B) Limits and methods of measurement of Radio Disturbance
Characteristics of Information Technology Equipment. (International)
CISPR 24: 1997 Information Technology Equipment – Immunity Characteristics – Limits
The D845HV and D845WN boards use an Intel/AMI BIOS that is stored in the Firmware Hub
(FWH) and can be updated using a disk-based program. The FWH contains the BIOS Setup
program, POST, the PCI auto-configuration utility, and Plug and Play support.
The D845HV and D845WN boards support system BIOS shadowing, allowing the BIOS to
execute from 64-bit onboard write-protected system memory.
The BIOS displays a message during POST identifying the type of BIOS and a revision code. The
initial production BIOSs are identified as HV84510A.86A.
When the D845HV or D845WN board’s jumper is set to configuration mode and the computer is
powered-up, the BIOS compares the CPU version and the microcode version in the BIOS and
reports if the two match.
For information about Refer to
The D845HV and D845WN boards’ compliance level with Plug and Play Section 1.5, page 18
The Intel 82802AB Firmware Hub (FWH) includes a 4 Mbit (512 KB) symmetrical flash memory
device. Internally, the device is grouped into eight 64-KB blocks that are individually erasable,
lockable, and unlockable.
3.3 Resource Configuration
3.3.1 PCI Autoconfiguration
The BIOS can automatically configure PCI devices. PCI devices may be onboard or add-in cards.
Autoconfiguration lets a user insert or remove PCI cards without having to configure the system.
When a user turns on the system after adding a PCI card, the BIOS automatically configures
interrupts, the I/O space, and other system resources. Any interrupts set to Available in Setup are
considered to be available for use by the add-in card. Autoconfiguration information is stored in
ESCD format.
For information about the versions of PCI and Plug and Play supported by the BIOS, see
Section 1.4.
3.3.2 PCI IDE Support
If you select Auto in the BIOS Setup program, the BIOS automatically sets up the two
PCI IDE connectors with independent I/O channel support. The IDE interface supports hard drives
up to ATA-66/100 and recognizes any ATAPI compliant devices, including CD-ROM drives, tape
drives, and Ultra DMA drives (see Section 1.4 for the supported version of ATAPI). The BIOS
determines the capabilities of each drive and configures them to optimize capacity and
performance. To take advantage of the high capacities typically available today, hard drives are
automatically configured for Logical Block Addressing (LBA) and to PIO Mode 3 or 4, depending
on the capability of the drive. You can override the auto-configuration options by specifying
manual configuration in the BIOS Setup program.
To use ATA-66/100 features the following items are required:
• An ATA-66/100 peripheral device
• An ATA-66/100 compatible cable
• ATA-66/100 operating system device drivers
NOTE
✏
ATA-66/100 compatible cables are backward compatible with drives using slower IDE transfer
protocols. If an ATA-66/100 disk drive and a disk drive using any other IDE transfer protocol are
attached to the same cable, the maximum transfer rate between the drives is reduced to that of the
slowest device.
NOTE
✏
Do not connect an ATA device as a slave on the same IDE cable as an ATAPI master device. For
example, do not connect an ATA hard drive as a slave to an ATAPI CD-ROM drive.
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Overview of BIOS Features
3.4 System Management BIOS (SMBIOS)
SMBIOS is a Desktop Management Interface (DMI) compliant method for managing computers in
a managed network.
The main component of SMBIOS is the management information format (MIF) database, which
contains information about the computing system and its components. Using SMBIOS, a system
administrator can obtain the system types, capabilities, operational status, and installation dates for
system components. The MIF database defines the data and provides the method for accessing this
information. The BIOS enables applications such as third-party management software to use
SMBIOS. The BIOS stores and reports the following SMBIOS information:
• BIOS data, such as the BIOS revision level
• Fixed-system data, such as peripherals, serial numbers, and asset tags
• Resource data, such as memory size, cache size, and processor speed
• Dynamic data, such as event detection and error logging
Non-Plug and Play operating systems, such as Windows NT, require an additional interface for
obtaining the SMBIOS information. The BIOS supports an SMBIOS table interface for such
operating systems. Using this support, an SMBIOS service-level application running on a
non-Plug and Play operating system can obtain the SMBIOS information.
For information about Refer to
The D845HV and D845WN boards’ compliance level with SMBIOS Section 1.4, page 17
3.5 Legacy USB Support
Legacy USB support enables USB devices such as keyboards, mice, and hubs to be used even
when the operating system’s USB drivers are not yet available. Legacy USB support is used to
access the BIOS Setup program, and to install an operating system that supports USB. By default,
Legacy USB support is set to Enabled.
Legacy USB support operates as follows:
1. When you apply power to the computer, legacy support is disabled.
2. POST begins.
3. Legacy USB support is enabled by the BIOS allowing you to use a USB keyboard to enter and
configure the BIOS Setup program and the maintenance menu.
5. The operating system loads. While the operating system is loading, USB keyboards and mice
are recognized and may be used to configure the operating system. (Keyboards and mice are
not recognized during this period if Legacy USB support was set to Disabled in the BIOS
Setup program.)
6. After the operating system loads the USB drivers, all legacy and non-legacy USB devices are
recognized by the operating system, and Legacy USB support from the BIOS is no longer
used.
To install an operating system that supports USB, verify that Legacy USB support in the BIOS
Setup program is set to Enabled and follow the operating system’s installation instructions.
NOTE
✏
Legacy USB support is for keyboards, mice, and hubs only. Other USB devices are not supported
in legacy mode.
3.6 BIOS Updates
The BIOS can be updated using either of the following utilities, which are available on the Intel
World Wide Web site:
®
• Intel
• Intel
Both utilities support the following BIOS maintenance functions:
• Verifying that the updated BIOS matches the target system to prevent accidentally installing
• Updating both the BIOS boot block and the main BIOS. This process is fault tolerant to
• Updating the BIOS boot block separately.
• Changing the language section of the BIOS.
• Updating replaceable BIOS modules, such as the video BIOS module.
• Inserting a custom splash screen.
NOTE
✏
Review the instructions distributed with the upgrade utility before attempting a BIOS update.
Express BIOS Update utility, which enables automated updating while in the Windows
environment. Using this utility, the BIOS can be updated from a file on a hard disk, a 1.44 MB
diskette, or a CD-ROM, or from the file location on the Web.
®
Flash Memory Update Utility, which requires creation of a boot diskette and manual
rebooting of the system. Using this utility, the BIOS can be updated from a file on a 1.44 MB
diskette (from a legacy diskette drive or an LS-120 diskette drive) or a CD-ROM.
an incompatible BIOS.
prevent boot block corruption.
For information about Refer to
The Intel World Wide Web site Section 1.3, page 17
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Overview of BIOS Features
3.6.1 Language Support
The BIOS Setup program and help messages are supported in five languages: US English,
German, Italian, French, and Spanish. The default language is US English, which is present unless
another language is selected in the BIOS Setup program.
3.6.2 Custom Splash Screen
During POST, an Intel splash screen is displayed by default. This splash screen can be replaced
with a custom splash screen. A utility is available from Intel to assist with creating a custom
splash screen. The custom splash screen can be programmed into the flash memory using the
BIOS upgrade utility. Information about this capability is available on the Intel Support World
Wide Web site.
For information about Refer to
The Intel World Wide Web site Section 1.3, page 17
3.7 Recovering BIOS Data
Some types of failure can destroy the BIOS. For example, the data can be lost if a power outage
occurs while the BIOS is being updated in flash memory. The BIOS can be recovered from a
diskette using the BIOS recovery mode. When recovering the BIOS, be aware of the following:
• Because of the small amount of code available in the non-erasable boot block area, there is no
video support. You can only monitor this procedure by listening to the speaker or looking at
the diskette drive LED.
• The recovery process may take several minutes; larger BIOS flash memory devices require
more time.
• Two beeps and the end of activity in the diskette drive indicate successful BIOS recovery.
• A series of continuous beeps indicates a failed BIOS recovery.
To create a BIOS recovery diskette, a bootable diskette must be created and the BIOS update files
copied to it. BIOS upgrades and the Intel Flash Memory Update Utility are available from Intel
Customer Support through the Intel World Wide Web site.
NOTE
✏
Even if the computer is configured to boot from an LS-120 diskette (in the Setup program’s
Removable Devices submenu), the BIOS recovery diskette must be a standard 1.44 MB diskette not
a 120 MB diskette.
For information about Refer to
The BIOS recovery mode jumper settings Section 2.9, page 72
The Boot menu in the BIOS Setup program Section 4.6.1, page 112
Contacting Intel customer support Section 1.3, page 17
In the BIOS Setup program, the user can choose to boot from a diskette drive, hard drives,
CD-ROM, or the network. The default setting is for the diskette drive to be the first boot device,
the hard drive second, and the ATAPI CD-ROM third. The fourth device is disabled.
3.8.1 CD-ROM and Network Boot
Booting from CD-ROM is supported in compliance to the El Torito bootable CD-ROM format
specification. Under the Boot menu in the BIOS Setup program, ATAPI CD-ROM is listed as a
boot device. Boot devices are defined in priority order. Accordingly, if there is not a bootable CD
in the CD-ROM drive, the system will attempt to boot from the next defined drive.
The network can be selected as a boot device. This selection allows booting from the onboard
LAN or a network add-in card with a remote boot ROM installed.
For information about Refer to
The El Torito specification Section 1.5, page 18
3.8.2 Booting Without Attached Devices
For use in embedded applications, the BIOS has been designed so that after passing the POST, the
operating system loader is invoked even if the following devices are not present:
• Video adapter
• Keyboard
• Mouse
3.9 Fast Booting Systems with Intel® Rapid BIOS Boot
These factors affect system boot speed:
• Selecting and configuring peripherals properly
®
• Using an optimized BIOS, such as the Intel
3.9.1 Peripheral Selecti on and Configuration
The following techniques help improve system boot speed:
• Choose a hard drive with parameters such as “power-up to data ready” less than eight seconds,
that minimize hard drive startup delays.
• Select a CD-ROM drive with a fast initialization rate. This rate can influence POST
execution time.
• Eliminate unnecessary add-in adapter features, such as logo displays, screen repaints, or mode
changes in POST. These features may add time to the boot process.
• Try different monitors. Some monitors initialize and communicate with the BIOS more
quickly, which enables the system to boot more quickly.
Rapid BIOS
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Overview of BIOS Features
3.9.2 Intel Rapid BIOS Boot
Use of the following BIOS Setup program settings reduces the POST execution time.
In the Boot Menu:
• Set the hard disk drive as the first boot device. As a result, the POST does not first seek a
diskette drive, which saves about one second from the POST execution time.
• Disable Quiet Boot, which eliminates display of the logo splash screen. This could save
several seconds of painting complex graphic images and changing video modes.
• Enabled Intel Rapid BIOS Boot. This feature bypasses memory count and the search for a
diskette drive.
In the Peripheral Configuration submenu, disable the LAN device if it will not be used. This can
reduce up to four seconds of option ROM boot time.
NOTE
✏
It is possible to optimize the boot process to the point where the system boots so quickly that the
Intel logo screen (or a custom logo splash screen) will not be seen. Monitors and hard disk drives
with minimum initialization times can also contribute to a boot time that might be so fast that
necessary logo screens and POST messages cannot be seen.
This boot time may be so fast that some drives might be not be initialized at all. If this condition
should occur, it is possible to introduce a programmable delay ranging from 3 to 30 seconds
(using the Hard Disk Pre-Delay feature of the Advanced Menu in the IDE Configuration Submenu
of the BIOS Setup program).
For information about Refer to
IDE Configuration Submenu in the BIOS Setup program Section 4.4.4, page 104
The BIOS includes security features that restrict access to the BIOS Setup program and who can
boot the computer. A supervisor password and a user password can be set for the BIOS Setup
program and for booting the computer, with the following restrictions:
• The supervisor password gives unrestricted access to view and change all the Setup options in
the BIOS Setup program. This is the supervisor mode.
• The user password gives restricted access to view and change Setup options in the BIOS Setup
program. This is the user mode.
• If only the supervisor password is set, pressing the <Enter> key at the password prompt of the
BIOS Setup program allows the user restricted access to Setup.
• If both the supervisor and user passwords are set, users can enter either the supervisor
password or the user password to access Setup. Users have access to Setup respective to
which password is entered.
• Setting the user password restricts who can boot the computer. The password prompt will be
displayed before the computer is booted. If only the supervisor password is set, the computer
boots without asking for a password. If both passwords are set, the user can enter either
password to boot the computer.
Table 57 shows the effects of setting the supervisor password and user password. This table is for
reference only and is not displayed on the screen.
Table 57. Supervisor and User Password Functions
Password Set
Neither Can change all
Supervisor
only
User only N/A Can change all
Supervisor
and user set
Note: If no password is set, any us er can change all Setup options.
Supervisor
Mode
options
Can change all
options
Can change all
options
(Note)
User Mode Setup Options
Can change all
options
Can change a
limited number
of options
options
Can change a
limited number
of options
(Note)
None None None
Supervisor Password Supervisor None
Enter Password
Clear User Password
Supervisor Password
Enter Password
Password to
Enter Setup
User User
Supervisor or
user
Password
During Boot
Supervisor or
user
For information about Refer to
Setting user and supervisor passwords Section 4.5, page 110
The BIOS Setup program can be used to view and change the BIOS settings for the computer. The
BIOS Setup program is accessed by pressing the <F2> key after the Power-On Self-Test (POST)
memory test begins and before the operating system boot begins. The menu bar is shown below.
Maintenance Main Advanced Security Power Boot Exit
Table 58 lists the BIOS Setup program menu features.
Table 58. BIOS Setup Program Menu Bar
Maintenance Main Advanced Security Power Boot Exit
Clears
passwords and
BIS credentials
and enables
extended
configuration
mode
Allocates
resources for
hardware
components
Configures
advanced
features
available
through the
chipset
Saves or
discards
changes to
Setup
program
options
NOTE
✏
In this chapter, all examples of the BIOS Setup program menu bar include the maintenance menu;
however, the maintenance menu is displayed only when the board is in configuration mode.
Section 2.9 on page 72 tells how to put the board in configuration mode.
Table 59 lists the function keys available for menu screens.
Table 59. BIOS Setup Program Function Keys
BIOS Setup Program Function Key Description
<←> or <→> Selects a different menu screen (Moves the cursor left or right)
<↑> or <↓> Selects an item (Moves the cursor up or down)
<Tab> Selects a field (Not implemented)
<Enter> Executes command or selects the submenu
<F9> Load the default configuration values for the current menu
<F10> Save the current values and exits the BIOS Setup program
<Esc> Exits the menu
4.2 Maintenance Menu
To access this menu, select Maintenance on the menu bar at the top of the screen.
Maintenance
Extended Configuration
The menu shown in Table 60 is for clearing Setup passwords and enabling extended configuration
mode. Setup only displays this menu in configuration mode. See Section 2.9 on page 72 for
configuration mode setting information.
Main Advanced Security Power Boot Exit
Table 60. Maintenance Menu
Feature Options Description
Clear All Passwords • Yes (default)
• No
Clear BIS Credentials • Yes (default)
• No
Extended
Configuration
CPU Information No options Displays CPU Information.
CPU Stepping
Signature
CPU Microcode
Update Revision
• Default (default)
• User-Defined
No options Displays CPU’ s Stepping Signature.
No options Displays CPU’s Microcode Update Revi sion.
Clears the user and supervisor passwords.
Clears the Wired for Management Boot Integrity Service (BIS)
credentials.
Invokes the Extended Configuration submenu.
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BIOS Setup Program
4.2.1 Extended Configuration Submenu
To access this submenu, select Maintenance on the menu bar and then Extended Configuration.
Maintenance
Extended Configuration
The submenu represented by Table 61 is for setting video memory cache mode. This submenu
becomes available when User Defined is selected under Extended Configuration.
User Defined allows setting memory control and video
(default)
• User Defined
• UC (default)
(default)
• User Defined
• 2
• Auto
(default)
• 3
• 2
• Auto
(default)
• 2
• Auto
(default)
• 7
• 6
• 5
• Auto
(default)
memory cache mode. If selected here, will also display in
the Advanced Menu as: “Extended Menu:
Selects Uncacheable Speculative Write-Combining
(USWC) video memory cache mode. Full 32 byte contents
of the Write Combining buffer are written to memory as
required. Cache lookups are not performed. Both the
video driver and the application must support Write
Combining.
Selects UnCacheable (UC) video memory cache mode.
This setting identifies the video memory range as
uncacheable by the processor. Memory writes are
performed in program order. Cache lookups are not
performed. Well suited for applications not supporting
Write Combining.
Sets extended memory configuration options to
User Defined
Selects the number of clock cycles required to address a
column in memory.
Selects the number of clock cycles between addressing a
row and addressing a column.
Selects the length of time required before accessing a
new row.
To access this menu, select Main on the menu bar at the top of the screen.
Maintenance
Main
Table 62 describes the Main menu. This menu reports processor and memory information and is
for configuring the system date and system time.
Table 62. Main Menu
Feature Options Description
BIOS Version No options Displays the version of the BIOS.
Processor Type No options Displays processor type.
Processor Speed No options Displays processor speed.
System Bus Speed No options Displays the system bus speed.
Cache RAM No options Displays the size of second-level cache and whether it is
Total Memory No options Displays the total amount of RAM.
Memory Bank 0
Memory Bank 1
Memory Bank 2
Language • English (default)
Memory
Configuration
System Time Hour, minute, and
System Date Day of week
No options Displays the amount and type of RAM in the memory
• Español
• Deutsch
• Italiano
• Français
• Non-ECC
• ECC (default)
second
Month/day/year
Advanced Security Power Boot Exit
ECC-capable.
banks.
Selects the current default language used by the BIOS.
Allows the user to enable error reporting if the system and
all installed memory support ECC. If non-ECC memory is
installed, BIOS will detect and change the setting to
Non-ECC.
Specifies the current time.
Specifies the current date.
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BIOS Setup Program
4.4 Advanced Menu
To access this menu, select Advanced on the menu bar at the top of the screen.
Maintenance Main
Advanced
PCI Configuration
Boot Configuration
Peripheral Configuration
IDE Configuration
Diskette Configuration
Event Log Configuration
Video Configuration
Table 63 describes the Advanced Menu. This menu is used for setting advanced features that are
available through the chipset.
Table 63. Advanced Menu
Feature Options Description
Extended Configuration No options If
PCI Configuration Select to display
submenu
Boot Configuration Select to display
submenu
Peripheral Configuration Select to display
submenu
IDE Configuration Select to display
submenu
Diskette Configuration Select to display
submenu
Event Log Configuration Select to display
submenu
Video Configuration Select to display
submenu
Security Power Boot Exit
Used
is displayed,
Extended Configuration under the Maintenance Menu.
Configures individual PCI slot’s IRQ priority.
Configures Plug and Play and the Numlock key, and resets
configuration data.