Intel 253666-024US User Manual

Download

Intel® 64 and IA-32 Architectures

Software Developer’s Manual

Volume 2A:

Instruction Set Reference, A-M

NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual

consists of five volumes: Basic Architecture, Order Number 253665;

Instruction Set Reference A-M, Order Number 253666; Instruction Set Reference N-Z, Order Number 253667; System Programming Guide, Part 1, Order Number 253668; System Programming Guide, Part 2,

Order Number 253669. Refer to all five volumes when evaluating your design needs.

Order Number: 253666-024US

August 2007

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERT Y RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.

Intel may make changes to specifications and product descriptions at any time, without notice. Developers must not rely on the absence or characteristics of any features or instructions marked “reserved”

or “undefined.” Improper use of reserved or undefined features or instructions may cause unpre dictab le be havior or failure in developer's software code when running on an Intel processor. Intel reserves these features or instructions for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from their unauthorized use.

The Intel acterized errata are available on request.

Hyper-Threading Technology requires a computer system with an Intel Threading Technology and an HT Technology enabled chipset, BIOS and oper ating sys tem. Pe rformance will vary depending on the specific hardware and software you use. For more information, see http://www.in-

tel.com/technology/hyperthread/index.htm; including details on which processors support HT Technology.

64 architecture processors ma y conta in de sign defects o r err ors kn own as err a ta. Curr ent c har -

processor supporting Hyper-

No computer system can provide absolute security under all conditions. Intel® Trusted Ex ecution Technology requires a computer system with Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenti cate d Code Mo dule s and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group, and specific software for some uses. For more information, see http://www.intel.com/technology/security

Virtualization T echnol ogy requires a computer syste m with an enabled Intel® processor , BIOS, virtual

Intel machine monitor (VMM) and for some uses, certain platform software enabled for it. Functionality, performance or other benefits will Technology-enabled BIOS and VMM applications are currently in development.

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel (including 32-bit operation) without an Intel pending on your hardware and software configurations. Consult with your system vendor for more information.

vary depending on hardware and software configurations. Intel® Virtualization

64 architecture-enabled BIOS. Performance will vary de-

64 architecture. Processors will not operate

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Chec k with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

Intel, Pentium, Intel Xeon, Intel NetBurst, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo, Intel Core 2 Extreme, Intel Pentium D, Itanium, Intel SpeedStep, MMX, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others. Contact your local Intel sales office or your distributor to obtain the latest specifications and befo re plac ing

your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel

literature, may be obtained from:

Intel Corporation P.O. Box 5937 Denver, CO 80217-9808

or call 1-800-548-4725 or visit Intel’s website a t http://www.intel.com

ii Vol. 2A

CONTENTS

PAGE

CHAPTER 1 ABOUT THIS MANUAL

1.1 IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 OVERVIEW OF VOLUME 2A AND 2B: INSTRUCTION SET REFERENCE . . . . . . . . . . . . . . . . . . 1-2

1.3 NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.3.1 Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.3.2 Reserved Bits and Software Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.3 Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3.4 Hexadecimal and Binary Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3.5 Segmented Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3.6 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.3.7 A New Syntax for CPUID, CR, and MSR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.4 RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

CHAPTER 2 INSTRUCTION FORMAT

2.1 INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE, AND VIRTUAL-8086 MODE 2-1

2.1.1 Instruction Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1.2 Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.1.3 ModR/M and SIB Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.1.4 Displacement and Immediate Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.1.5 Addressing-Mode Encoding of ModR/M and SIB Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2 IA-32E MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.1 REX Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.1.1 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.2.1.2 More on REX Prefix Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.2.1.3 Displacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.2.1.4 Direct Memory-Offset MOVs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.2.1.5 Immediates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.2.1.6 RIP-Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.2.1.7 Default 64-Bit Operand Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.2.2 Additional Encodings for Control and Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

CHAPTER 3 INSTRUCTION SET REFERENCE, A-M

3.1 INTERPRETING THE INSTRUCTION REFERENCE PAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1 Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1.1 Opcode Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.1.1.2 Instruction Column in the Opcode Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.1.1.3 64-bit Mode Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.1.1.4 Compatibility/Legacy Mode Column in the Instruction Summary Table. . . . . . . . . . . 3-7

Vol. 2A iii

CONTENTS

PAGE

3.1.1.5 Description Column in the Instruction Summary Table. . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.1.1.6 Description Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.1.1.7 Operation Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.1.1.8 Intel® C/C++ Compiler Intrinsics Equivalents Section . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.1.1.9 Flags Affected Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.1.1.10 FPU Flags Affected Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.1.1.11 Protected Mode Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.1.1.12 Real-Address Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.1.1.13 Virtual-8086 Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.1.1.14 Floating-Point Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.1.1.15 SIMD Floating-Point Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

3.1.1.16 Compatibility Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

3.1.1.17 64-Bit Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

3.2 INSTRUCTIONS (A-M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

AAA—ASCII Adjust After Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

AAD—ASCII Adjust AX Before Division. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

AAM—ASCII Adjust AX After Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

AAS—ASCII Adjust AL After Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

ADC—Add with Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

ADD—Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30

ADDPD—Add Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . 3-33

ADDPS—Add Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . 3-36

ADDSD—Add Scalar Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . 3-39

ADDSS—Add Scalar Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . 3-42

ADDSUBPD—Packed Double-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45

ADDSUBPS—Packed Single-FP Add/Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

AND—Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53

ANDPD—Bitwise Logical AND of Packed Double-Precision Floating-Point Values . . . 3-56

ANDPS—Bitwise Logical AND of Packed Single-Precision Floating-Point Values . . . . 3-58

ANDNPD—Bitwise Logical AND NOT of Packed Double-Precision

Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision

Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62

ARPL—Adjust RPL Field of Segment Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64

BOUND—Check Array Index Against Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-66

BSF—Bit Scan Forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69

BSR—Bit Scan Reverse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71

BSWAP—Byte Swap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73

BT—Bit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75

BTC—Bit Test and Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78

BTR—Bit Test and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81

BTS—Bit Test and Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84

CALL—Call Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87

CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Dou-

bleword to Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-105

CLC—Clear Carry Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-106

CLD—Clear Direction Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107

Vol. 2A

CONTENTS

PAGE

CLFLUSH—Flush Cache Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-108

CLI — Clear Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110

CLTS—Clear Task-Switched Flag in CR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113

CMC—Complement Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115

CMOVcc—Conditional Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-116

CMP—Compare Two Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-123

CMPPD—Compare Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . 3-126

CMPPS—Compare Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . 3-131

CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands . . . . . . . . . . . . . . . 3-136

CMPSD—Compare Scalar Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . 3-142

CMPSS—Compare Scalar Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . 3-146

CMPXCHG—Compare and Exchange. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-150

CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes . . . . . . . . . . . . . . . . . . . . 3-153

COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set

EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-156

COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set

EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-159

CPUID—CPU Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-162

CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision

Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-190

CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision

Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-192

CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed

Doubleword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-195

CVTPD2PI—Convert Packed Double-Precision Floating-Point Values to Packed

Doubleword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-198

CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed

Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-201

CVTPI2PD—Convert Packed Doubleword Integers to Packed Double-Precision

Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-204

CVTPI2PS—Convert Packed Doubleword Integers to Packed Single-Precision

Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-207

CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed

Doubleword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-210

CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed

Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-213

CVTPS2PI—Convert Packed Single-Precision Floating-Point Values to Packed

Doubleword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-216

CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword

Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-219

CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar

Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-222

CVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision

Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-225

CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision

Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-228

CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar

Vol. 2A v

CONTENTS

PAGE

Double-Precision Floating-Point Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-231

CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to

Doubleword Integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-234

CVTTPD2PI—Convert with Truncation Packed Double-Precision Floating-Point

Values to Packed Doubleword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-237

CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point

Values to Packed Doubleword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-240

CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point

Values to Packed Doubleword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-243

CVTTPS2PI—Convert with Truncation Packed Single-Precision Floating-Point

Values to Packed Doubleword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-246

CVTTSD2SI—Convert with Truncation Scalar Double-Precision Floating-Point

Value to Signed Doubleword Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-249

CVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point

Value to Doubleword Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-252

CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword3-255

DAA—Decimal Adjust AL after Addition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-257

DAS—Decimal Adjust AL after Subtraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-259

DEC—Decrement by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-261

DIV—Unsigned Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-264

DIVPD—Divide Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . .3-268

DIVPS—Divide Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . .3-271

DIVSD—Divide Scalar Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . 3-274

DIVSS—Divide Scalar Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . .3-277

EMMS—Empty MMX Technology State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-280

ENTER—Make Stack Frame for Procedure Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 3-282

F2XM1—Compute 2x–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-286

FABS—Absolute Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-288

FADD/FADDP/FIADD—Add. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-290

FBLD—Load Binary Coded Decimal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-294

FBSTP—Store BCD Integer and Pop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-296

FCHS—Change Sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-299

FCLEX/FNCLEX—Clear Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-301

FCMOVcc—Floating-Point Conditional Move. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-303

FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point

Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-309

FCOS—Cosine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-312

FDECSTP—Decrement Stack-Top Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-314

FDIV/FDIVP/FIDIV—Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-316

FDIVR/FDIVRP/FIDIVR—Reverse Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-320

FFREE—Free Floating-Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-324

FICOM/FICOMP—Compare Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-325

FILD—Load Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-328

FINCSTP—Increment Stack-Top Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-330

FINIT/FNINIT—Initialize Floating-Point Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-332

FIST/FISTP—Store Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-334

FISTTP—Store Integer with Truncation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-338

Vol. 2A

CONTENTS

PAGE

FLD—Load Floating Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-341

FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant . . . . . . . . . . . 3-344

FLDCW—Load x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-346

FLDENV—Load x87 FPU Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-348

FMUL/FMULP/FIMUL—Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-351

FNOP—No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-355

FPATAN—Partial Arctangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-356

FPREM—Partial Remainder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-359

FPREM1—Partial Remainder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-362

FPTAN—Partial Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-365

FRNDINT—Round to Integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-368

FRSTOR—Restore x87 FPU State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-370

FSAVE/FNSAVE—Store x87 FPU State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-373

FSCALE—Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-377

FSIN—Sine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-379

FSINCOS—Sine and Cosine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-381

FSQRT—Square Root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-384

FST/FSTP—Store Floating Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-386

FSTCW/FNSTCW—Store x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-389

FSTENV/FNSTENV—Store x87 FPU Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-392

FSTSW/FNSTSW—Store x87 FPU Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-395

FSUB/FSUBP/FISUB—Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-398

FSUBR/FSUBRP/FISUBR—Reverse Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-402

FTST—TEST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-406

FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point Values . . . . . . . . . 3-408

FXAM—ExamineModR/M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-411

FXCH—Exchange Register Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-413

FXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR State. . . . . . . . . . . . . . . . . . . . 3-415

FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 State . . . . . . . . . . . . . . . . 3-418

FXTRACT—Extract Exponent and Significand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-429

FYL2X—Compute y * log2x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-431

FYL2XP1—Compute y * log2(x +1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-433

HADDPD—Packed Double-FP Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-435

HADDPS—Packed Single-FP Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-439

HLT—Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-443

HSUBPD—Packed Double-FP Horizontal Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-445

HSUBPS—Packed Single-FP Horizontal Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-449

IDIV—Signed Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-453

IMUL—Signed Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-457

IN—Input from Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-462

INC—Increment by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-464

INS/INSB/INSW/INSD—Input from Port to String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-467

INT n/INTO/INT 3—Call to Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-471

INVD—Invalidate Internal Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-486

INVLPG—Invalidate TLB Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-488

IRET/IRETD—Interrupt Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-490

Jcc—Jump if Condition Is Met . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-501

Vol. 2A vii

CONTENTS

PAGE

JMP—Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-508

LAHF—Load Status Flags into AH Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-518

LAR—Load Access Rights Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-520

LDDQU—Load Unaligned Integer 128 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-524

LDMXCSR—Load MXCSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-527

LDS/LES/LFS/LGS/LSS—Load Far Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-529

LEA—Load Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-535

LEAVE—High Level Procedure Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-538

LFENCE—Load Fence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-540

LGDT/LIDT—Load Global/Interrupt Descriptor Table Register . . . . . . . . . . . . . . . . . . . .3-541

LLDT—Load Local Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-544

LMSW—Load Machine Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-547

LOCK—Assert LOCK# Signal Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-549

LODS/LODSB/LODSW/LODSD/LODSQ—Load String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-551

LOOP/LOOPcc—Loop According to ECX Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-555

LSL—Load Segment Limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-558

LTR—Load Task Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-562

MASKMOVDQU—Store Selected Bytes of Double Quadword . . . . . . . . . . . . . . . . . . . . . 3-565

MASKMOVQ—Store Selected Bytes of Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-568

MAXPD—Return Maximum Packed Double-Precision Floating-Point Values . . . . . . .3-571

MAXPS—Return Maximum Packed Single-Precision Floating-Point Values . . . . . . . . 3-574

MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value . . . . . . . . . 3-577

MAXSS—Return Maximum Scalar Single-Precision Floating-Point Value . . . . . . . . . .3-580

MFENCE—Memory Fence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-583

MINPD—Return Minimum Packed Double-Precision Floating-Point Values. . . . . . . . . 3-584

MINPS—Return Minimum Packed Single-Precision Floating-Point Values. . . . . . . . . . 3-587

MINSD—Return Minimum Scalar Double-Precision Floating-Point Value . . . . . . . . . . .3-590

MINSS—Return Minimum Scalar Single-Precision Floating-Point Value . . . . . . . . . . . .3-593

MONITOR—Set Up Monitor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-596

MOV—Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-599

MOV—Move to/from Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-605

MOV—Move to/from Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-608

MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values . . . . . . . . . 3-610

MOVAPS—Move Aligned Packed Single-Precision Floating-Point Values . . . . . . . . . . 3-613

MOVD/MOVQ—Move Doubleword/Move Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-616

MOVDDUP—Move One Double-FP and Duplicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-620

MOVDQA—Move Aligned Double Quadword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-623

MOVDQU—Move Unaligned Double Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-625

MOVDQ2Q—Move Quadword from XMM to MMX Technology Register . . . . . . . . . . . 3-628

MOVHLPS— Move Packed Single-Precision Floating-Point Values High to Low . . . .3-630

MOVHPD—Move High Packed Double-Precision Floating-Point Value . . . . . . . . . . . . .3-632

MOVHPS—Move High Packed Single-Precision Floating-Point Values . . . . . . . . . . . . .3-635

MOVLHPS—Move Packed Single-Precision Floating-Point Values Low to High. . . . . 3-638

MOVLPD—Move Low Packed Double-Precision Floating-Point Value. . . . . . . . . . . . . . 3-640

MOVLPS—Move Low Packed Single-Precision Floating-Point Values. . . . . . . . . . . . . . 3-642

MOVMSKPD—Extract Packed Double-Precision Floating-Point Sign Mask . . . . . . . . . 3-645

MOVMSKPS—Extract Packed Single-Precision Floating-Point Sign Mask . . . . . . . . . . 3-647

viii

Vol. 2A

CONTENTS

PAGE

MOVNTDQ—Store Double Quadword Using Non-Temporal Hint . . . . . . . . . . . . . . . . . 3-649

MOVNTI—Store Doubleword Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . . . 3-652

MOVNTPD—Store Packed Double-Precision Floating-Point Values Using

Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-654

MOVNTPS—Store Packed Single-Precision Floating-Point Values Using

Non-Temporal Hint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-657

MOVNTQ—Store of Quadword Using Non-Temporal Hint. . . . . . . . . . . . . . . . . . . . . . . . 3-660

MOVQ—Move Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-663

MOVQ2DQ—Move Quadword from MMX Technology to XMM Register. . . . . . . . . . . 3-666

MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String. . . . . . . 3-668

MOVSD—Move Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . 3-673

MOVSHDUP—Move Packed Single-FP High and Duplicate . . . . . . . . . . . . . . . . . . . . . . . 3-676

MOVSLDUP—Move Packed Single-FP Low and Duplicate . . . . . . . . . . . . . . . . . . . . . . . . 3-679

MOVSS—Move Scalar Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . 3-682

MOVSX/MOVSXD—Move with Sign-Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-685

MOVUPD—Move Unaligned Packed Double-Precision Floating-Point Values . . . . . . 3-687

MOVUPS—Move Unaligned Packed Single-Precision Floating-Point Values . . . . . . . 3-690

MOVZX—Move with Zero-Extend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-693

MUL—Unsigned Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-695

MULPD—Multiply Packed Double-Precision Floating-Point Values. . . . . . . . . . . . . . . . 3-698

MULPS—Multiply Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . 3-701

MULSD—Multiply Scalar Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . 3-704

MULSS—Multiply Scalar Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . 3-707

MWAIT—Monitor Wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-710

CHAPTER 4 INSTRUCTION SET REFERENCE, N-Z

4.1 INSTRUCTIONS (N-Z). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

NEG—Two's Complement Negation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

NOP—No Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

NOT—One's Complement Negation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

OR—Logical Inclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

ORPD—Bitwise Logical OR of Double-Precision Floating-Point Values . . . . . . . . . . . . . .4-12

ORPS—Bitwise Logical OR of Single-Precision Floating-Point Values . . . . . . . . . . . . . . .4-14

OUT—Output to Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-16

OUTS/OUTSB/OUTSW/OUTSD—Output String to Port . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-18

PABSB/PABSW/PABSD — Packed Absolute Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-23

PACKSSWB/PACKSSDW—Pack with Signed Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-27

PACKUSWB—Pack with Unsigned Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-32

PADDB/PADDW/PADDD—Add Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-36

PADDQ—Add Packed Quadword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-40

PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation. . . . . . . . . . .4-43

PADDUSB/PADDUSW—Add Packed Unsigned Integers with Unsigned Saturation . . .4-47

PALIGNR — Packed Align Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-51

PAND—Logical AND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-54

PANDN—Logical AND NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-57

PAUSE—Spin Loop Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-60

Vol. 2A ix

CONTENTS

PAGE

PAVGB/PAVGW—Average Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61

PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal. . . . . . . . . . . . . . . . 4-64

PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than .4-

PEXTRW—Extract Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-73

PHADDW/PHADDD — Packed Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-76

PHADDSW — Packed Horizontal Add and Saturate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79

PHSUBW/PHSUBD — Packed Horizontal Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82

PHSUBSW — Packed Horizontal Subtract and Saturate . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85

PINSRW—Insert Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-88

PMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes. . . . . . . . . . . . . 4-91

PMADDWD—Multiply and Add Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94

PMAXSW—Maximum of Packed Signed Word Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-98

PMAXUB—Maximum of Packed Unsigned Byte Integers . . . . . . . . . . . . . . . . . . . . . . . . .4-101

PMINSW—Minimum of Packed Signed Word Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-104

PMINUB—Minimum of Packed Unsigned Byte Integers . . . . . . . . . . . . . . . . . . . . . . . . . . 4-107

PMOVMSKB—Move Byte Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-110

PMULHRSW — Packed Multiply High with Round and Scale . . . . . . . . . . . . . . . . . . . . . . 4-113

PMULHUW—Multiply Packed Unsigned Integers and Store High Result . . . . . . . . . . .4-116

PMULHW—Multiply Packed Signed Integers and Store High Result . . . . . . . . . . . . . . .4-120

PMULLW—Multiply Packed Signed Integers and Store Low Result. . . . . . . . . . . . . . . . 4-123

PMULUDQ—Multiply Packed Unsigned Doubleword Integers . . . . . . . . . . . . . . . . . . . . . 4-127

POP—Pop a Value from the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-130

POPA/POPAD—Pop All General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-137

POPF/POPFD/POPFQ—Pop Stack into EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . 4-139

POR—Bitwise Logical OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-143

PREFETCHh—Prefetch Data Into Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-146

PSADBW—Compute Sum of Absolute Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-148

PSHUFB — Packed Shuffle Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-152

PSHUFD—Shuffle Packed Doublewords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-156

PSHUFHW—Shuffle Packed High Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-159

PSHUFLW—Shuffle Packed Low Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-162

PSHUFW—Shuffle Packed Words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-165

PSIGNB/PSIGNW/PSIGND — Packed SIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-168

PSLLDQ—Shift Double Quadword Left Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-173

PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical. . . . . . . . . . . . . . . . . . . . . . . . . . .4-175

PSRAW/PSRAD—Shift Packed Data Right Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-180

PSRLDQ—Shift Double Quadword Right Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-185

PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical. . . . . . . . . . . . . . . . . . . . . . . . . 4-187

PSUBB/PSUBW/PSUBD—Subtract Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-192

PSUBQ—Subtract Packed Quadword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-196

PSUBSB/PSUBSW—Subtract Packed Signed Integers with Signed Saturation . . . . .4-199

PSUBUSB/PSUBUSW—Subtract Packed Unsigned Integers

with Unsigned Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-203

PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data . . . . 4-207

PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—

Unpack Low Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-212

Vol. 2A

CONTENTS

PAGE

PUSH—Push Word, Doubleword or Quadword Onto the Stack . . . . . . . . . . . . . . . . . . . 4-217

PUSHA/PUSHAD—Push All General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 4-222

PUSHF/PUSHFD—Push EFLAGS Register onto the Stack . . . . . . . . . . . . . . . . . . . . . . . . 4-225

PXOR—Logical Exclusive OR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-228

RCL/RCR/ROL/ROR-—Rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-231

RCPPS—Compute Reciprocals of Packed Single-Precision Floating-Point Values . . 4-238

RCPSS—Compute Reciprocal of Scalar Single-Precision Floating-Point Values . . . . 4-241

RDMSR—Read from Model Specific Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-244

RDPMC—Read Performance-Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-246

RDTSC—Read Time-Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-251

REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix . . . . . . . . . . . . . . . 4-253

RET—Return from Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-258

RSM—Resume from System Management Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-270

RSQRTPS—Compute Reciprocals of Square Roots of Packed

Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-272

RSQRTSS—Compute Reciprocal of Square Root of Scalar

Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-275

SAHF—Store AH into Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-278

SAL/SAR/SHL/SHR—Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-280

SBB—Integer Subtraction with Borrow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-287

SCAS/SCASB/SCASW/SCASD—Scan String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-291

SETcc—Set Byte on Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-296

SFENCE—Store Fence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-301

SGDT—Store Global Descriptor Table Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-302

SHLD—Double Precision Shift Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-305

SHRD—Double Precision Shift Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-308

SHUFPD—Shuffle Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . 4-311

SHUFPS—Shuffle Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . 4-314

SIDT—Store Interrupt Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-317

SLDT—Store Local Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-320

SMSW—Store Machine Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-322

SQRTPS—Compute Square Roots of Packed Single-Precision

Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-328

SQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point Value. 4-331 SQRTSS—Compute Square Root of Scalar Single-Precision Floating-Point Value. . 4-334

STC—Set Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-337

STD—Set Direction Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-338

STI—Set Interrupt Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-339

STMXCSR—Store MXCSR Register State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-342

STOS/STOSB/STOSW/STOSD/STOSQ—Store String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-344

STR—Store Task Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-348

SUB—Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-350

SUBPD—Subtract Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . 4-353

SUBPS—Subtract Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . 4-356

SUBSD—Subtract Scalar Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . 4-359

SUBSS—Subtract Scalar Single-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . 4-362

SWAPGS—Swap GS Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-365

Vol. 2A xi

CONTENTS

PAGE

SYSCALL—Fast System Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-367

SYSENTER—Fast System Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-369

SYSEXIT—Fast Return from Fast System Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-373

SYSRET—Return From Fast System Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-377

TEST—Logical Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-379

UCOMISD—Unordered Compare Scalar Double-Precision Floating-Point Values and Set

EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-382

UCOMISS—Unordered Compare Scalar Single-Precision Floating-Point Values and Set

EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-385

UD2—Undefined Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-388

UNPCKHPD—Unpack and Interleave High Packed Double-Precision

Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-389

UNPCKHPS—Unpack and Interleave High Packed Single-Precision

Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-392

UNPCKLPD—Unpack and Interleave Low Packed Double-Precision

Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-395

UNPCKLPS—Unpack and Interleave Low Packed Single-Precision

Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-398

VERR/VERW—Verify a Segment for Reading or Writing . . . . . . . . . . . . . . . . . . . . . . . . . 4-401

WAIT/FWAIT—Wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-404

WBINVD—Write Back and Invalidate Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-406

WRMSR—Write to Model Specific Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-408

XADD—Exchange and Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-410

XCHG—Exchange Register/Memory with Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-413

XLAT/XLATB—Table Look-up Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-416

XOR—Logical Exclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-418

XORPD—Bitwise Logical XOR for Double-Precision Floating-Point Values. . . . . . . . . 4-421

XORPS—Bitwise Logical XOR for Single-Precision Floating-Point Values. . . . . . . . . . 4-423

CHAPTER 5 VMX INSTRUCTION REFERENCE

5.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.3 VMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

VMCALL—Call to VM Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

VMCLEAR—Clear Virtual-Machine Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

VMLAUNCH/VMRESUME—Launch/Resume Virtual Machine . . . . . . . . . . . . . . . . . . . . . . . 5-10

VMPTRLD—Load Pointer to Virtual-Machine Control Structure. . . . . . . . . . . . . . . . . . . . 5-13

VMPTRST—Store Pointer to Virtual-Machine Control Structure . . . . . . . . . . . . . . . . . . . 5-16

VMREAD—Read Field from Virtual-Machine Control Structure . . . . . . . . . . . . . . . . . . . . 5-18

VMRESUME—Resume Virtual Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21

VMWRITE—Write Field to Virtual-Machine Control Structure . . . . . . . . . . . . . . . . . . . . . . 5-22

VMXOFF—Leave VMX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25

VMXON—Enter VMX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27

Vol. 2A

xii

CONTENTS

PAGE

CHAPTER 6 SAFER MODE EXTENSIONS REFERENCE

6.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

6.2 SMX FUNCTIONALITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

6.2.1 Detecting and Enabling SMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

6.2.2 SMX Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

6.2.2.1 GETSEC[CAPABILITIES] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

6.2.2.2 GETSEC[ENTERACCS] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

6.2.2.3 GETSEC[EXITAC]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

6.2.2.4 GETSEC[SENTER] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

6.2.2.5 GETSEC[SEXIT] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

6.2.2.6 GETSEC[PARAMETERS] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

6.2.2.7 GETSEC[SMCTRL]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

6.2.2.8 GETSEC[WAKEUP] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

6.2.3 Measured Environment and SMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

6.3 GETSEC LEAF FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

GETSEC[CAPABILITIES] - Report the SMX Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

GETSEC[ENTERACCS] - Execute Authenticated Chipset Code . . . . . . . . . . . . . . . . . . . . . .5-12

GETSEC[EXITAC]—Exit Authenticated Code Execution Mode . . . . . . . . . . . . . . . . . . . . . .5-23

GETSEC[SENTER]—Enter a measured environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-27

GETSEC[SEXIT]—Exit measured environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-39

GETSEC[PARAMETERS]—Report the SMX parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-43

GETSEC[SMCTRL]—SMX mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-48

GETSEC[WAKEUP]—Wake up sleeping processors in measured environment . . . . . . .5-52

APPENDIX A OPCODE MAP

A.1 USING OPCODE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.2 KEY TO ABBREVIATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

A.2.1 Codes for Addressing Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

A.2.2 Codes for Operand Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

A.2.3 Register Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4

A.2.4 Opcode Look-up Examples for One, Two,

and Three-Byte OpcodesA-4

A.2.4.1 One-Byte Opcode Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4

A.2.4.2 Two-Byte Opcode Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5

A.2.4.3 Three-Byte Opcode Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6

A.2.5 Superscripts Utilized in Opcode Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7

A.3 ONE, TWO, AND THREE-BYTE OPCODE MAPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8

A.4 OPCODE EXTENSIONS FOR ONE-BYTE AND TWO-BYTE OPCODES . . . . . . . . . . . . . . . . . . . A-19

A.4.1 Opcode Look-up Examples Using Opcode Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-19

A.4.2 Opcode Extension Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-20

A.5 ESCAPE OPCODE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-22

A.5.1 Opcode Look-up Examples for Escape Instruction Opcodes . . . . . . . . . . . . . . . . . . . . . . . .A-22

A.5.2 Escape Opcode Instruction Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-22

A.5.2.1 Escape Opcodes with D8 as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-23

A.5.2.2 Escape Opcodes with D9 as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-24

Vol. 2A xiii

CONTENTS

PAGE

A.5.2.3 Escape Opcodes with DA as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25

A.5.2.4 Escape Opcodes with DB as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26

A.5.2.5 Escape Opcodes with DC as First Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-27

A.5.2.6 Escape Opcodes with DD as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-28

A.5.2.7 Escape Opcodes with DE as First Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-29

A.5.2.8 Escape Opcodes with DF As First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-30

APPENDIX B INSTRUCTION FORMATS AND ENCODINGS

B.1 MACHINE INSTRUCTION FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

B.1.1 Legacy Prefixes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

B.1.2 REX Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

B.1.3 Opcode Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

B.1.4 Special Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

B.1.4.1 Reg Field (reg) for Non-64-Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

B.1.4.2 Reg Field (reg) for 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4

B.1.4.3 Encoding of Operand Size (w) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5

B.1.4.4 Sign-Extend (s) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5

B.1.4.5 Segment Register (sreg) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6

B.1.4.6 Special-Purpose Register (eee) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6

B.1.4.7 Condition Test (tttn) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7

B.1.4.8 Direction (d) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8

B.1.5 Other Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9

B.2 GENERAL-PURPOSE INSTRUCTION FORMATS AND ENCODINGS

FOR NON-64-BIT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9

B.2.1 General Purpose Instruction Formats and Encodings for 64-Bit Mode . . . . . . . . . . . . . B-24

B.3 PENTIUM

PROCESSOR FAMILY INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . B-53

B.4 64-BIT MODE INSTRUCTION ENCODINGS FOR SIMD INSTRUCTION EXTENSIONS . . . . . . B-54

B.5 MMX INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-54

B.5.1 Granularity Field (gg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-54

B.5.2 MMX Technology and General-Purpose Register Fields (mmxreg and reg) . . . . . . . . . B-55

B.5.3 MMX Instruction Formats and Encodings Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-55

B.6 P6 FAMILY INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-58

B.7 SSE INSTRUCTION FORMATS AND ENCODINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-59

B.8 SSE2 INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-68

B.8.1 Granularity Field (gg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-68

B.9 SSE3 FORMATS AND ENCODINGS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-85

B.10 SSSE3 FORMATS AND ENCODING TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-87

B.11 SPECIAL ENCODINGS FOR 64-BIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-91

B.12 FLOATING-POINT INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . B-95

B.13 VMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-101

B.14 SMX INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-103

APPENDIX C INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS

C.1 SIMPLE INTRINSICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2

C.2 COMPOSITE INTRINSICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-14

Vol. 2A

xiv

CONTENTS

PAGE

FIGURES

Figure 1-1. Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Figure 2-1. Intel 64 and IA-32 Architectures Instruction Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Figure 2-2. Table Interpretation of ModR/M Byte (C8H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Figure 2-3. Prefix Ordering in 64-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Figure 2-4. Memory Addressing Without an SIB Byte; REX.X Not Used . . . . . . . . . . . . . . . . . . . . .2-11

Figure 2-5. Register-Register Addressing (No Memory Operand); REX.X Not Used . . . . . . . . . .2-11

Figure 2-6. Memory Addressing With a SIB Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12

Figure 2-7. Register Operand Coded in Opcode Byte; REX.X & REX.R Not Used . . . . . . . . . . . . .2-12

Figure 3-1. Bit Offset for BIT[RAX, 21] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10

Figure 3-2. Memory Bit Indexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11

Figure 3-3. ADDSUBPD—Packed Double-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-45

Figure 3-4. ADDSUBPS—Packed Single-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-49

Figure 3-5. Version Information Returned by CPUID in EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-170

Figure 3-6. Feature Information Returned in the ECX Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3-172

Figure 3-7. Feature Information Returned in the EDX Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3-174

Figure 3-8. Determination of Support for the Processor Brand String . . . . . . . . . . . . . . . . . . . . 3-182

Figure 3-9. Algorithm for Extracting Maximum Processor Frequency . . . . . . . . . . . . . . . . . . . . 3-184

Figure 3-10. HADDPD—Packed Double-FP Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-435

Figure 3-11. HADDPS—Packed Single-FP Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-439

Figure 3-12. HSUBPD—Packed Double-FP Horizontal Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-445

Figure 3-13. HSUBPS—Packed Single-FP Horizontal Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-450

Figure 3-14. MOVDDUP—Move One Double-FP and Duplicate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-620

Figure 3-15. MOVSHDUP—Move Packed Single-FP High and Duplicate . . . . . . . . . . . . . . . . . . . . 3-676

Figure 3-16. MOVSLDUP—Move Packed Single-FP Low and Duplicate . . . . . . . . . . . . . . . . . . . . . 3-679

Figure 4-1. Operation of the PACKSSDW Instruction Using 64-bit Operands . . . . . . . . . . . . . . . .4-27

Figure 4-2. PMADDWD Execution Model Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . .4-95

Figure 4-3. PMULHUW and PMULHW Instruction Operation Using 64-bit Operands . . . . . . . 4-116

Figure 4-4. PMULLU Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . 4-123

Figure 4-5. PSADBW Instruction Operation Using 64-bit Operands. . . . . . . . . . . . . . . . . . . . . . . 4-149

Figure 4-6. PSHUB with 64-Bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-153

Figure 4-7. PSHUFD Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-156

Figure 4-8. PSLLW, PSLLD, and PSLLQ Instruction Operation Using 64-bit Operand . . . . . . . 4-176

Figure 4-9. PSRAW and PSRAD Instruction Operation Using a 64-bit Operand . . . . . . . . . . . . 4-181

Figure 4-10. PSRLW, PSRLD, and PSRLQ Instruction Operation Using 64-bit Operand . . . . . . 4-188

Figure 4-11. PUNPCKHBW Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . 4-208

Figure 4-12. PUNPCKLBW Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . . 4-212

Figure 4-13. SHUFPD Shuffle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-311

Figure 4-14. SHUFPS Shuffle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-314

Figure 4-15. UNPCKHPD Instruction High Unpack and Interleave Operation . . . . . . . . . . . . . . . 4-389

Figure 4-16. UNPCKHPS Instruction High Unpack and Interleave Operation . . . . . . . . . . . . . . . 4-392

Figure 4-17. UNPCKLPD Instruction Low Unpack and Interleave Operation . . . . . . . . . . . . . . . . 4-395

Figure 4-18. UNPCKLPS Instruction Low Unpack and Interleave Operation . . . . . . . . . . . . . . . . 4-398

Figure A-1. ModR/M Byte nnn Field (Bits 5, 4, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-19

Figure B-1. General Machine Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Vol. 2A xv

CONTENTS

PAGE

TABLES

Table 2-1. 16-Bit Addressing Forms with the ModR/M Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Table 2-2. 32-Bit Addressing Forms with the ModR/M Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Table 2-3. 32-Bit Addressing Forms with the SIB Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Table 2-4. REX Prefix Fields [BITS: 0100WRXB]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Table 2-5. Special Cases of REX Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

Table 2-6. Direct Memory Offset Form of MOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Table 2-7. RIP-Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

Table 3-1. Register Codes Associated With +rb, +rw, +rd, +ro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Table 3-2. Range of Bit Positions Specified by Bit Offset Operands . . . . . . . . . . . . . . . . . . . . . . 3-11

Table 3-3. Intel 64 and IA-32 General Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

Table 3-5. SIMD Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

Table 3-4. x87 FPU Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

Table 3-6. Decision Table for CLI Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-110

Table 3-7. Comparison Predicate for CMPPD and CMPPS Instructions. . . . . . . . . . . . . . . . . . . . 3-126

Table 3-8. Pseudo-Op and CMPPD Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-127

Table 3-9. Pseudo-Ops and CMPPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-132

Table 3-10. Pseudo-Ops and CMPSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-142

Table 3-11. Pseudo-Ops and CMPSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-147

Table 3-12. Information Returned by CPUID Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163

Table 3-13. Highest CPUID Source Operand for Intel 64 and IA-32 Processors . . . . . . . . . . . .3-169

Table 3-14. Processor Type Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-170

Table 3-15. Feature Information Returned in the ECX Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-173

Table 3-16. More on Feature Information Returned in the EDX Register . . . . . . . . . . . . . . . . . .3-175

Table 3-17. Encoding of Cache and TLB Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-178

Table 3-18. Processor Brand String Returned with Pentium 4 Processor. . . . . . . . . . . . . . . . . . 3-183

Table 3-19. Mapping of Brand Indices; and

Intel 64 and IA-32 Processor Brand Strings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-185

Table 3-20. DIV Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-265

Table 3-21. Results Obtained from F2XM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-286

Table 3-22. Results Obtained from FABS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-288

Table 3-23. FADD/FADDP/FIADD Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-291

Table 3-24. FBSTP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-296

Table 3-25. FCHS Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-299

Table 3-26. FCOM/FCOMP/FCOMPP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-305

Table 3-27. FCOMI/FCOMIP/ FUCOMI/FUCOMIP Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-309

Table 3-28. FCOS Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-312

Table 3-29. FDIV/FDIVP/FIDIV Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-317

Table 3-30. FDIVR/FDIVRP/FIDIVR Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-321

Table 3-31. FICOM/FICOMP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-325

Table 3-32. FIST/FISTP Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-334

Table 3-33. FISTTP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-338

Table 3-34. FMUL/FMULP/FIMUL Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-352

Table 3-35. FPATAN Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-357

Table 3-36. FPREM Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-359

Table 3-37. FPREM1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-362

xvi

Vol. 2A

CONTENTS

PAGE

Table 3-38. FPTAN Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-365

Table 3-39. FSCALE Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-377

Table 3-40. FSIN Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-379

Table 3-41. FSINCOS Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-381

Table 3-42. FSQRT Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-384

Table 3-43. FSUB/FSUBP/FISUB Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-399

Table 3-44. FSUBR/FSUBRP/FISUBR Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-403

Table 3-45. FTST Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-406

Table 3-46. FUCOM/FUCOMP/FUCOMPP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-408

Table 3-47. FXAM Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-411

Table 3-48. Non-64-bit-Mode Layout of FXSAVE and FXRSTOR

Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-418

Table 3-49. Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-420

Table 3-50. Recreating FSAVE Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-422

Table 3-51. Layout of the 64-bit-mode FXSAVE Map

with Promoted OperandSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-423

Table 3-52. Layout of the 64-bit-mode FXSAVE Map with

Default OperandSize. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-424

Table 3-53. FYL2X Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-431

Table 3-54. FYL2XP1 Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-433

Table 3-55. IDIV Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-454

Table 3-56. Decision Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-472

Table 3-57. Segment and Gate Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-521

Table 3-58. Non-64-bit Mode LEA Operation with Address and Operand Size Attributes . . 3-535

Table 3-59. 64-bit Mode LEA Operation with Address and Operand Size Attributes . . . . . . . 3-536

Table 3-60. Segment and Gate Descriptor Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-559

Table 3-61. MUL Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-695

Table 3-62. MWAIT Extension Register (ECX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-711

Table 3-63. MWAIT Hints Register (EAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-712

Table 4-1. Recommended Multi-Byte Sequence of NOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Table 4-2. Valid General and Special Purpose Performance Counter Index Range

for RDPMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-247

Table 4-3. Repeat Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-256

Table 4-4. Decision Table for STI Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-339

Table 4-5. SWAPGS Operation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-365

Table 4-6. MSRs Used By the SYSENTER and SYSEXIT Instructions . . . . . . . . . . . . . . . . . . . . . 4-369

Table 6-1. Layout of IA32_FEATURE_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Table 6-2. GETSEC Leaf Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

Table 6-3. GETSEC Capability Result Encoding (EBX = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Table 6-4. Register State Initialization after GETSEC[ENTERACCS] . . . . . . . . . . . . . . . . . . . . . . . .5-15

Table 6-5. IA32_MISC_ENALBES MSR Initialization by ENTERACCS and SENTER . . . . . . . . . . .5-17

Table 6-6. Register State Initialization after GETSEC[SENTER] and GETSEC[WAKEUP] . . . . .5-31

Table 6-7. SMX Reporting Parameters Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-43

Table 6-8. External Memory Types Using Parameter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-45

Table 6-9. Default Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-46

Table 6-10. Supported Actions for GETSEC[SMCTRL(0)] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-49

Table 6-11. RLP MVMM JOIN Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-52

Vol. 2A xvii

CONTENTS

PAGE

Table A-1. Superscripts Utilized in Opcode Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7

Table A-2. One-byte Opcode Map: (00H — F7H) *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9

Table A-3. Two-byte Opcode Map: 00H — 77H (First Byte is 0FH) * . . . . . . . . . . . . . . . . . . . . . . A-11

Table A-4. Three-byte Opcode Map: 00H — F7H (First Two Bytes are 0F 38H) * . . . . . . . . . . A-15

Table A-5. Three-byte Opcode Map: 00H — F7H (First two bytes are 0F 3AH) *. . . . . . . . . . . A-17

Table A-6. Opcode Extensions for One- and Two-byte Opcodes by Group Number * . . . . . . . A-20

Table A-7. D8 Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . A-23

Table A-8. D8 Opcode Map When ModR/M Byte is Outside 00H to BFH *. . . . . . . . . . . . . . . . . . A-23

Table A-9. D9 Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . A-24

Table A-10. D9 Opcode Map When ModR/M Byte is Outside 00H to BFH *. . . . . . . . . . . . . . . . . . A-24

Table A-11. DA Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . A-25

Table A-12. DA Opcode Map When ModR/M Byte is Outside 00H to BFH *. . . . . . . . . . . . . . . . . . A-25

Table A-13. DB Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . A-26

Table A-14. DB Opcode Map When ModR/M Byte is Outside 00H to BFH *. . . . . . . . . . . . . . . . . . A-26

Table A-15. DC Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . A-27

Table A-16. DC Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . A-27

Table A-17. DD Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . A-28

Table A-18. DD Opcode Map When ModR/M Byte is Outside 00H to BFH *. . . . . . . . . . . . . . . . . . A-28

Table A-19. DE Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . A-29

Table A-20. DE Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . A-29

Table A-21. DF Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . A-30

Table A-22. DF Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . A-30

Table B-1. Special Fields Within Instruction Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

Table B-2. Encoding of reg Field When w Field is Not Present in Instruction. . . . . . . . . . . . . . . . B-3

Table B-4. Encoding of reg Field When w Field is Not Present in Instruction. . . . . . . . . . . . . . . . B-4

Table B-3. Encoding of reg Field When w Field is Present in Instruction. . . . . . . . . . . . . . . . . . . . B-4

Table B-5. Encoding of reg Field When w Field is Present in Instruction. . . . . . . . . . . . . . . . . . . . B-5

Table B-6. Encoding of Operand Size (w) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5

Table B-7. Encoding of Sign-Extend (s) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6

Table B-8. Encoding of the Segment Register (sreg) Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6

Table B-9. Encoding of Special-Purpose Register (eee) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7

Table B-11. Encoding of Operation Direction (d) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8

Table B-10. Encoding of Conditional Test (tttn) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8

Table B-12. Notes on Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9

Table B-13. General Purpose Instruction Formats and Encodings

for Non-64-Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9

Table B-14. Special Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24

Table B-15. General Purpose Instruction Formats and Encodings

for 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24

Table B-16. Pentium Processor Family Instruction Formats and Encodings,

Non-64-Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-53

Table B-17. Pentium Processor Family Instruction Formats and Encodings, 64-Bit Mode . . . . B-53

Table B-18. Encoding of Granularity of Data Field (gg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-54

Table B-19. MMX Instruction Formats and Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-55

Table B-20. Formats and Encodings of P6 Family Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-58

Table B-21. Formats and Encodings of SSE Floating-Point Instructions. . . . . . . . . . . . . . . . . . . . . B-60

Table B-22. Formats and Encodings of SSE Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . B-66

xviii

Vol. 2A

CONTENTS

PAGE

Table B-23. Format and Encoding of SSE Cacheability & Memory Ordering Instructions. . . . . .B-67

Table B-24. Encoding of Granularity of Data Field (gg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-68

Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions . . . . . . . . . . . . . . . . . . . .B-69

Table B-26. Formats and Encodings of SSE2 Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .B-77

Table B-27. Format and Encoding of SSE2 Cacheability Instructions . . . . . . . . . . . . . . . . . . . . . . . .B-84

Table B-28. Formats and Encodings of SSE3 Floating-Point Instructions . . . . . . . . . . . . . . . . . . . .B-85

Table B-29. Formats and Encodings for SSE3 Event Management Instructions . . . . . . . . . . . . . .B-86

Table B-30. Formats and Encodings for SSE3 Integer and Move Instructions. . . . . . . . . . . . . . . .B-86

Table B-31. Formats and Encodings for SSSE3 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-87

Table B-32. Special Case Instructions Promoted Using REX.W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-91

Table B-33. General Floating-Point Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-95

Table B-34. Floating-Point Instruction Formats and Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-96

Table B-35. Encodings for VMX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-101

Table B-36. Encodings for SMX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-103

Table C-1. Simple Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3

Table C-2. Composite Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-14

Vol. 2A xix

CONTENTS

PAGE

Vol. 2A

CHAPTER 1

ABOUT THIS MANUAL

The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B: Instruction Set Reference (order numbers 253666 and 253667) are part of

a set that describes the architecture and programming environment of all Intel 64 and IA-32 architecture processors. Other volumes in this set are:

• The Intel

Basic Architecture (Order Number 253665).

• The Intel

3A & 3B: System Programming Guide (order numbers 253668 and 253669).

The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, describes the basic architecture and programming environment of Intel 64 and IA-32 processors. The Intel Volumes 2A & 2B, describe the instruction set of the processor and the opcode structure. These volumes apply to application programmers and to programmers who write operating system s or executiv es. The Intel ware Developer’s Manual, Volumes 3A & 3B, describe the operating-system support environment of Intel 64 and IA-32 processors. These volumes target operatingsystem and BIOS designers. In addition, the Intel ware Developer’s Manual, Volume 3B, addresses the programming environment for classes of software that host operating systems.

64 and IA-32 Architectures Software Developer’s Manual, Volume 1:

64 and IA-32 Architectures Software Developer’s Manual, Volumes

64 and IA-32 Architectures Software Developer’s Manual,

64 and IA-32 Architectures Soft-

1.1 IA-32 PROCESSORS COVERED IN THIS MANUAL

This manual set includes information pertaining primarily to the most recent Intel 64 and IA-32 processors, which include:

• Pentium

processors

• P6 family processors

• Pentium

• Intel

• Pentium

• 64-bit Intel

• Intel

• Dual-Core Intel

4 processors

M processors

Xeon® processors

D processors

processor Extreme Editions

Xeon® processors

Core™ Duo processor

Core™ Solo processor

Xeon® processor LV

Vol. 2A 1-1

ABOUT THIS MANUAL

• Intel

P6 family processors are IA-32 processors based on the P6 family microarchitecture. This includes the Pentium® Pro, Pentium® II, Pentium® III, and P entium® III Xeon® processors.

The Pentium® 4, Pentium® D, and Pentium® processor Extreme Editions are based on the Intel NetBurst® microarchitecture. Most early Intel® Xeon® processors are based on the Intel NetBurst series are based on the Intel NetBurst® microarchitecture.

The Intel® Core™ Duo, Intel® Core™ Solo and dual-core Intel® Xeon® processor LV are based on an improved Pentium® M processor microarchitecture.

The Intel® Xeon® processor 3000, 3200, 5100, 5300, and 7300 series, Intel® Pentium® dual-core, Intel® Core™2 Duo, Intel® Core™2 Quad, and Intel® Core™2 Extreme processors are based on Intel® Core™ microarchitecture.

P6 family , P entium® M, Intel® Core™ Solo, Intel® Core™ Duo processors, dual-core Intel® Xeon® processor LV, and early generations of P entium 4 and Intel X eon processors support IA-32 architecture.

The Intel® Xeon® processor 3000, 3200, 5000, 5100, 5300, 7100, 7300 series, Intel Pentium® D processors, Pentium® Dual-Core processor, newer generations of Pentium 4 and Intel Xeon processor family support Intel

IA-32 architecture is the instruction set architecture and programming environment for Intel's 32-bit microprocessors.

Intel® 64 architecture is the instruction set architecture and programming environment which is the superset of Intel’s 32-bit and 64-bit architectures. It is compatible with the IA-32 architecture.

Core™2 Duo processor

Core™2 Quad processor

Xeon® processor 3000, 3200 series

Xeon® processor 5000 series

Xeon® processor 5100, 5300 series

Core™2 Extreme processor

Core™2 Extreme Quad-core processor

Xeon® processor 7100, 7300 series

Pentium® Dual-Core processor

microarchitecture. Intel Xeon processor 5000, 7100

Core™2 Duo, Intel® Core™2 Extreme, Intel® Core™2 Quad processors,

64 architecture.

1.2 OVERVIEW OF VOLUME 2A AND 2B: INSTRUCTION

SET REFERENCE

A description of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B, content follows:

1-2 Vol. 2A

ABOUT THIS MANUAL

Chapter 1 — About This Manual. Gives an overview of all five volumes of the

Intel

64 and IA-32 Architectures Software Developer’s Manual. It also describes the

notational conventions in these manuals and lists related Intel® manuals and documentation of interest to programmers and hardware designers.

Chapter 2 — Instruction Format. Describes the machine-level instruction format used for all IA-32 instructions and gives the allowable encodings of prefixes, the operand-identifier byte (ModR/M byte), the addressing-mode specifier byte (SIB byte), and the displacement and immediate bytes.

Chapter 3 — Instruction Set Reference , A-M. Describes Intel 64 and IA-32 instructions in detail, including an algorithmic description of operations, the effect on flags, the effect of operand- and address-size attributes, and the ex ceptions that may be generated. The instructions are arranged in alphabetical order. Generalpurpose, x87 FPU, Intel MMX™ technology , SSE/SSE2/SSE3 extensions, and system instructions are included.

Chapter 4 — Instruction Set Reference, N-Z. Continues the description of Intel 64 and IA-32 instructions started in Chapter 3. It provides the balance of the alphabetized list of instructions and starts Intel

64 and IA-32 Architectures Software

Developer’s Manual, Volume 2B.

Chapter 5 — VMX Instruction Reference. Describes the virtual-machine extensions (VMX). VMX is intended for a system executive to support virtualization of processor hardware and a system software layer acting as a host to multiple guest software environments.

Chapter 6— Safer Mode Extensions Reference. Describes the safer mode extensions (SMX). SMX is intended for a system executive to support launching a measured environment in a platform where the identity of the software controlling the platform hardware can be measured for the purpose of making trust decisions.

Appendix A — Opcode Map. Gives an opcode map for the IA-32 instruction set. Appendix B — Instruction Formats and Encodings. Gives the binary encoding of

each form of each IA-32 instruction.

Appendix C — Intel

Lists the Intel

C/C++ compiler intrinsics and their assembly code equivalents for each

C/C++ Compiler Intrinsics and Functional Equivalents.

of the IA-32 MMX and SSE/SSE2/SSE3 instructions.

1.3 NOTATIONAL CONVENTIONS

This manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for hexadecimal and binary numbers. A review of this notation makes the manual easier to read.

Vol. 2A 1-3

ABOUT THIS MANUAL

1.3.1 Bit and Byte Order

In illustrations of data structures in memory , smaller addresses appear toward the bottom of the figure; addresses increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to two raised to the power of the bit position. IA-32 processors are “little endian” machines; this means the bytes of a word are numbered starting from the least significant byte. Figure 1-1 illustrates these conventions.

1-4 Vol. 2A

ABOUT THIS MANUAL

Highest Address

Byte 3

Byte 2

Data Structure

Byte 1

Byte 0

Byte Offset

Bit offset

28 24

20 16 12

8 4

Lowest

Address

Figure 1-1. Bit and Byte Order

1.3.2 Reserved Bits and Software Compatibility

In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked as reserved, it is essential for compatibility with future processors that software treat these bits as having a future, though unkno wn, effect. The behavior of reserved bits should be regarded as not only undefined, but unpredictable. Software should follow these guidelines in dealing with reserved bits:

• Do not depend on the states of any reserved bits when testing the values of

registers which contain such bits. Mask out the reserved bits before testing.

• Do not depend on the states of any reserved bits when storing to memory or to a

• Do not depend on the ability to retain information written into any reserved bits.

• When loading a register, always load the reserved bits with the values indicated

in the documentation, if any , or reload them with values previously read from the same register.

NOTE

Avoid any softw are dependence upon the st ate of reserved bits in IA-32 registers. Depending upon the values of reserved register bits will make software dependent upon the unspecified manner in which the processor handles these bits. Programs that depend upon reserved values risk incompatibility with future processors.

Vol. 2A 1-5

ABOUT THIS MANUAL

1.3.3 Instruction Operands

When instructions are represented symbolically , a subset of the IA -32 assembly language is used. In this subset, an instruction has the following format:

label: mnemonic argument1, argument2, argument3

where:

• A label is an identifier which is followed by a colon.

• A mnemonic is a reserved name for a class of instruction opcodes which have

the same function.

• The operands argument1, argument2, and argument3 are optional. Th ere may

be from zero to three operands, depending on the opcode. When present, they take the form of either literals or identifiers for data items. Operand identifiers are either reserved names of registers or are assumed to be assigned to data items declared in another part of the program (which may not be shown in the example).

When two operands are present in an arithmetic or logical instruction, the right operand is the source and the left operand is the destination.

For example:

LOADREG: MOV EAX, SUBTOTAL

In this example, LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand, and SUBT OTAL is the source operand. Some assembly languages put the source and destination in reverse order.

1.3.4 Hexadecimal and Binary Numbers

Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed by the character H (for example, F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F.

Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the character B (for example, 1010B). The “B” designation is only used in situations where confusion as to the type of number might arise.

1.3.5 Segmented Addressing

The processor uses byte addressing. This means memory is organized and accessed as a sequence of bytes. Whether one or more bytes are being accessed, a byte address is used to locate the byte or bytes in memory. The r ange of memory that can be addressed is called an address space.

The processor also supports segmented addressing. This is a form of addressing where a program may have many independent address spaces, called segments.

1-6 Vol. 2A

ABOUT THIS MANUAL

For example, a program can keep its code (instructions) and stack in separate segments. Code addresses would always refer to the code space, and stack addresses would always refer to the stack space. The following notation is used to specify a byte address within a segment:

Segment-register:Byte-address

For example, the following segment address identifies the byte at address FF79H in the segment pointed by the DS register:

DS:FF79H

The following segment address identifies an instruction address in the code segment. The CS register points to the code segment and the EIP register contains the address of the instruction.

CS:EIP

1.3.6 Exceptions

An exception is an event that typically occurs when an instruction causes an error. For example, an attempt to divide by zero gener ates an exception. However, some exceptions, such as breakpoints, occur under other conditions. Some types of exceptions may provide error codes. An error code reports additional information about the error. An example of the notation used to show an exception and error code is shown below:

#PF(fault code)

This example refers to a page-fault exception under conditions where an error code naming a type of fault is reported. Under some conditions, exceptions which produce error codes may not be able to report an accurate code. In this case, the error code is zero, as shown below for a general-protection exception:

#GP(0)

1.3.7 A New Syntax for CPUID, CR, and MSR Values

Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register bits, and by reading model-specific registers. We are moving toward a new syntax to represent this information. See Figure 1-2.

Vol. 2A 1-7

ABOUT THIS MANUAL

&38,',QSXWDQG2XWSXW

6RPHLQSXWVUHTXLUHYDOXHVLQ($;DQG(&; 7KLVLVUHSUHVHQWHGDV&38,'($; Q(&; Q ,IRQO\RQHYDOXHLVSUHVHQW($;LVLPSOLHG

&RQWURO5HJLVWHU9DOXHV

&38,'+(&;66(>ELW@ 

2XWSXWUHJLVWHUDQGIHDWXUHIODJRUILHOG

QDPHZLWKELWSRVLWLRQV

9DOXHRUUDQJHRIRXWSXW

&526);65>ELW@ 

([DPSOH&5QDPH

)HDWXUHIODJRUILHOGQDPH

ZLWKELWSRVLWLRQV

9DOXHRUUDQJHRIRXWSXW

0RGHO6SHFLILF5HJLVWHU9DOXHV

,$B0,6&B(1$%/(6(1$%/()23&2'(>ELW@ 

([DPSOH065QDPH

)HDWXUHIODJRUILHOGQDPHZLWKELWSRVLWLRQV

9DOXHRUUDQJHRIRXWSXW

20

Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation

1.4 RELATED LITERATURE

Literature related to Intel 64 and IA-32 processors is listed on-line at:

http://developer.intel.com/products/processor/manuals/index.htm

Some of the documents listed at this web site can be viewed on-line; others can be ordered. The literature available is listed by Intel processor and then by the following

1-8 Vol. 2A

ABOUT THIS MANUAL

literature types: applications notes, data sheets, manuals, papers, and specification updates.

2.1 INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE, AND VIRTUAL-8086 MODE

The Intel 64 and IA-32 architectures instruction encodings are subsets of the format shown in Figure 2-1. Instructions consist of optional instruction prefixes (in any order), primary opcode bytes (up to three bytes), an addressing-form specifier (if required) consisting of the ModR/M byte and sometimes the SIB (Scale-Index-Base) byte, a displacement (if required), and an immediate data field (if required).

Instruction

Prefixes

Up to four prefixes of 1 byte each (optional)

Opcode

1-, 2-, or 3-byte opcode

Mod

Reg/

Opcode

ModR/M

1 byte (if required)

R/M

1 byte (if required)

SIB Displacement

Address displacement of 1, 2, or 4 bytes or none

Index

Base

65 3

Scale

Immediate

Immediate data of 1, 2, or 4 bytes or none

Figure 2-1. Intel 64 and IA-32 Architectures Instruction Format

2.1.1 Instruction Prefixes

Instruction prefixes are divided into four groups, each with a set of allowable prefix codes. For each instruction, one prefix may be used from each of four groups (Groups 1, 2, 3, 4) and be placed in any order .

• Group 1

— Lock and repeat prefixes:

• F0H—LOCK

Vol. 2A 2-1

INSTRUCTION FORMAT

• F2H—REPNE/REPNZ (used only with string instructions; when used with

the escape opcode 0FH, this prefix is treated as a mandatory prefix for some SIMD instructions)

• F3H—REP or REPE/REPZ (used only with string instructions; when used

with the escape opcode 0FH, this prefix is treated as an mandatory prefix for some SIMD instructions)

• Group 2

— Segment override prefixes:

• 2EH—CS segment override (use with any branch instruction is reserved)

• 36H—SS segment override prefix (use with any branch instruction is

reserved)

• 3EH—DS segment override prefix (use with any bran ch instruction is

reserved)

• 26H—ES segment override prefix (use with any branch instruction is

reserved)

• 64H—FS segment override prefix (use with any branch instruction is

reserved)

• 65H—GS segment override prefix (use with any branch instruction is

reserved)

— Branch hints:

• 2EH—Branch not taken (used only with Jcc instructions)

• 3EH—Branch taken (used only with Jcc instructions)

• Group 3

• 66H—Operand-size override prefix (when used with the es cape opcode

0FH, this is treated as a mandatory prefix for some SIMD instructions)

• Group 4

• 67H—Address-size override prefix

The LOCK prefix (F0H) forces an operation that ensures exclusive use of shared memory in a multiprocessor environment. See “LOCK — Assert LOCK# Sig nal Prefix” in Chapter 3, “Instruction Set Reference, A-M,” for a description of this prefix.

Repeat prefixes (F2H, F3H) cause an instruction to be repeated for each element of a string. Use these prefixes only with string instructions (MOVS, CMPS, SCAS, LODS, STOS, INS, and OUTS). Their use, followed by 0FH, is treated as a mandatory prefix by a number of SSE/SSE2/SSE3 instructions. Use of repeat prefixes and/or undefined opcodes with other Intel 64 or IA-32 instructions is reserved; such use may cause unpredictable behavior.

Branch hint prefixes (2EH, 3EH) allow a progr am to give a hint to the processor about the most likely code path for a branch. Use these prefixes only with conditional branch instructions (Jcc). Other use of branch hint prefixes and/or other undefined

2-2 Vol. 2A

INSTRUCTION FORMAT

opcodes with Intel 64 or IA-32 instructions is reserved; such use may cause unpredictable behavior.

The operand-size override prefix allows a program to switch between 16- and 32-bit operand sizes. Either size can be the default; use of the prefix selects the non-default size. Use of 66H followed by 0FH is treated as a mandatory prefix by some SSE/SSE2/SSE3 instructions. Other use of the 66H prefix with MMX/SSE/SSE2/SSE3 instructions is reserved; such use may cause unpredictable behavior.

The address-size override prefix (67H) allows programs to switch between 16- and 32-bit addressing. Either size can be the default; the prefix selects the non-default size. Using this prefix and/or other undefined opcodes when operands for the instruction do not reside in memory is reserved; such use may cause unpredictable behavior.

2.1.2 Opcodes

A primary opcode can be 1, 2, or 3 bytes in length. An additional 3-bit opcode field is sometimes encoded in the ModR/M byte. Smaller fields can be defined within the primary opcode. Such fields define the direction of operation, size of displacements, register encoding, condition codes, or sign extension. Encoding fields used by an opcode vary depending on the class of operation.

T wo-byte opcode formats for general-purpose and SIMD instructions consist of:

• An escape opcode byte 0FH as the primary opcode and a second opcode byte, or

• A mandatory prefix (66H, F2H, or F3H), an escape opcode byte, and a second

opcode byte (same as previous bullet)

For example, CVTDQ2PD consists of the following sequence: F3 0F E6. The first byte is a mandatory prefix for SSE/SSE2/SSE3 instructions (it is not considered as a repeat prefix).

Three-byte opcode formats for general-purpose and SIMD instructions consist of:

• An escape opcode byte 0FH as the primary opcode, plus two additional opcode

bytes, or

• A mandatory prefix (66H), an escape opcode byte, plus two additional opcode

bytes (same as previous bullet)

For example, PHADDW for XMM registers consists of the following sequence: 66 0F 38 01. The first byte is the mandatory prefix.

Valid opcode expressions are defined in Appendix A and Appendix B.

Vol. 2A 2-3

INSTRUCTION FORMAT

2.1.3 ModR/M and SIB Bytes

Many instructions that refer to an operand in memory have an addressing-form specifier byte (called the ModR/M byte) following the primary opcode. The ModR/M byte contains three fields of information:

• The mod field combines with the r/m field to form 32 possible values: eight

registers and 24 addressing modes.

• The reg/opcode field specifies either a register number or three more bits of

opcode information. The purpose of the reg/opcode field is specified in the primary opcode.

• The r/m field can specify a register as an oper and or it can be combined with the

mod field to encode an addressing mode. Sometimes, certain combinations of the mod field and the r/m field is used to express opcode information for some instructions.

Certain encodings of the ModR/M byte require a second addressing byte (the SIB byte). The base-plus-index and scale-plus-index forms of 32-bit addressing require the SIB byte. The SIB byte includes the following fields:

• The scale field specifies the scale factor.

• The index field specifies the register number of the index register .

• The base field specifies the register number of the base register.

See Section 2.1.5 for the encodings of the ModR/M and SIB bytes.

2.1.4 Displacement and Immediate Bytes

Some addressing forms include a displacement immediately following the ModR/M byte (or the SIB byte if one is present). If a displacement is required; it be 1, 2, or 4 bytes.

If an instruction specifies an immediate operand, the operand always follows any displacement bytes. An immediate operand can be 1, 2 or 4 bytes.

2.1.5 Addressing-Mode Encoding of ModR/M and SIB Bytes

The values and corresponding addressing forms of the ModR/M and SIB bytes are shown in Table 2-1 through T able 2-3: 16-bit addressing forms specifie d by the ModR/M byte are in T able 2-1 and 32-bit addressing forms are in T able 2-2. Table 2-3 shows 32-bit addressing forms specified by the SIB byte. In cases where the reg/opcode field in the ModR/M byte represents an extended opcode, valid encodings are shown in Appendix B.

In T able 2-1 and Table 2-2, the Effective Address column lists 32 effective addresses that can be assigned to the first operand of an instruction by using the Mod and R/M fields of the ModR/M byte. The first 24 options provide ways of specifying a memory

2-4 Vol. 2A

INSTRUCTION FORMAT

location; the last eight (Mod = 11B) provide ways of specifying general-purpose, MMX technology and XMM registers.

The Mod and R/M columns in T able 2-1 and T able 2-2 give the binary encodings of the Mod and R/M fields required to obtain the effective address listed in the first column. For example: see the row indicated by Mod = 11B, R/M = 000B. The row identifies the general-purpose registers EAX, AX or AL; MMX technology register MM0; or XMM register XMM0. The register used is determined by the opcode byte and the operandsize attribute.

Now look at the seventh row in either table (labeled “REG =”). This row specifies the use of the 3-bit Reg/Opcode field when the field is used to give the location of a second operand. The second operand must be a gener al-purpose, MMX technology, or XMM register. Rows one through five list the registers that may correspond to the value in the table. Again, the reg ister used is determined by the opcode byte along with the operand-size attribute.

If the instruction does not require a second operand, then the Reg/Opcode field may be used as an opcode extension. This use is represented by the sixth row in the tables (labeled “/digit (Opcode)”). Note that values in row six are represented in decimal form.

The body of T able 2-1 and T able 2-2 (under the label “V alue of ModR/M Byte (in Hexadecimal)”) contains a 32 by 8 array that presents all of 256 values of the ModR/M byte (in hexadecimal). Bits 3, 4 and 5 are specified by the column of the table in which a byte resides. The row specifies bits 0, 1 and 2; and bits 6 and 7. The figure below demonstrates interpretation of one table value.

Mod 11 RM 000

/digit (Opcode);

REG = 001 C8H 11001000

Figure 2-2. Table Interpretation of ModR/M Byte (C8H)

Vol. 2A 2-5

INSTRUCTION FORMAT

Table 2-1. 16-Bit Addressing Forms with the ModR/M Byte

001 010 011 100 101 110 111

AL AX EAX MM0 XMM0 0 000

00 01 02 03 04 05 06 07

40 41 42 43 44 45 46 47

80 81 82 83 84 85 86 87

C0 C1 C2 C3 C4 C5 C6 C7

CX ECX MM1 XMM1 1 001

08 09 0A 0B 0C 0D 0E 0F

48 49 4A 4B 4C 4D 4E 4F

88 89 8A 8B 8C 8D 8E 8F

C8 C9 CA CB CC CD CE CF

DX EDX MM2 XMM2 2 010

10 11 12 13 14 15 16 17

50 51 52 53 54 55 56 57

90 91 92 93 94 95 96 97

D0 D1 D2 D3 D4 D5 D6 D7

BX EBX MM3 XMM3 3 011

18 19 1A 1B 1C 1D 1E 1F

58 59 5A 5B 5C 5D 5E 5F

98 99 9A 9B 9C 9D 9E 9F

D8 D9 DA DB DC DD DE DF

SP ESP MM4 XMM4 4 100

20 21 22 23 24 25 26 27

60 61 62 63 64 65 66 67

A0 A1 A2 A3 A4 A5 A6 A7

E0 EQ E2 E3 E4 E5 E6 E7

BP1 EBP MM5 XMM5 5 101

28 29 2A 2B 2C 2D 2E 2F

68 69 6A 6B 6C 6D 6E 6F

A8 A9 AA AB AC AD AE AF

E8 E9 EA EB EC ED EE EF

r8(/r) r16(/r) r32(/r) mm(/r) xmm(/r) (In decimal) /digit (Opcode) (In binary) REG =

Effective Address Mod R/M Value of ModR/M Byte (in Hexadecimal)

[BX+SI]

00 000 [BX+DI] [BP+SI] [BP+DI] [SI] [DI]

disp16 [BX]

[BX+SI]+disp8

01 000 [BX+DI]+disp8 [BP+SI]+disp8 [BP+DI]+disp8 [SI]+disp8 [DI]+disp8 [BP]+disp8 [BX]+disp8

[BX+SI]+disp16

10 000 [BX+DI]+disp16 [BP+SI]+disp16 [BP+DI]+disp16 [SI]+disp16 [DI]+disp16 [BP]+disp16 [BX]+disp16

EAX/AX/AL/MM0/XMM0

11 000 ECX/CX/CL/MM1/XMM1 EDX/DX/DL/MM2/XMM2 EBX/BX/BL/MM3/XMM3 ESP/SP/AHMM4/XMM4 EBP/BP/CH/MM5/XMM5 ESI/SI/DH/MM6/XMM6 EDI/DI/BH/MM7/XMM7

DH SI ESI MM6 XMM6 6 110

30 31 32 33 34 35 36 37

70 71 72 73 74 75 76 77

B0 B1 B2 B3 B4 B5 B6 B7

F0 F1 F2 F3 F4 F5 F6 F7

BH DI EDI MM7 XMM7 7 111

38 39 3A 3B 3C 3D 3E 3F

78 79 7A 7B 7C 7D 7E 7F

B8 B9 BA BB BC BD BE BF

F8 F9 FA FB FC FD FE FF

NOTES:

1. The default segment register is SS for the effective addresses containing a BP index, DS for other effective addresses.

2. The disp16 nomenclature denotes a 16-bit displacement that follows the ModR/M byte and that is added to the index.

3. The disp8 nomenclature denotes an 8-bit displacement that follows the ModR/M byte and that is sign-extended and added to the index.

2-6 Vol. 2A

INSTRUCTION FORMAT

Table 2-2. 32-Bit Addressing Forms with the ModR/M Byte

r8(/r) r16(/r) r32(/r) mm(/r) xmm(/r) (In decimal) /digit (Opcode) (In binary) REG =

Effective Address Mod R/M Value of ModR/M Byte (in Hexadecimal)

[EAX] [ECX] [EDX] [EBX]

[--][--]

disp32 [ESI] [EDI]

[EAX]+disp8

[ECX]+disp8 [EDX]+disp8 [EBX]+disp8 [--][--]+disp8 [EBP]+disp8 [ESI]+disp8 [EDI]+disp8

[EAX]+disp32 [ECX]+disp32 [EDX]+disp32 [EBX]+disp32 [--][--]+disp32 [EBP]+disp32 [ESI]+disp32 [EDI]+disp32

EAX/AX/AL/MM0/XMM0 ECX/CX/CL/MM/XMM1 EDX/DX/DL/MM2/XMM2 EBX/BX/BL/MM3/XMM3 ESP/SP/AH/MM4/XMM4 EBP/BP/CH/MM5/XMM5 ESI/SI/DH/MM6/XMM6 EDI/DI/BH/MM7/XMM7

00 000

001 010 011 100 101 110 111

01 000

001 010 011 100 101 110 111

10 000

001 010 011 100 101 110 111

11 000

001 010 011 100 101 110 111

AL AX EAX MM0 XMM0 0 000

00 01 02 03 04 05 06 07

40 41 42 43 44 45 46 47

80 81 82 83 84 85 86 87

C0 C1 C2 C3 C4 C5 C6 C7

CX ECX MM1 XMM1 1 001

08 09 0A 0B 0C 0D 0E 0F

48 49 4A 4B 4C 4D 4E 4F

88 89 8A 8B 8C 8D 8E 8F

C8 C9 CA CB CC CD CE CF

DX EDX MM2 XMM2 2 010

10 11 12 13 14 15 16 17

50 51 52 53 54 55 56 57

90 91 92 93 94 95 96 97

D0 D1 D2 D3 D4 D5 D6 D7

BX EBX MM3 XMM3 3 011

18 19 1A 1B 1C 1D 1E 1F

58 59 5A 5B 5C 5D 5E 5F

98 99 9A 9B 9C 9D 9E 9F

D8 D9 DA DB DC DD DE DF

SP ESP MM4 XMM4 4 100

20 21 22 23 24 25 26 27

60 61 62 63 64 65 66 67

A0 A1 A2 A3 A4 A5 A6 A7

E0 E1 E2 E3 E4 E5 E6 E7

BP EBP MM5 XMM5 5 101

28 29 2A 2B 2C 2D 2E 2F

68 69 6A 6B 6C 6D 6E 6F

A8 A9 AA AB AC AD AE AF

E8 E9 EA EB EC ED EE EF

DH SI ESI MM6 XMM6 6 110

30 31 32 33 34 35 36 37

70 71 72 73 74 75 76 77

B0 B1 B2 B3 B4 B5 B6 B7

F0 F1 F2 F3 F4 F5 F6 F7

BH DI EDI MM7 XMM7 7 111

38 39 3A 3B 3C 3D 3E 3F

78 79 7A 7B 7C 7D 7E 7F

B8 B9 BA BB BC BD BE BF

F8 F9 FA FB FC FD FE FF

NOTES:

1. The [--][--] nomenclature means a SIB follows the ModR/M byte.

2. The disp32 nomenclature denotes a 32-bit displacement that follows the ModR/M byte (or the SIB byte if one is present) and that is added to the index.

3. The disp8 nomenclature denotes an 8-bit displacement that follows the ModR/M byte (or the SIB byte if one is present) and that is sign-extended and added to the index.

Table 2-3 is organized to give 256 possible values of the SIB byte (in hexadecimal). General purpose registers used as a base are indicated across the top of the table, along with corresponding values for the SIB byte’s base field. Table rows in the body

Vol. 2A 2-7

INSTRUCTION FORMAT

of the table indicate the register used as the index (SIB byte bits 3, 4 and 5) and the scaling factor (determined by SIB byte bits 6 and 7).

Table 2-3. 32-Bit Addressing Forms with the SIB Byte

r32 (In decimal) Base = (In binary) Base =

Scaled Index SS Index Value of SIB Byte (in Hexadecimal)

[EAX] [ECX] [EDX] [EBX] none [EBP] [ESI] [EDI]

[EAX*2] [ECX*2] [EDX*2] [EBX*2] none [EBP*2] [ESI*2] [EDI*2]

[EAX*4] [ECX*4] [EDX*4] [EBX*4] none [EBP*4] [ESI*4] [EDI*4]

[EAX*8] [ECX*8] [EDX*8] [EBX*8] none [EBP*8] [ESI*8] [EDI*8]

00 000

001 010 011 100 101 110 111

01 000

001 010 011 100 101 110 111

10 000

001 010 011 100 101 110 111

11 000

001 010 011 100 101 110 111

EAX 0 000

00 08 10 18 20 28 30 38

40 48 50 58 60 68 70 78

80 88 90 98 A0 A8 B0 B8

C0 C8 D0 D8 E0 E8 F0 F8

ECX 1 001

01 09 11 19 21 29 31 39

41 49 51 59 61 69 71 79

81 89 91 89 A1 A9 B1 B9

C1 C9 D1 D9 E1 E9 F1 F9

EDX 2 010

02 0A 12 1A 22 2A 32 3A

42 4A 52 5A 62 6A 72 7A

82 8A 92 9A A2 AA B2 BA

C2 CA D2 DA E2 EA F2 FA

EBX 3 011

03 0B 13 1B 23 2B 33 3B

43 4B 53 5B 63 6B 73 7B

83 8B 93 9B A3 AB B3 BB

C3 CB D3 DB E3 EB F3 FB

ESP 4 100

04 0C 14 1C 24 2C 34 3C

44 4C 54 5C 64 6C 74 7C

84 8C 94 9C A4 AC B4 BC

C4 CC D4 DC E4 EC F4 FC

[*] 5 101

05 0D 15 1D 25 2D 35 3D

45 4D 55 5D 65 6D 75 7D

85 8D 95 9D A5 AD B5 BD

C5 CD D5 DD E5 ED F5 FD

ESI 6 110

06 0E 16 1E 26 2E 36 3E

46 4E 56 5E 66 6E 76 7E

86 8E 96 9E A6 AE B6 BE

C6 CE D6 DE E6 EE F6 FE

EDI 7 111

07 0F 17 1F 27 2F 37 3F

47 4F 57 5F 67 6F 77 7F

87 8F 97 9F A7 AF B7 BF

C7 CF D7 DF E7 EF F7 FF

NOTES:

1. The [*] nomenclature means a disp32 with no base if the MOD is 00B. Otherwise, [*] means disp8 or disp32 + [EBP]. This provides the following address modes:

MOD bits Effective Address 00 [scaled index] + disp32 01 [scaled index] + disp8 + [EBP] 10 [scaled index] + disp32 + [EBP]

2-8 Vol. 2A

INSTRUCTION FORMAT

2.2 IA-32E MODE

IA-32e mode has two sub-modes. These are:

• Compatibility Mode. Enables a 64-bit operating system to run most legacy

protected mode software unmodified.

• 64-Bit Mode. Enables a 64-bit operating system to run applications written to

access 64-bit address space.

2.2.1 REX Prefixes

REX prefixes are instruction-prefix bytes used in 64-bit mode. They do the following:

• Specify GPRs and SSE registers.

• Specify 64-bit operand size.

• Specify extended control registers.

Not all instructions require a REX prefix in 64-bit mode. A prefix is necessary only if an instruction references one of the extended registers or uses a 64-bit operand. If a REX prefix is used when it has no meaning, it is ignored.

Only one REX prefix is allowed per instruction. If used, the prefix must immediately precede the opcode byte or the two-byte opcode escape prefix (if present). Other placements are ignored. The instruction-size limit of 15 bytes still applies to instructions with a REX prefix. See Figure 2-3.

Legacy Prefixes

Grp 1, Grp 2, Grp 3, Grp 4 (optional)

REX

Prefix

(optional)

Opcode

1-, 2-, or 3-byte opcode

ModR/M

1 byte (if required)

SIB Displacement

1 byte (if required)

Address displacement of 1, 2, or 4 bytes

Figure 2-3. Prefix Ordering in 64-bit Mode

Immediate

Immediate data of 1, 2, or 4 bytes or none

Vol. 2A 2-9

INSTRUCTION FORMAT

2.2.1.1 Encoding

Intel 64 and IA-32 instruction formats specify up to three registers by using 3-bit fields in the encoding, depending on the format:

• ModR/M: the reg and r/m fields of the ModR/M byte

• ModR/M with SIB: the reg field of the ModR/M byte, the base and index fields of

the SIB (scale, index, base) byte

• Instructions without ModR/M: the reg field of the opcode

In 64-bit mode, these formats do not change. Bits needed to define fields in the 64-bit context are provided by the addition of REX prefixes.

2.2.1.2 More on REX Prefix Fields

REX prefixes are a set of 16 opcodes that span one row of the opcode map and occupy entries 40H to 4FH. These opcodes represent valid instructions (INC or DEC) in IA-32 operating modes and in compatibility mode. In 64-bit mode, the same opcodes represent the instruction prefix REX and are not treated as individual instructions.

The single-byte-opcode form of INC/DEC in struction not available in 64-bit mode. INC/DEC functionality is still available using ModR/M forms of the same instructions (opcodes FF/0 and FF/1).

See T able 2-4 for a summary of the REX prefix format. Figure 2-4 though Figure 2-7 show examples of REX prefix fields in use. Some combinations of REX prefix fields are invalid. In such cases, the prefix is ignored. Some additional information follows:

• Setting REX.W can be used to determine the operand size but does not solely

determine operand width. Like the 66H size prefix, 64-bit operand size override has no effect on byte-specific operations.

• For non-byte operations: if a 66H prefix is used with prefix (REX.W = 1), 66H is

ignored.

• If a 66H override is used with REX and REX.W = 0, the operand size is 16 bits.

• REX.R modifies the ModR/M reg field when that field encodes a GPR, SSE, control

or debug register. REX.R is ignored when ModR/M specifies other registers or defines an extended opcode.

• REX.X bit modifies the SIB index field.

• REX.B either modifies the base in the ModR/M r/m field or SIB base field; or it

modifies the opcode reg field used for accessing GPRs.

2-10 Vol. 2A

INSTRUCTION FORMAT

Table 2-4. REX Prefix Fields [BITS: 0100WRXB]

Field Name Bit Position Definition

- 7:4 0100

W 3 0 = Operand size determined by CS.D

1 = 64 Bit Operand Size

R 2 Extension of the ModR/M reg field

X 1 Extension of the SIB index field

B 0 Extension of the ModR/M r/m field, SIB base field, or

Opcode reg field

0RG50%\WH

5(;35(),;

:5%

2SFRGH

PRG



UHJ UP UUU EEE

5UUU %EEE

20;ILJ

Figure 2-4. Memory Addressing Without an SIB Byte; REX.X Not Used

0RG50%\WH

5(;35(),;

:5%

2SFRGH

PRG



UHJ UP

UUU EEE

5UUU %EEE

20;ILJ

Figure 2-5. Register-Register Addressing (No Memory Operand); REX.X Not Used

Vol. 2A 2-11

INSTRUCTION FORMAT

5(;35(),;

:5;%

0RG50%\WH

2SFRGH

PRG



UHJ

UUU

UP



VFDOH

5UUU

Figure 2-6. Memory Addressing With a SIB Byte

5(;35(),;

:%

2SFRGH

UHJ EEE

%EEE

20;ILJ

6,%%\WH

LQGH[

[[[

;[[[

EDVH EEE

%EEE

20;ILJ

Figure 2-7. Register Operand Coded in Opcode Byte; REX.X & REX.R Not Used

In the IA-32 architecture, byte registers (AH, AL, BH, BL, CH, CL, DH, and DL) are encoded in the ModR/M byte’s reg field, the r/m field or the opcode reg field as registers 0 through 7. REX prefixes provide an additional addressing capability for byteregisters that makes the least-significant byte of GPRs available for byte oper ations.

Certain combinations of the fields of the ModR/M byte and the SIB byte have special meaning for register encodings. For some combinations, fields expanded by the REX prefix are not decoded. Table 2-5 describes how each case behaves.

2-12 Vol. 2A

Table 2-5. Special Cases of REX Encodings

ModR/M or SIB

ModR/M Byte mod != 11 SIB byte present. SIB byte required

ModR/M Byte mod == 0 Base register not

SIB Byte index ==

SIB Byte base ==

NOTES:

* Don’t care about value of REX.B

Sub-field Encodings

r/m == b*100(ESP)

r/m == b*101(EBP)

0100(ESP)

0101(EBP)

Compatibility Mode Operation

used.

Index register not used.

Base register is unused if mod = 0.

Compatibility Mode Implications Additional Implications

for ESP-based addressing.

EBP without a displacement must be done using

mod = 01 with displacement of 0.

ESP cannot be used as an index register.

Base register depends on mod encoding.

INSTRUCTION FORMAT

REX prefix adds a fourth bit (b) which is not decoded (don't care).

SIB byte also required for R12-based addressing.

REX prefix adds a fourth bit (b) which is not decoded (don't care).

Using RBP or R13 without displacement must be done using mod = 01 with a displacement of 0.

REX prefix adds a fourth bit (b) which is decoded.

There are no additional implications. The expanded index field allows distinguishing RSP from R12, therefore R12 can be used as an index.

REX prefix adds a fourth bit (b) which is not decoded.

This requires explicit displacement to be used with EBP/RBP or R13.

2.2.1.3 Displacement

Addressing in 64-bit mode uses existing 32-bit ModR/M and SIB encodings. The ModR/M and SIB displacement sizes do not change. They remain 8 bits or 32 bits and are sign-extended to 64 bits.

2.2.1.4 Direct Memory-Offset MOVs

In 64-bit mode, direct memory-offset forms of the MOV instruction are extended to specify a 64-bit immediate absolute address. This address is called a moffset. No prefix is needed to specify this 64-bit memory offset. For these MOV instructions, the

Vol. 2A 2-13

INSTRUCTION FORMAT

size of the memory offset follows the address-size default (64 bits in 64-bit mode). See Table 2-6.

Table 2-6. Direct Memory Offset Form of MOV

Opcode Instruction

A0 MOV AL, moffset

A1 MOV EAX, moffset

A2 MOV moffset, AL

A3 MOV moffset, EAX

2.2.1.5 Immediates

In 64-bit mode, the typical size of immediate operands remains 32 bits. When the operand size is 64 bits, the processor sign-extends all immediates to 64 bits prior to their use.

Support for 64-bit immediate operands is accomplished by expanding the semantics of the existing move (MOV reg, imm16/32) instructions. These instructions (opcodes B8H – BFH) move 16-bits or 32-bits of immediate data (depending on the effective operand size) into a GPR. When the effective operand size is 64 bits, these instructions can be used to load an immediate into a GPR. A REX prefix is needed to override the 32-bit default operand size to a 64-bit operand size.

For example:

48 B8 8877665544332211 MOV RAX,1122334455667788H

2.2.1.6 RIP-Relative Addressing

A new addressing form, RIP-relative (relative instruction-pointer) addressing, is implemented in 64-bit mode. An effective address is formed by adding displacement to the 64-bit RIP of the next instruction.

In IA-32 architecture and compatibility mode, addressing relative to the instruction pointer is available only with control-transfer instructions. In 64-bit mode, instructions that use ModR/M addressing can use RIP-relative addressing. Without RIP-relative addressing, all ModR/M instruction modes address memory relative to zero.

RIP-relative addressing allows specific ModR/M modes to address memory relative to the 64-bit RIP using a signed 32-bit displacement. This provides an offset range of ±2GB from the RIP. Table 2-7 shows the ModR/M and SIB encodings for RIP- relative addressing. Redundant forms of 32-bit displacement-addressing exist in the current ModR/M and SIB encodings. There is one ModR/M encoding and there are several SIB encodings. RIP-relative addressing is encoded using a redundant form.

In 64-bit mode, the ModR/M Disp32 (32-bit displacement) encoding is re-defined to be RIP+Disp32 rather than disp lacement -only. See T able 2-7.

2-14 Vol. 2A

INSTRUCTION FORMAT

Table 2-7. RIP-Relative Addressing

ModR/M and SIB Sub-field Encodings

ModR/M Byte

SIB Byte base == 101 (none) if mod = 00,

The ModR/M encoding for RIP-relative addressing does not depend on using prefix. Specifically , the r/m bit field encoding of 101B (used to select RIP-relative addressing) is not affected by the REX prefix. For example, selecting R13 (REX.B = 1, r/m = 101B) with mod = 00B still results in RIP-relative addressing. The 4-bit r/m field of REX.B combined with ModR/M is not fully decoded. In order to address R13 with no displacement, software must encode R13 + 0 using a 1-byte displacement of zero.

RIP-relative addressing is enabled by 64-bit mode, not by a 64-bit address-size. The use of the address-size prefix does not disable RIP-relative addressing. The effect of the address-size prefix is to truncate and zero-extend the computed effective address to 32 bits.

mod == 00 Disp32 RIP + Disp32 Must use SIB form with

r/m == 101 (none)

index == 100 (none)

scale = 0, 1, 2, 4

Compatibility Mode Operation

Disp32

64-bit Mode Operation

Same as legacy

Additional Implications in 64-bit mode

normal (zero-based) displacement addressing

None

2.2.1.7 Default 64-Bit Operand Size

In 64-bit mode, two groups of instructions have a default operand size of 64 bits (do not need a REX prefix for this operand size). These are:

• Near branches

• All instructions, except far branches, that implicitly reference the RSP

2.2.2 Additional Encodings for Control and Debug Registers

In 64-bit mode, more encodings for control and debug registers are available. The REX.R bit is used to modify the ModR/M reg field when that field encodes a control or debug register (see T able 2-4). These encodings enable the processor to address CR8-CR15 and DR8- DR15. An additional control register (CR8) is defined in 64-bit mode. CR8 becomes the Task Priority Register (TPR).

In the first implementation of IA-32e mode, CR9-CR15 and DR8-DR15 are not implemented. Any attempt to access unimplemented registers results in an invalid-opcode exception (#UD).

Vol. 2A 2-15

INSTRUCTION FORMAT

2-16 Vol. 2A

CHAPTER 3

INSTRUCTION SET REFERENCE, A-M

This chapter describes the instruction set for the Intel 64 and IA-32 architectures (A-M) in IA-32e, protected, Virtual-8086, and real modes of operation. The set includes general-purpose, x87 FPU, MMX, SSE/SSE2/SSE3/SSS E3, and system instructions. See also Chapter 4, “Instruction Set Reference, N-Z,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.

For each instruction, each operand combination is described. A description of the instruction and its operand, an operational description, a description of the effect of the instructions on flags in the EFLAGS register, and a summary of exceptions that can be generated are also provided.

3.1 INTERPRETING THE INSTRUCTION REFERENCE PAGES

This section describes the format of information contained in the instruction reference pages in this chapter . It explains notational con ventions and abbreviations used in these sections.

3.1.1 Instruction Format

The following is an example of the format used for each instruction description in this chapter. The heading below introduces the example. The table below provides an example summary table.

CMC—Complement Carry Flag [this is an example]

Opcode Instruction 64-bit Mode Compat/

Leg Mode

F5 CMC Valid Valid Complement carry flag.

Description

Vol. 2A 3-1

INSTRUCTION SET REFERENCE, A-M

3.1.1.1 Opcode Column in the Instruction Summary Table

The “Opcode” column in the table above shows the object code produced for each form of the instruction. When possible, codes are given as hexadecimal bytes in the same order in which they appear in memory. Definitions of entries other than hexadecimal bytes are as follows:

• REX.W — Indicates the use of a REX prefix that affects operand size or

instruction semantics. The ordering of the REX prefix and other optional/mandatory instruction prefixes are discussed Chapter 2. Note that REX prefixes that promote legacy instructions to 64-bit behavior are not listed explicitly in the opcode column.

• /digit — A digit between 0 and 7 indicates that the ModR/M byte of th e

instruction uses only the r/m (register or memory) operand. The reg field contains the digit that provides an extension to the instruction's opcode.

• /r — Indicates that the ModR/M byte of the instruction contains a register

operand and an r/m operand.

• cb, cw, cd, cp, co, ct — A 1-byte (cb), 2-byte (cw), 4-byte (cd), 6-byte (cp),

8-byte (co) or 10-byte (ct) value following the opcode. This value is used to specify a code offset and possibly a new value for the code segment register .

• ib, iw, id, io — A 1-byte (ib), 2-byte (iw), 4-byte (id) or 8-byte (io) immediate

operand to the instruction that follows the opcode, ModR/M bytes or scaleindexing bytes. The opcode determines if the operand is a signed value. All words, doublewords and quadwords are given with the low-order byte first.

• +rb, +rw, +rd, +ro — A register code, from 0 through 7, added to the

hexadecimal byte given at the left of the plus sign to form a single opcode byte. See Table 3-1 for the codes. The +ro columns in the table are applicable only in 64-bit mode.

• +i — A number used in floating-point instructions when one of the operands is

ST(i) from the FPU register stack. The number i (which can range from 0 to 7) is added to the hexadecimal byte given at the left of the plus sign to form a single opcode byte.

Table 3-1. Register Codes Associated With +rb, +rw, +rd, +ro

byte register word register dword register quadword register

(64-Bit Mode only)

AL None 0 AX None 0 EAX None 0 RAX None 0

CL None 1 CX None 1 ECX None 1 RCX None 1

DL None 2 DX None 2 EDX None 2 RDX None 2

3-2 Vol. 2A

REX.B

Reg Field

REX.B

Reg Field

REX.B

Reg Field

REX.B

Reg Field

INSTRUCTION SET REFERENCE, A-M

Table 3-1. Register Codes Associated With +rb, +rw, +rd, +ro (Contd.)

byte register word register dword register quadword register

(64-Bit Mode only)

BL None 3 BX None 3 EBX None 3 RBX None 3

AH Not

CH N.E. 5 BP None 5 EBP None 5 N/A N/A N/A

DH N.E. 6 SI None 6 ESI None 6 N/A N/A N/A

BH N.E. 7 DI None 7 EDI None 7 N/A N/A N/A

SPL Yes 4 SP None 4 ESP None 4 RSP None 4

BPL Yes 5 BP None 5 EBP None 5 RBP None 5

SIL Yes 6 SI None 6 ESI None 6 RSI None 6

DIL Yes 7 DI None 7 EDI None 7 RDI None 7

REX.B

encod able (N.E.)

Reg Field

4 SP None 4 ESP None 4 N/A N/A N/A

REX.B

Reg Field

REX.B

Reg Field

REX.B

Reg Field

Registers R8 - R15 (see below): Available in 64-Bit Mode Only

R8L Yes 0 R8W Yes 0 R8D Yes 0 R8 Yes 0

R9L Yes 1 R9W Yes 1 R9D Yes 1 R9 Yes 1

R10L Yes 2 R10W Yes 2 R10D Yes 2 R10 Yes 2

R11L Yes 3 R11W Yes 3 R11D Yes 3 R11 Yes 3

R12L Yes 4 R12W Yes 4 R12D Yes 4 R12 Yes 4

R13L Yes 5 R13W Yes 5 R13D Yes 5 R13 Yes 5

R14L Yes 6 R14W Yes 6 R14D Yes 6 R14 Yes 6

R15L Yes 7 R15W Yes 7 R15D Yes 7 R15 Yes 7

3.1.1.2 Instruction Column in the Opcode Summary Table

The “Instruction” column gives the syntax of the instruction statement as it would appear in an ASM386 program. The following is a list of the symbols used to represent operands in the instruction statements:

• rel8 — A relative address in the range from 128 bytes before the end of the

instruction to 127 bytes after the end of the instruction.

• rel16, rel32, rel64 — A relative address within the same code segment as the

instruction assembled. The rel16 symbol applies to instructions with an operandsize attribute of 16 bits; the rel32 symbol applies to instructions with an operand-size attribute of 32 bits; the rel64 symbol applies to instructions with an operand-size attribute of 64 bits.

Vol. 2A 3-3

INSTRUCTION SET REFERENCE, A-M

• ptr16:16, ptr16:32 and ptr16:64 — A far pointer, typically to a code segment

different from that of the instruction. The notation 16:16 indicates that the value of the pointer has two parts. The value to the left of the colon is a 16-bit selector or value destined for the code segment register. The value to the right corresponds to the offset within the destination segment. The ptr16:16 symbol is used when the instruction's operand-size attribute is 16 bits; the ptr16:32 symbol is used when the operand-size attribute is 32 bits; the ptr16:64 symbol is used when the operand-size attribute is 64 bits.

• r8 — One of the byte general-purpose registers: AL, CL, DL, BL, AH, CH , DH, BH,

BPL, SPL, DIL and SIL; or one of the byte registers (R8L - R15L) available when using REX.R and 64-bit mode.

• r16 — One of the word general-purpose registers: AX, CX, DX, BX, SP , BP, SI, DI;

or one of the word registers (R8-R15) available when using REX.R and 64-bit mode.

• r32 — One of the doubleword general-purpose registers: EAX, EC X, EDX, EBX,

ESP, EBP , ESI, EDI; or one of the doubleword registers (R8D - R15D) available when using REX.R in 64-bit mode.

• r64 — One of the quadword general-purpos e registers: RAX, RBX, RCX, RDX,

RDI, RSI, RBP, RSP , R8–R15. These are available when using REX.R and 64-bit mode.

• imm8 — An immediate byte value. The imm8 symbol is a signed number

between –128 and +127 inclusive. For instructions in which imm8 is combined with a word or doubleword operand, the immediate value is sign-extended to form a word or doubleword. The upper byte of the word is filled with the topmost bit of the immediate value.

• imm16 — An immediate word value used for instructions whose operand-siz e

attribute is 16 bits. This is a number between –32,768 and +32,767 inclusive.

• imm32 — An immediate doubleword value used for instructions whose

operand-size attribute is 32 bits. It allows the use of a number between +2,147,483,647 and –2,147,483,648 inclusive.

• imm64 — An immediate quadword value used for instructions whose

operand-size attribute is 64 bits. The value allows the use of a number between +9,223,372,036,854,775,807 and –9,223,372,036,854,775,808 inclusive.

• r/m8 — A byte operand that is either the contents of a byte general-purpose

register (AL, CL, DL, BL, AH, CH, DH, BH, BPL, SPL, DIL and SIL) or a byte from memory . Byte registers R8L - R15L are available using REX.R in 64-bit mode.

• r/m16 — A word general-purpose register or memory operand used for instruc-

tions whose operand-size attribute is 16 bits. The word general-purpose registers are: AX, CX, DX, BX, SP, BP, SI, DI. The contents of memory are found at the address provided by the effective address computation. Word registers R8W R15W are available using REX.R in 64-bit mode.

3-4 Vol. 2A

INSTRUCTION SET REFERENCE, A-M

• r/m32 — A doubleword general-purpose register or memory oper and used for

instructions whose operand-size attribute is 32 bits. The doubleword generalpurpose registers are: EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI. The contents of memory are found at the address provided by the effective address computation. Doubleword registers R8D - R15D are available when using REX.R in 64-bit mode.

• r/m64 — A quadword general-purpose register or memory oper and used for

instructions whose operand-size attribute is 64 bits when using REX.W . Quadword general-purpose registers are: RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8–R15; these are available only in 64-bit mode. The contents of memory are found at the address provided by the effective address computation.

• m — A 16-, 32- or 64-bit operand in memory.

• m8 — A byte operand in memory , usually expressed as a v ariable or array name,

but pointed to by the DS:(E)SI or ES:(E)DI registers. In 64-bit mode, it is pointed to by the RSI or RDI registers.

• m16 — A word oper and in memory, usually expressed as a variable or array

name, but pointed to by the DS:(E)SI or ES:(E)DI registers. This nomenclature is used only with the string instructions.

• m32 — A doubleword operand in memory, usually expressed as a variable or

array name, but pointed to by the DS:(E)SI or ES:(E)DI registers. This nomenclature is used only with the string instructions.

• m64 — A memory quadword oper and in memory.

• m128 — A memory double quadword operand in memory. This nomenclature is

used only with SSE and SSE2 instructions.

• m16:16, m16:32 & m16:64 — A memory operand containing a far pointer

composed of two numbers. The number to the left of the colon corresponds to the pointer's segment selector. The number to the right corresponds to its offset.

• m16&32, m16&16, m32&32, m16&64 — A memory operand consisting of

data item pairs whose sizes are indicated on the left and the right side of the ampersand. All memory addressing modes are allowed. The m16&16 and m32&32 operands are used by the BOUND instruction to provide an operand containing an upper and lower bounds for array indices. The m16&32 operand is used by LIDT and LGDT to provide a word with which to load the limit field, and a doubleword with which to load the base field of the corresponding GDTR and IDTR registers. The m16&64 operand is used by LIDT and LGDT in 64-bit mode to provide a word with which to load the limit field, and a quadword with which to load the base field of the corresponding GDTR and IDTR registers.

• moffs8, moffs16, moffs32, moffs64 — A simple memory variable (memory

offset) of type byte, word, or doubleword used by some variants of the MOV instruction. The actual address is given by a simple offset relative to the segment base. No ModR/M byte is used in the instruction. The number shown with moffs indicates its size, which is determined by the address-size attribute of the instruction.

Vol. 2A 3-5

INSTRUCTION SET REFERENCE, A-M

• Sreg — A segment register. The segment register bit assignments are ES = 0,

CS = 1, SS = 2, DS = 3, FS = 4, and GS = 5.

• m32fp, m64fp, m80fp — A single-precision, double-precision, and double

extended-precision (respectively) floating-point operand in memory . These symbols designate floating-point values that are used as operands for x87 FPU floating-point instructions.

• m16int, m32int, m64int — A word, doubleword, and quadword integer

(respectively) operand in memory . These symbols designate integers that are used as operands for x87 FPU integer instructions.

• ST or ST(0) — The top element of the FPU register stack.

• ST(i) — The i

element from the top of the FPU register stack (i ← 0 through 7).

• mm — An MMX register. The 64-bit MMX registers are: MM0 through MM7.

• mm/m32 — The low order 32 bits of an MMX register or a 32-bit memory

operand. The 64-bit MMX registers are: MM0 through MM7. The contents of memory are found at the address provided by the effective address computation.

• mm/m64 — An MMX register or a 64-bit memory operand. The 64-bit MMX

registers are: MM0 through MM7. The contents of memory are found at the address provided by the effective address computation.

• xmm — An XMM register. The 128-bit XMM registers are: XMM0 through XMM7;

XMM8 through XMM15 are available using REX.R in 64-bit mode.

• xmm/m32— An XMM register or a 32-bit memory operand. The 128-bit XMM

registers are XMM0 through XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at the address provided by the effective address computation.

• xmm/m64 — An XMM register or a 64-bit memory operand. The 128-bit SIMD

floating-point registers are XMM0 through XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at the address provided by the effective address computation.

• xmm/m128 — An XMM register or a 128-bit memory operand. The 128-bit XMM

registers are XMM0 through XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at the address provided by the effective address computation.

3.1.1.3 64-bit Mode Column in the Instruction Summary Table

The “64-bit Mode” column indicates whether the opcode sequence is supported in 64-bit mode. The column uses the following notation:

• Valid — Supported.

• Invalid — Not supported.

• N.E. — Indicates an instruction syntax is not encodable in 64-bit mode (it may

represent part of a sequence of valid instructions in other modes).

3-6 Vol. 2A

INSTRUCTION SET REFERENCE, A-M

• N.P. — Indicates the REX prefix does not affect the legacy instruction in 64-bit

mode.

• N.I. — Indicates the opcode is treated as a new instruction in 64-bit mode.

• N.S. — Indicates an instruction syntax that requires an address override prefix in

64-bit mode and is not supported. Using an address override prefix in 64-bit mode may result in model-specific execution behavior.

3.1.1.4 Compatibility/Legacy Mode Column in the Instruction Summary

Table

The “Compatibility/Legacy Mode” column provides information on the opcode sequence in either the compatibility mode or other IA-32 modes. The column uses the following notation:

• Valid — Supported.

• Invalid — Not supported.

• N.E. — Indicates an Intel 64 instruction mnemonics/syntax that is not

encodable; the opcode sequence is not applicable as an individual instruction in compatibility mode or IA-32 mode. The opcode may represent a valid sequence of legacy IA-32 instructions.

3.1.1.5 Description Column in the Instruction Summary Table

The “Description” column briefly explains forms of the instruction.

3.1.1.6 Description Section

Each instruction is then described by number of information sections. The “Description” section describes the purpose of the instructions and required operands in more detail.

3.1.1.7 Operation Section

The “Operation” section contains an algorithm description (frequently written in pseudo-code) for the instruction. Algorithms are composed of the following elements:

• Comments are enclosed within the symbol pairs “(*” and “*)”.

• Compound statements are enclosed in keywords, such as: IF , THEN, ELSE and FI

for an if statement; DO and OD for a do statement; or CASE... OF for a case statement.

• A register name implies the contents of the register . A register name enclosed in

brackets implies the contents of the location whose address is contained in that register. For example, ES:[DI] indicates the contents of the location whose ES segment relative address is in register DI. [SI] indicates the contents of the

Vol. 2A 3-7

INSTRUCTION SET REFERENCE, A-M

address contained in register SI relative to the SI register’s default segment (DS) or the overridden segment.

• Parentheses around the “E” in a general-purpose register name, such as (E)SI,

indicates that the offset is read from the SI register if the address-size attribute is 16, from the ESI register if the address-size attribute is 32. Parentheses around the “R” in a gener al-purpose register name, (R)SI, in the presence of a 64-bit register definition such as (R)SI, indicates that the offset is read from the 64-bit RSI register if the address-size attribute is 64.

• Brackets are used for memory operands where they mean that the contents of

the memory location is a segment-relative offset. For example, [SRC] indicates that the content of the source operand is a segment-relative offset.

• A ← B indicates that the value of B is assigned to A.

• The symbols =, ≠, >, <, ≥, and ≤ are relational operators used to compare two

values: meaning equal, not equal, greater or equal, less or equal, respectively . A relational expression such as A ← B is TRUE if the value of A is equal to B; otherwise it is FALSE.

• The expression “<< COUNT” and “>> COUNT” indicates that the destination

operand should be shifted left or right by the number of bits indicated by the count operand.

The following identifiers are used in the algorithmic descriptions:

• OperandSize and AddressSize — The OperandSiz e identifier repre sents the

operand-size attribute of the instruction, which is 16, 32 or 64-bits. The AddressSize identifier represents the addr ess-size attribute, which is 16, 32 or 64-bits. For example, the following pseudo-code indicates that the operand-size attribute depends on the form of the MOV instruction used.

IF Instruction ← MOVW

THEN OperandSize ← 16;

ELSE

IF Instruction ← MOVD

THEN OperandSize ← 32;

ELSE

IF Instruction ← MOVQ

THEN OperandSize ← 64;

FI;

See “Operand-Size and Address-Size Attributes” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for guidelines

on how these attributes are determined.

• StackAddrSize — Represents the stack address-size attribute associated with

the instruction, which has a value of 16, 32 or 64-bits. See “ Address-Siz e

3-8 Vol. 2A

INSTRUCTION SET REFERENCE, A-M

Attribute for Stack” in Chapter 6, “Proc edure Calls, Interrupts, and Exceptions, ” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.

• SRC — Represents the source operand.

• DEST — Represents the destination operand.

The following functions are used in the algorithmic descriptions:

• ZeroExtend(value) — Returns a v alue zero-extended to the operand-size

attribute of the instruction. For example, if the operand-size attribute is 32, zero extending a byte value of –10 converts the byte from F6H to a doubleword value of 000000F6H. If the value passed to the ZeroExtend function and the operandsize attribute are the same size, ZeroExtend returns the value unaltered.

• SignExtend(value) — Returns a value sign-extended to the operand-size

attribute of the instruction. For example, if the operand-size attribute is 32, sign extending a byte containing the value –10 converts the byte from F6H to a doubleword value of FFFFFFF6H. If the value passed to the SignExtend function and the operand-size attribute are the same size, SignExtend returns the value unaltered.

• SaturateSignedWordToSignedByte — Converts a signed 16-bit value to a

signed 8-bit value . If the signed 16- bit value is less than –128, it is represented by the saturated value -128 (80H); if it is greater than 127, it is represented by the saturated value 127 (7FH).

• SaturateSignedDwordToSignedWord — Converts a signed 32-bit v alue to a

signed 16-bit value. If the signed 32-bit value is less than –32768, it is represented by the saturated value –32768 (8000H); if it is greater than 32767, it is represented by the saturated value 32767 (7FFFH).

• SaturateSignedWordToUnsignedByte — Converts a signed 16-bit value to an

unsigned 8-bit value. If the signed 16-bit value is less than zero, it is represented by the saturated value zero (00H); if it is greater than 255, it is represented by the saturated value 255 (FFH).

• SaturateToSignedByte — Represents the result of an operation as a signed

8-bit value. If the result is less than –128, it is represented by the saturated value –128 (80H); if it is greater than 127, it is represented by the saturated value 127 (7FH).

• SaturateToSignedWord — Represents the result of an operation as a signed

16-bit value. If the result is less than –32768, it is represented by the saturated value –32768 (8000H); if it is greater than 32767, it is represented by the saturated value 32767 (7FFFH).

• SaturateToUnsignedByte — Represents the result of an oper ation as a signed

8-bit value. If the result is less than zero it is represented by the saturated value zero (00H); if it is greater than 255, it is represented by the saturated value 255 (FFH).

• SaturateToUnsignedWord — Represents the result of an operation as a signed

16-bit value. If the result is less than zero it is represented by the saturated value

Vol. 2A 3-9

INSTRUCTION SET REFERENCE, A-M

zero (00H); if it is greater than 65535, it is represented by the saturated value 65535 (FFFFH).

• LowOrderWord(DEST * SRC) — Multiplies a word operand by a word operand

and stores the least significant word of the doubleword result in the destination operand.

• HighOrderWord(DEST * SRC) — Multiplies a word operand by a word oper and

and stores the most significant word of the doubleword result in the destination operand.

• Push(value) — Pushes a value onto the stack. The number of bytes pushed is

determined by the operand-size attribute of the instruction. See the “Operation” subsection of the “PUSH—Push Word, Doubleword or Quadword Onto the Stack” section in Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.

• Pop() removes the value from the top of the stack and returns it. The statement

EAX ← Pop(); assigns to EAX the 32-bit value from the top of the stack. P op will return either a word, a doubleword or a quadword depending on the operand-size attribute. See the “Operation” subsection in the “POP—Pop a V alue from the Stack” section of Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.

• PopRegisterStack — Marks the FPU ST(0) register as empty and increments

the FPU register stack pointer (TOP) by 1.

• Switch-Tasks — Performs a task switch.

• Bit(BitBase, BitOffset) — Returns the value of a bit within a bit string. The bit

string is a sequence of bits in memory or a register . Bits are numbered from loworder to high-order within registers and within memory bytes. If the BitBase is a register, the BitOffset can be in the range 0 to [15, 31, 63] depending on the mode and register size. See Figure 3-1: the function Bit[RAX, 21] is illustrated.

Bit Offset ← 21

Figure 3-1. Bit Offset for BIT[RAX, 21]

If BitBase is a memory address, the BitOffset can range has different ranges depending on the operand size (see Table 3-2).

3-10 Vol. 2A

02131

INSTRUCTION SET REFERENCE, A-M

Table 3-2. Range of Bit Positions Specified by Bit Offset Operands

Operand Size Immediate BitOffset Register BitOffset

16 0 to 15 −2 32 0 to 31 −2 64 0 to 63 −2

The addressed bit is numbered (Offset MOD 8) within the byte at address (BitBase + (BitOffset DIV 8)) where DIV is signed division with rounding towards negative infinity and MOD returns a positive number (see Figure 3-2).

to 215 − 1

to 231 − 1

to 263 − 1

07775 0 0

BitBase + 1

BitBase BitBase − 1

BitOffset ← +13

0777500

BitBase − 1BitBase

BitBase − 2

BitOffset ← −11

Figure 3-2. Memory Bit Indexing

3.1.1.8 Intel® C/C++ Compiler Intrinsics Equivalents Section

The Intel C/C++ compiler intrinsics equivalents are special C/C++ coding extensions that allow using the syntax of C function calls and C variables instead of hardware registers. Using these intrinsics frees programmers from having to manage registers and assembly programming. Further, the compiler optimizes the instruction scheduling so that executable run faster.

The following sections discuss the intrinsics API and the MMX technology and SIMD floating-point intrinsics. Each intrinsic equivalent is listed with the instruction description. There may be additional intrinsics that do not have an instru ction equivalent. It is strongly recommended that the reader reference the compiler documentation for the complete list of supported intrinsics.

Vol. 2A 3-11

INSTRUCTION SET REFERENCE, A-M

See Appendix C, “InteL® C/C++ Compiler Intrinsics and Functional Equivalents,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B, for more information on using intrinsics.

Intrinsics API

The benefit of coding with MMX technology intrinsics and the SSE/SSE2/SSE3 intrinsics is that you can use the syntax of C function calls and C variables instead of hardware registers. This frees you from managing registers and programming assembly. Further, the compiler optimizes the instruction scheduling so that your executable runs faster. For each computational and data manipulation instruction in the new instruction set, there is a corresponding C intrinsic that implements it directly. The intrinsics allow you to specify the underlying implementation (instruction selection) of an algorithm yet leave instruction scheduling and register allocation to the compiler.

MMX™ Technology Intrinsics

The MMX technology intrinsics are based on a __m64 data type that represents the specific contents of an MMX technology register. You can specify values in bytes, short integers, 32-bit values, or a 64-bit object. The __m64 data type, however, is not a basic ANSI C data type, and therefore you must observe the following usage restrictions:

• Use __m64 data only on the left-hand side of an assignment, as a return value,

or as a parameter. You cannot use it with other arithmetic expressions (“ +”, “>>”, and so on).

• Use __m64 objects in aggregates, such as unions to access the byte elements

and structures; the address of an __m64 object may be taken.

• Use __m64 data only with the MMX technology intrinsics described in this manual

and Intel® C/C++ compiler documentation.

• See:

— http://www.intel.com/support/performancetools/ — Appendix C, “InteL® C/C++ Compiler Intrinsics and Functional Equiv alents, ”

in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2B, for more information on using intrinsics. — SSE/SSE2/SSE3 Intrinsics — SSE/SSE2/SSE3 intrinsics all make use of the XMM registers of the P entium

III, Pentium 4, and Intel Xeon processors. There are three data types

supported by these intrinsics: __m128, __m128d, and __m128i.

• The __m128 data type is used to represent the contents of an XMM register used

by an SSE intrinsic. This is either four packed single-precision floating-point values or a scalar single-precision floating-point value.

• The __m128d data type holds two packed double-precision floating-point values

or a scalar double-precision floating-point value.

3-12 Vol. 2A

INSTRUCTION SET REFERENCE, A-M

• The __m128i data type can hold sixteen byte, eight word, or four doubleword, or

two quadword integer values.

The compiler aligns __m128, __m128d, and __m128i local and global data to 16-byte boundaries on the stack. To align integer , float, or double arrays, use the declspec statement as described in Intel C/C++ compiler documentation. See http://www.intel.com/support/performancetools/.

The __m128, __m128d, and __m128i data types are not basic ANSI C data types and therefore some restrictions are placed on its usage:

• Use __m128, __m128d, and __m128i only on the left-hand side of an

assignment, as a return value, or as a parameter . Do not use it in other arithmetic expressions such as “+” and “>>.”

• Do not initialize __m128, __m128d, and __m128i with literals; there is no way to

express 128-bit constants.

• Use __m128, __m128d, and __m128i objects in aggregates, such as unions (for

example, to access the float elements) and structures. The address of these objects may be taken.

• Use __m128, __m128d, and __m128i data only with the intrinsics described in

this user’s guide. See Appendix C, “InteL® C/C++ Compiler Intrinsics and Functional Equivalents,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B, for more information on using intrinsics.

The compiler aligns __m128, __m128d, and __m128i local data to 16-byte boundaries on the stack. Global __m128 data is also aligned on 16-byte boundaries. (To align float arrays, you can use the alignment declspec described in the following section.) Because the new instruction set treats the SIMD floating-point registers in the same way whether you are using packed or scalar data, there is no __m32 data type to represent scalar data as you might expect. For scalar operations, you should use the __m128 objects and the “scalar” forms of the intrinsics; the compiler and the processor implement these operations with 32-bit memory references.

The suffixes ps and ss are used to denote “packed single” and “scalar single” precision operations. The packed floats are represented in right-to-left order, with the lowest word (right-most) being used for scalar operations: [z, y, x, w]. T o explain how memory storage reflects this, consider the following example.

The operation:

float a[4] ← { 1.0, 2.0, 3.0, 4.0 }; __m128 t ← _mm_load_ps(a);

Produces the same result as follows:

__m128 t ← _mm_set_ps(4.0, 3.0, 2.0, 1.0);

In other words:

t ← [ 4.0, 3.0, 2.0, 1.0 ]

Where the “scalar” element is 1.0.

Vol. 2A 3-13

INSTRUCTION SET REFERENCE, A-M

Some intrinsics are “composites” because they require more than one instruction to implement them. You should be familiar with the hardware features provided by the SSE, SSE2, SSE3, and MMX technology when writing programs with the intrinsics.

Keep the following important issues in mind:

• Certain intrinsics, such as _mm_loadr_ps and _mm_cmpgt_ss, are not directly

supported by the instruction set. While these intrinsics are convenient programming aids, be mindful of their implementation cost.

• Data loaded or stored as __m128 objects must generally be 16-byte-aligned.

• Some intrinsics require that their argument be immediates, that is, constant

integers (literals), due to the nature of the instruction.

• The result of arithmetic operations acting on two NaN (Not a Number) arguments

is undefined. Therefore, floating- point operations using NaN arguments may not match the expected behavior of the corresponding assembly instructions.

For a more detailed description of each intrinsic and additional information related to its usage, refer to Intel C/C++ compiler documentation. See:

— http://www.intel.com/support/performancetools/ — Appendix C, “Intel® C/C++ Compiler Intrinsics and Functional Equiv alents,”

in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2B, for more information on using intrinsics.

3.1.1.9 Flags Affected Section

The “Flags Affected” section lists the flags in the EFLAGS register that are affected by the instruction. When a flag is cleared, it is equal to 0; when it is set, it is equal to 1. The arithmetic and logical instructions usually assign values to the status flags in a uniform manner (see Appendix A, “Eflags Cross-Reference,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1). Non-conventional assignments are described in the “Operation” section. The values of flags listed as undefined may be changed by the instruction in an indeterminate manner. Flags that are not listed are unchanged by the instruction.

3.1.1.10 FPU Flags Affected Section

The floating-point instructions have an “FPU Flags Affected” section that describes how each instruction can affect the four condition code flags of the FPU status word.

3.1.1.11 Protected Mode Exceptions Section

The “Protected Mode Exceptions” section lists the exceptions that can occur when the instruction is executed in protected mode and the reasons for the exceptions. Each exception is given a mnemonic that consists of a pound sign (#) followed by two letters and an optional error code in parentheses. For example, #GP(0) denotes a general protection exception with an error code of 0. Table 3-3 associates each two-

3-14 Vol. 2A

INSTRUCTION SET REFERENCE, A-M

letter mnemonic with the corresponding interrupt vector number and exception name. See Chapter 5, “Interrupt and Exception Handling, ” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for a detailed description of the exceptions.

Application programmers should consult the documentation provided with their operating systems to determine the actions taken when exceptions occur.

Table 3-3. Intel 64 and IA-32 General Exceptions

Vector No.

Name Source Protected

Mode

Real Address Mode

0#DE—Divide ErrorDIV and IDIV instructions. Yes Yes Yes

1 #DB—Debug Any code or data reference. Yes Yes Yes

3 #BP—Breakpoint INT 3 instruction. Yes Yes Yes

4 #OF—Overflow INTO instruction. Yes Yes Yes

5 #BR—BOUND Range

BO U N D instr u c tion. Yes Yes Ye s

Exceeded

6#UD—Invalid

Opcode (Undefined

UD2 instruction or reserved opcode.

Yes Yes Ye s

Opcode)

7 #NM—Device Not

Available (No Math

Floating-point or WAIT/FWAIT instruction.

Yes Yes Ye s

Coprocessor)

8 #DF—Double Fault Any instruction that can

Yes Yes Ye s generate an exception, an NMI, or an INTR.

10 #TS—Invalid TSS Task switch or TSS access. Yes Reserved Yes

11 #NP—Segment Not

Present

12 #SS—Stack

Segment Fault

13 #GP—General

Protection

Loading segment registers or accessing system segments.

Stack operations and SS register loads.

Any memory reference and other protection checks.

Yes Reserved Yes

Yes Yes Ye s

14 #PF—Page Fault Any memory reference. Yes Reserved Yes

16 #MF—Floating-Point

Error (Math Fault)

17 #AC—Alignment

Check

Floating-point or WAIT/FWAIT instruction.

Any data reference in memory.

Yes Yes Ye s

Yes Reserved Yes

Virtual 8086 Mode

Vol. 2A 3-15

INSTRUCTION SET REFERENCE, A-M

Table 3-3. Intel 64 and IA-32 General Exceptions (Contd.)

Vector No.

NOTES:

1. Apply to protected mode, compatibility mode, and 64-bit mode.

2. In the real-address mode, vector 13 is the segment overrun exception.

Name Source Protected

18 #MC—Machine

Check

19 #XM—SIMD

Floating-Point Numeric Error

Model dependent machine check errors.

SSE/SSE2/SSE3 floating-point instructions.

Mode

Yes Yes Ye s

Real Address Mode

Virtual 8086 Mode

3.1.1.12 Real-Address Mode Exceptions Section

The “Real-Address Mode Exceptions” section lists the exceptions that can occur when the instruction is executed in real-address mode (see T able 3-3).

3.1.1.13 Virtual-8086 Mode Exceptions Section

The “Virtual-8086 Mode Exceptions” section lists the exceptions that can occur when the instruction is executed in virtual-8086 mode (see T able 3-3).

3.1.1.14 Floating-Point Exceptions Section

The “Floating-Point Exceptions” section lists exceptions that can occur when an x87 FPU floating-point instruction is executed. All of these exception conditions result in a floating-point error exception (#MF, vector number 16) being generated. T able 3-4 associates a one- or two-letter mnemonic with the corresponding exception name. See “Floating-Point Exception Conditions” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a detailed description of these exceptions.

3-16 Vol. 2A

INSTRUCTION SET REFERENCE, A-M

Table 3-4. x87 FPU Floating-Point Exceptions

Mnemonic Name Source

Floating-point invalid operation:

#IS

#IA

#Z Floating-point divide-by-zero Divide-by-zero

#D Floating-point denormal operand Source operand that is a denormal number

#O Floating-point numeric overflow Overflow in result

#U Floating-point numeric underflow Underflow in result

#P Floating-point inexact result

- Stack overflow or underflow

- Invalid arithmetic operation

(precision)

- x87 FPU stack overflow or underflow

- Invalid FPU arithmetic operation

Inexact result (precision)

3.1.1.15 SIMD Floating-Point Exceptions Section

The “SIMD Floating-Point Exceptions” section lists exceptions that can occur when an SSE/SSE2/SSE3 floating-point instruction is executed. All of these exception conditions result in a SIMD floating-point error exception (#XM, vector number 19) being generated. Table 3-5 associates a one-letter mnemonic with the corresponding exception name. For a detailed description of these ex ceptions, refer to ”SSE and SSE2 Exceptions”, in Chapter 11 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.

Table 3-5. SIMD Floating-Point Exceptions

Mnemonic Name Source

#I Floating-point invalid operation Invalid arithmetic operation or source operand

#Z Floating-point divide-by-zero Divide-by-zero

#D Floating-point denormal operand Source operand that is a denormal number

#O Floating-point numeric overflow Overflow in result

#U Floating-point numeric underflow Underflow in result

#P Floating-point inexact result Inexact result (precision)

3.1.1.16 Compatibility Mode Exceptions Section

This section lists exception that occur within compatibility mode.

3.1.1.17 64-Bit Mode Exceptions Section

This section lists exception that occur within 64-bit mode.

Vol. 2A 3-17

INSTRUCTION SET REFERENCE, A-M

3.2 INSTRUCTIONS (A-M)

The remainder of this chapter provides descriptions of Intel 64 and IA-32 instructions (A-M). See also: Chapter 4, “Instruction Set Reference, N-Z,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.

3-18 Vol. 2A

INSTRUCTION SET REFERENCE, A-M

AAA—ASCII Adjust After Addition

Opcode Instruction 64-Bit Mode Compat/

Leg Mode

37 AAA Invalid Valid ASCII adjust AL after addition.

Description

Adjusts the sum of two unpacked BCD values to create an unpacked BCD result. The AL register is the implied source and destination operand for this instruction. The AAA instruction is only useful when it follows an ADD instruction that adds (binary addition) two unpacked BCD values and stores a byte result in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result.

If the addition produces a decimal carry , the AH register increments by 1, and the CF and AF flags are set. If there was no decimal carry, the CF and AF flags are cleared and the AH register is unchanged. In either case, bits 4 through 7 of the AL register are set to 0.

This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.

Operation

Description

IF 64-Bit Mode

THEN

#UD;

ELSE

IF ((AL AND 0FH) > 9) or (AF

THEN

AL ← AL + 6; AH ← AH + 1; AF ← 1; CF ← 1; AL ← AL AND 0FH;

ELSE

AF ← 0; CF ← 0;

AL ← AL AND 0FH;

FI;

= 1)

Flags Affected

The AF and CF flags are set to 1 if the adjustment results in a decimal carry; otherwise they are set to 0. The OF, SF , ZF, and PF flags are undefined.

AAA—ASCII Adjust After Addition

Vol. 2A 3-19

INSTRUCTION SET REFERENCE, A-M

Protected Mode Exceptions

#UD If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as protected mode.

Compatibility Mode Exceptions

Same exceptions as protected mode.

64-Bit Mode Exceptions

#UD If in 64-bit mode.

3-20 Vol. 2A AAA—ASCII Adjust After Addition

INSTRUCTION SET REFERENCE, A-M

AAD—ASCII Adjust AX Before Division

Opcode Instruction 64-Bit Mode Compat/

Leg Mode

D5 0A AAD Invalid Valid ASCII adjust AX before division.

D5 ib (No mnemonic) Invalid Valid Adjust AX before division to

Description

Adjusts two unpacked BCD digits (the least-significant digit in the AL register and the most-significant digit in the AH register) so that a division operation performed on the result will yield a correct unpacked BCD value. The AAD instruction is only useful when it precedes a DIV instruction that divides (binary division) the adjusted value in the AX register by an unpacked BCD value.

The AAD instruction sets the value in the AL register to (AL + (10 * AH)), and then clears the AH register to 00H. The value in the AX register is then equal to the binary equivalent of the original unpacked two-digit (base 10) number in registers AH and AL.

The generalized version of this instruction allows adjustment of two unpacked digits of any number base (see the “Operation” section below), by setting the imm8 byte to the selected number base (for example, 08H for octal, 0AH for decimal, or 0CH for base 12 numbers). The AAD mnemonic is interpreted by all assemblers to mean adjust ASCII (base 10) values. To adjust values in another number base, the instruction must be hand coded in machine code (D5 imm8).

This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.

Description

number base imm8.

Operation

IF 64-Bit Mode

THEN

#UD;

ELSE

tempAL ← AL; tempAH ← AH; AL ← (tempAL + (tempAH ∗ imm8)) AND FFH; (* imm8 is set to 0AH for the AAD mnemonic.*) AH ← 0;

FI;

The immediate value (imm8) is taken from the second byte of the instruction.

AAD—ASCII Adjust AX Before Division

Vol. 2A 3-21

INSTRUCTION SET REFERENCE, A-M

Flags Affected

The SF, ZF, and PF flags are set according to the resulting binary value in the AL register; the OF, AF, and CF flags are undefined.

Protected Mode Exceptions

#UD If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as protected mode.

Compatibility Mode Exceptions

Same exceptions as protected mode.

64-Bit Mode Exceptions

#UD If in 64-bit mode.

3-22 Vol. 2A AAD—ASCII Adjust AX Before Division

INSTRUCTION SET REFERENCE, A-M

AAM—ASCII Adjust AX After Multiply

Opcode Instruction 64-Bit

Mode

D4 0A AAM Invalid Valid ASCII adjust AX after multiply.

D4 ib (No mnemonic) Invalid Valid Adjust AX after multiply to number

Description

Adjusts the result of the multiplication of two unpacked BCD values to create a pair of unpacked (base 10) BCD values. The AX register is the implied source and destination operand for this instruction. The AAM instruction is only useful when it follows an MUL instruction that multiplies (binary multiplication) two unpacked BCD values and stores a word result in the AX register . The AAM instruction then adjusts the contents of the AX register to contain the correct 2-digit unpacked (base 10) BCD result.

The generalized version of this instruction allows adjustment of the contents of the AX to create two unpacked digits of any number base (see the “Operation” section below). Here, the imm8 byte is set to the selected number base (for example, 08H for octal, 0AH for decimal, or 0CH for base 12 numbers). The AAM mnemonic is interpreted by all assemblers to mean adjust to ASCII (base 10) values. To adjust to values in another number base, the instruction must be hand coded in machine code (D4 imm8).

This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.

Compat/ Leg Mode

Description

base imm8.

Operation

IF 64-Bit Mode

THEN

#UD;

ELSE

tempAL ← AL; AH ← tempAL / imm8; (* imm8 is set to 0AH for the AAM mnemonic *) AL ← tempAL MOD imm8;

FI;

The immediate value (imm8) is taken from the second byte of the instruction.

Flags Affected

The SF, ZF , and PF flags are set according to the resulting binary value in the AL register. The OF, AF , and CF flags are undefine d.

AAM—ASCII Adjust AX After Multiply

Vol. 2A 3-23

INSTRUCTION SET REFERENCE, A-M

Protected Mode Exceptions

#DE If an immediate value of 0 is used. #UD If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as protected mode.

Compatibility Mode Exceptions

Same exceptions as protected mode.

64-Bit Mode Exceptions

#UD If in 64-bit mode.

3-24 Vol. 2A AAM—ASCII Adjust AX After Multiply

INSTRUCTION SET REFERENCE, A-M

AAS—ASCII Adjust AL After Subtraction

Opcode Instruction 64-Bit

Mode

3F AAS Invalid Valid ASCII adjust AL after subtraction.

Description

Adjusts the result of the subtraction of two unpacked BCD values to create a unpacked BCD result. The AL register is the implied source and destination operand for this instruction. The AAS instruction is only useful when it follows a SUB instruction that subtracts (binary subtraction) one unpacked BCD value from another and stores a byte result in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result.

If the subtraction produced a decimal carry , the AH register decrements by 1, and the CF and AF flags are set. If no decimal carry occurred, the CF and AF flags are cleared, and the AH register is unchanged. In either case, the AL register is left with its top nibble set to 0.

This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.

Operation

Compat/ Leg Mode

Description

IF 64-bit mode

THEN

#UD;

ELSE

IF ((AL AND 0FH) > 9) or (AF

THEN

AL ← AL – 6; AH ← AH – 1; AF ← 1; CF ← 1; AL ← AL AND 0FH;

ELSE

CF ← 0; AF ← 0; AL ← AL AND 0FH;

FI;

= 1)

Flags Affected

The AF and CF flags are set to 1 if there is a decimal borrow; otherwise, they are cleared to 0. The OF, SF , ZF, and PF flags are undefined.

AAS—ASCII Adjust AL After Subtraction

Vol. 2A 3-25

INSTRUCTION SET REFERENCE, A-M

Protected Mode Exceptions

#UD If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as protected mode.

Compatibility Mode Exceptions

Same exceptions as protected mode.

64-Bit Mode Exceptions

#UD If in 64-bit mode.

3-26 Vol. 2A AAS—ASCII Adjust AL After Subtraction

INSTRUCTION SET REFERENCE, A-M

ADC—Add with Carry

Opcode Instruction 64-Bit

Mode

14 ib ADC AL, imm8 Valid Valid Add with carry imm8 to AL.

15 iw ADC AX, imm16 Valid Valid Add with carry imm16 to AX.

15 id ADC EAX,

Valid Valid Add with carry imm32 to EAX.

imm32

REX.W + 15 id ADC RAX,

Valid N.E. Add with carry imm32 sign

imm32

80 /2 ib ADC r/m8,

Valid Valid Add with carry imm8 to r/m8.

imm8

REX + 80 /2 ib ADC r/m8

Valid N.E. Add with carry imm8 to r/m8.

imm8

81 /2 iw ADC r/m16,

Valid Valid Add with carry imm16 to r/m16.

imm16

81 /2 id ADC r/m32,

Valid Valid Add with CF imm32 to r/m32.

imm32

REX.W + 81 /2 id ADC r/m64,

Valid N.E. Add with CF imm32 sign

imm32

83 /2 ib ADC r/m16,

Valid Valid Add with CF sign-extended

imm8

83 /2 ib ADC r/m32,

Valid Valid Add with CF sign-extended

imm8

REX.W + 83 /2 ib ADC r/m64,

Valid N.E. Add with CF sign-extended

imm8

10 /r ADC r/m8, r8 Valid Valid Add with carry byte register to

REX + 10 /r ADC r/m8

, r8*Valid N.E. Add with carry byte register to

11 /r ADC r/m16, r16 Valid Valid Add with carry r16 to r/m16.

11 /r ADC r/m32, r32 Valid Valid Add with CF r32 to r/m32.

REX.W + 11 /r ADC r/m64, r64 Valid N.E. Add with CF r64 to r/m64.

12 /r ADC r8, r/m8 Valid Valid Add with carry r/m8 to byte

REX + 12 /r ADC r8

, r/m8*Valid N.E. Add with carry r/m64 to byte

13 /r ADC r16, r/m16 Valid Valid Add with carry r/m16 to r16.

Compat/ Leg Mode

Description

extended to 64-bits to RAX.

extended to 64-bits to r/m64.

imm8 to r/m16.

imm8 into r/m32.

imm8 into r/m64.

r/m8.

r/m64.

ADC—Add with Carry

Vol. 2A 3-27

INSTRUCTION SET REFERENCE, A-M

Opcode Instruction 64-Bit

Mode

13 /r ADC r32, r/m32 Valid Valid Add with CF r/m32 to r32.

REX.W + 13 /r ADC r64, r/m64 Valid N.E. Add with CF r/m64 to r64.

NOTES:

* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is

used: AH, BH, CH, DH.

Compat/ Leg Mode

Description

Adds the destination operand (first operand), the source operand (second operand), and the carry (CF) flag and stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) The state of the CF flag represents a carry from a previous addition. When an immediate value is used as an operand, it is signextended to the length of the destination operand format.

The ADC instruction does not distinguish between signed or unsigned oper ands. Instead, the processor evaluates the result for both data types and sets the OF and CF flags to indicate a carry in the signed or unsigned result, respectively . The SF flag indicates the sign of the signed result.

The ADC instruction is usually executed as part of a multibyte or multiword addition in which an ADD instruction is followed by an ADC instruction.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically .

In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

Operation

DEST ← DEST + SRC + CF;

Flags Affected

The OF, SF , ZF, AF, CF, and PF flags are set according to the result.

Protected Mode Exceptions

#GP(0) If the destination is located in a non-writable segment.

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

3-28 Vol. 2A ADC—Add with Carry

INSTRUCTION SET REFERENCE, A-M

If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.

#SS(0) If a memory operand effective address is outside the SS

segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory

reference is made while the current privilege level is 3. #UD If the LOCK prefix is used but the destination is not a memory

operand.

Real-Address Mode Exceptions

#GP If a memory operand effective address is outside the CS, DS,

ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS

segment limit. #UD If the LOCK prefix is used but the destination is not a memory

operand.

Virtual-8086 Mode Exceptions

#GP(0) If a memory operand effective address is outside the CS, DS,

ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS

segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory

reference is made. #UD If the LOCK prefix is used but the destination is not a memory

operand.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-

canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory

reference is made while the current privilege level is 3. #UD If the LOCK prefix is used but the destination is not a memory

operand.

ADC—Add with Carry

Vol. 2A 3-29

INSTRUCTION SET REFERENCE, A-M

ADD—Add

Opcode Instruction 64-Bit Mode Compat/

Leg Mode

04 ib ADD AL, imm8 Valid Valid Add imm8 to AL.

05 iw ADD AX, imm16 Valid Valid Add imm16 to AX.

05 id ADD EAX, imm32 Valid Valid Add imm32 to EAX.

REX.W + 05 id ADD RAX, imm32 Valid N.E. Add imm32 sign-

80 /0 ib ADD r/m8, imm8 Valid Valid Add imm8 to r/m8.

REX + 80 /0 ib ADD r/m8

, imm8 Valid N.E. Add sign-extended

81 /0 iw ADD r/m16, imm16 Valid Valid Add imm16 to r/m16.

81 /0 id ADD r/m32, imm32 Valid Valid Add imm32 to r/m32.

REX.W + 81 /0 id ADD r/m64, imm32 Valid N.E. Add imm32 sign-

83 /0 ib ADD r/m16, imm8 Valid Valid Add sign-extended

83 /0 ib ADD r/m32, imm8 Valid Valid Add sign-extended

REX.W + 83 /0 ib ADD r/m64, imm8 Valid N.E. Add sign-extended

00 /r ADD r/m8, r8 Valid Valid Add r8 to r/m8.

REX + 00 /r ADD r/m8

, r8

Valid N.E. Add r8 to r/m8.

01 /r ADD r/m16, r16 Valid Valid Add r16 to r/m16.

01 /r ADD r/m32, r32 Valid Valid Add r32 to r/m32.

REX.W + 01 /r ADD r/m64, r64 Valid N.E. Add r64 to r/m64.

02 /r ADD r8, r/m8 Valid Valid Add r/m8 to r8.

REX + 02 /r ADD r8

, r/m8

Valid N.E. Add r/m8 to r8.

03 /r ADD r16, r/m16 Valid Valid Add r/m16 to r16.

03 /r ADD r32, r/m32 Valid Valid Add r/m32 to r32.

REX.W + 03 /r ADD r64, r/m64 Valid N.E. Add r/m64 to r64.

NOTES:

* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is

used: AH, BH, CH, DH.

Description

extended to 64-bits

to RAX.

imm8 to r/m64.

extended to 64-bits to r/m64.

imm8 to r/m16.

imm8 to r/m32.

imm8 to r/m64.

3-30 Vol. 2A ADD—Add

INSTRUCTION SET REFERENCE, A-M

Description

Adds the destination operand (first operand) and the source operand (second operand) and then stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is signextended to the length of the destination operand format.

The ADD instruction performs integer addition. It evaluates the result for both signed and unsigned integer operands and sets the OF and CF flags to indicate a carry (ov erflow) in the signed or unsigned result, respectively . The SF flag indicates the sign of the signed result.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically .

In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

Operation

DEST ← DEST + SRC;

Flags Affected

The OF, SF , ZF, AF, CF, and PF flags are set according to the result.

Protected Mode Exceptions

#GP(0) If the destination is located in a non-writable segment.

If a memory operand effective address is outside the CS, DS,

ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register is used to access memory and it

contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS

segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory

reference is made while the current privilege level is 3. #UD If the LOCK prefix is used but the destination is not a memory

operand.

Real-Address Mode Exceptions

#GP If a memory operand effective address is outside the CS, DS,

ES, FS, or GS segment limit.

ADD—Add

Vol. 2A 3-31

INSTRUCTION SET REFERENCE, A-M

#SS If a memory operand effective address is outside the SS

segment limit.

#UD If the LOCK prefix is used but the destination is not a memory

operand.

Virtual-8086 Mode Exceptions

#GP(0) If a memory operand effective address is outside th e CS, DS,

ES, FS, or GS segment limit.

#SS(0) If a memory operand effective address is outside the SS

segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory

reference is made. #UD If the LOCK prefix is used but the destination is not a memory

operand.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-

canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory

reference is made while the current privilege level is 3. #UD If the LOCK prefix is used but the destination is not a memory

operand.

3-32 Vol. 2A ADD—Add

INSTRUCTION SET REFERENCE, A-M

ADDPD—Add Packed Double-Precision Floating-Point Values

Opcode Instruction 64-Bit

Mode

66 0F 58 /r ADDPD xmm1,

xmm2/m128

Valid Valid Add packed double-precision floating-

Description

Performs a SIMD add of the two packed doub le-precision floating-point v alues from the source operand (second operand) and the destination operand (first operand), and stores the packed double-precision floating-point results in the destination operand.

The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. See Chapter 11 in the Intel® 64 and IA-32 Archi- tectures Software Developer’s Manual, Volume 1, for an overview of SIMD doubleprecision floating-point operation.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Operation

Compat/ Leg Mode

Description

point values from xmm2/m128 to xmm1.

DEST[63:0] ← DEST[63:0] + SRC[63:0]; DEST[127:64] ← DEST[127:64] + SRC[127:64];

Intel C/C++ Compiler Intrinsic Equivalent

ADDPD __m128d _mm_add_pd (m128d a, m128d b)

SIMD Floating-Point Exceptions

Overflow, Underflow , Invalid, Precision, Denormal.

Protected Mode Exceptions

#GP(0) For an illegal memory operand effective address in the CS, DS,

ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary ,

regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CRO.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1.

ADDPD—Add Packed Double-Precision Floating-Point Values

Vol. 2A 3-33

INSTRUCTION SET REFERENCE, A-M

#UD If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0. If CRO.EM[bit 2] = 1 . If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP(0) If a memory operand is not aligned on a 16-byte boundary,

regardless of segment. If any part of the operand lies outside the effective address

space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0.

If CR0.EM[bit 2] = 1.

If CR4.OSFXSR[bit 9] = 0.

If CPUID.01H:E DX.SSE 2[bit 26] = 0.

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

Same exceptions as in real address mode. #PF(fault-code) For a page fault.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-

canonical form. #GP(0) If the memory address is in a non-canonical form.

If memory operand is not aligned on a 16-byte boundary,

regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1.

3-34 Vol. 2A ADDPD—Add Packed Double-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-M

#UD If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.

ADDPD—Add Packed Double-Precision Floating-Point Values

Vol. 2A 3-35

INSTRUCTION SET REFERENCE, A-M

ADDPS—Add Packed Single-Precision Floating-Point Values

Opcode Instruction 64-Bit

Mode

0F 58 /r ADDPS xmm1, xmm2/m128 Valid Valid Add packed single-precision

Description

Performs a SIMD add of the four packed single-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the packed single-precision floating-point results in the destination operand.

The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. See Chapter 10 in the Intel® 64 and IA-32 Archi- tectures Software Developer’s Manual, Volume 1, for an ov erview of S IMD singleprecision floating-point operation.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Operation

Compat/ Leg Mode

Description

floating-point values from xmm2/m128 to xmm1.

DEST[31:0] ← DEST[31:0] + SRC[31:0]; DEST[63:32] ← DEST[63:32] DEST[95:64] ← DEST[95:64] DEST[127:96] ← DEST[127:96]

+ SRC[63:32]; + SRC[95:64];

+ SRC[127:96];

Intel C/C++ Compiler Intrinsic Equivalent

ADDPS __m128 _mm_add_ps(__m128 a, __m128 b)

SIMD Floating-Point Exceptions

Overflow, Underflow , Inv alid, Precision, Denormal.

Protected Mode Exceptions

#GP(0) For an illegal memory operand effective address in the CS, DS,

ES, FS or GS segments.

If a memory operand is not aligned on a 16-byte boundary ,

regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1.

3-36 Vol. 2A ADDPS—Add Packed Single-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-M

#XM If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1.

#UD If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP(0) If a memory operand is not aligned on a 16-byte boundary,

regardless of segment. If any part of the operand lies outside the effective address

space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0.

If CR0.EM[bit 2] = 1.

If CR4.OSFXSR[bit 9] = 0.

If CPUID.01H:EDX.SSE[bit 25] = 0.

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

Same exceptions as in real address mode. #PF(fault-code) For a page fault.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-

canonical form. #GP(0) If the memory address is in a non-canonical form.

If memory operand is not aligned on a 16-byte boundary ,

regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1.

ADDPS—Add Packed Single-Precision Floating-Point Values

Vol. 2A 3-37

INSTRUCTION SET REFERENCE, A-M

#XM If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1.

#UD If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.

3-38 Vol. 2A ADDPS—Add Packed Single-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-M

ADDSD—Add Scalar Double-Precision Floating-Point Values

Opcode Instruction 64-Bit

Mode

F2 0F 58 /r ADDSD xmm1, xmm2/m64 Valid Valid Add the low double-

Description

Adds the low double-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stor es the double-precision floating-point result in the destination operand.

The source operand can be an XMM register or a 64-bit memory location. The destination operand is an XMM register. The high quadword of the destination operand remains unchanged. See Chapter 11 in the Intel® 64 and IA-32 Architectures Soft- ware Developer’s Manual, Volume 1, for an overview of a scalar double-precision floating-point operation.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Compat/ Leg Mode

Description

precision floating-point value from xmm2/m64 to xmm1.

Operation

DEST[63:0] ← DEST[63:0] + SRC[63:0]; (* DEST[127:64] unchanged *)

Intel C/C++ Compiler Intrinsic Equivalent

ADDSD __m128d _mm_add_sd (m128d a, m128d b)

SIMD Floating-Point Exceptions

Overflow, Underflow , Invalid, Precision, Denormal.

Protected Mode Exceptions

#GP(0) For an illegal memory operand effective address in the CS, DS,

ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1.

ADDSD—Add Scalar Double-Precision Floating-Point Values

Vol. 2A 3-39

INSTRUCTION SET REFERENCE, A-M

#UD If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:E DX.SSE 2[bit 26] = 0. If the LOCK prefix is used.

#AC(0) If alignment checking is enabled and an unaligned memory

reference is made while the current privilege level is 3.

Real-Address Mode Exceptions

GP(0) If any part of the operand lies outside the effective address

space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0.

If CR0.EM[bit 2] = 1.

If CR4.OSFXSR[bit 9] = 0.

If CPUID.01H:E DX.SSE 2[bit 26] = 0.

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

Same exceptions as in real address mode. #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory

reference is made.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-

canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CRO.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1.

3-40 Vol. 2A ADDSD—Add Scalar Double-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-M

#UD If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.

#AC(0) If alignment checking is enabled and an unaligned memory

reference is made while the current privilege level is 3.

ADDSD—Add Scalar Double-Precision Floating-Point Values

Vol. 2A 3-41

INSTRUCTION SET REFERENCE, A-M

ADDSS—Add Scalar Single-Precision Floating-Point Values

Opcode Instruction 64-Bit

Mode

F3 0F 58 /r ADDSS xmm1, xmm2/m32 Valid Valid Add the low single-

Description

Adds the low single-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the single-precision floating-point result in the destination operand.

The source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. The three high-order doublewords of the destination operand remain unchanged. See Chapter 10 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an overview of a scal ar single-precision floating-point operation.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Compat/ Leg Mode

Description

precision floating-point value from xmm2/m32 to xmm1.

Operation

DEST[31:0] ← DEST[31:0] + SRC[31:0]; (* DEST[127:32] unchanged *)

Intel C/C++ Compiler Intrinsic Equivalent

ADDSS __m128 _mm_add_ss(__m128 a, __m128 b)

SIMD Floating-Point Exceptions

Overflow, Underflow , Inv alid, Precision, Denormal.

Protected Mode Exceptions

#GP(0) For an illegal memory operand effective address in the CS, DS,

ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CRO.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1.

3-42 Vol. 2A ADDSS—Add Scalar Single-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-M

#UD If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.

#AC(0) If alignment checking is enabled and an unaligned memory

reference is made while the current privilege level is 3.

Real-Address Mode Exceptions

GP(0) If any part of the operand lies outside the effective address

space from 0 to FFFFH. #NM If CRO.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0.

If CR0.EM[bit 2] = 1.

If CR4.OSFXSR[bit 9] = 0.

If CPUID.01H:EDX.SSE[bit 25] = 0.

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

Same exceptions as in real address mode. #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory

reference is made.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-

canonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CRO.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1.

ADDSS—Add Scalar Single-Precision Floating-Point Values

Vol. 2A 3-43

INSTRUCTION SET REFERENCE, A-M

#UD If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.

#AC(0) If alignment checking is enabled and an unaligned memory

reference is made while the current privilege level is 3.

3-44 Vol. 2A ADDSS—Add Scalar Single-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-M

ADDSUBPD—Packed Double-FP Add/Subtract

Opcode Instruction 64-Bit

Mode

66 0F D0 /r ADDSUBPD xmm1, xmm2/m128 Valid Valid Add/subtract

Description

Adds the double-precision floating-point values in the high quadword of the source and destination operands and stores the result in the high quadword of the destination operand.

Subtracts the double-precision floating-point value in the low quadword of the source operand from the low quadword of the destination operand and stores the result in the low quadword of the destination operand. See Figure 3-3.

The source operand can be a 128-bit memory location or an XMM register . The destination operand is an XMM register.

Compat/ Leg Mode

Description

double-precision floating-point values from xmm2/m128 to xmm1.

$''68%3'[PP[PPP

>@

[PP>@[PPP>@ [PP>@[PPP>@

>@ >@

>@

[PPP

5(68/7 [PP

20

Figure 3-3. ADDSUBPD—Packed Double-FP Add/Subtract

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

ADDSUBPD—Packed Double-FP Add/Subtract

Vol. 2A 3-45

INSTRUCTION SET REFERENCE, A-M

Operation

xmm1[63:0] = xmm1[63:0] − xmm2/m128[63:0]; xmm1[127:64]

= xmm1[127:64] + xmm2/m128[127:64];

Intel C/C++ Compiler Intrinsic Equivalent

ADDSUBPD __m128d _mm_addsub_pd(__m128d a, __m128d b)

Exceptions

When the source operand is a memory oper and, it must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.

SIMD Floating-Point Exceptions

Overflow, Underflow , Inv alid, Precision, Denormal.

Protected Mode Exceptions

#GP(0) For an illegal memory operand effective address in the CS, DS,

ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary ,

regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM For an unmasked Streaming SIMD Extensions numeric excep-

tion, CR4.OSXMMEXCPT[bit 10] = 1. #UD If CR0.EM is 1.

For an unmasked Streaming SIMD Extensions numeric excep-

tion (CR4.OSXMMEXCPT[bit 10] = 0).

If CR4.OSFXSR[bit 9] = 0.

If CPUID.01H:ECX.SSE3[bit 0] = 0.

If the LOCK prefix is used.

Real Address Mode Exceptions

GP(0) If any part of the operand would lie outside of the effective

address space from 0 to 0FFFFH.

If a memory operand is not aligned on a 16-byte boundary ,

regardless of segment. #NM If TS bit in CR0 is 1. #XM For an unmasked Streaming SIMD Extensions numeric excep-

tion, CR4.OSXMMEXCPT[bit 10] = 1.

3-46 Vol. 2A ADDSUBPD—Packed Double-FP Add/Subtract

INSTRUCTION SET REFERENCE, A-M

#UD If CR0.E M[bit 2] = 1.

For an unmasked Streaming SIMD Extensions numeric ex ception (CR4.OSXMMEXCPT[bit 10] = 0).

If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.

Virtual 8086 Mode Exceptions

GP(0) If any part of the operand would lie outside of the effective

address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary ,

regardless of segment. #NM If CR0.TS[bit 3] = 1. #XM For an unmasked Streaming SIMD Extensions numeric excep-

tion, CR4.OSXMMEXCPT[bit 10] = 1. #UD If CR0.E M[bit 2] = 1.

For an unmasked Streaming SIMD Extensions numeric ex cep-

tion (CR4.OSXMMEXCPT[bit 10] = 0).

If CR4.OSFXSR[bit 9] = 0.

If CPUID.01H:ECX.SSE3[bit 0] = 0.

If the LOCK prefix is used. #PF(fault-code) For a page fault.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-

canonical form. #GP(0) If the memory address is in a non-canonical form.

If memory operand is not aligned on a 16-byte boundary ,

regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1.

ADDSUBPD—Packed Double-FP Add/Subtract

Vol. 2A 3-47

INSTRUCTION SET REFERENCE, A-M

#UD If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.

3-48 Vol. 2A ADDSUBPD—Packed Double-FP Add/Subtract

INSTRUCTION SET REFERENCE, A-M

ADDSUBPS—Packed Single-FP Add/Subtract

Opcode Instruction 64-Bit

Mode

F2 0F D0 /r ADDSUBPS xmm1, xmm2/m128 Valid Valid Add/subtract single-

Description

Adds odd-numbered single-precision floating-point values of the source operand (second operand) with the corresponding single-precision floating-point values from the destination operand (first operand); stores the result in the odd-numbered values of the destina tion oper and.

Subtracts the even-numbered single-precision floating-point values in the source operand from the corresponding single-precision floating values in the destination operand; stores the result into the even-numbered values of the destination operand.

The source operand can be a 128-bit memory location or an XMM register . The destination operand is an XMM register. See Figure 3-4.

Compat/ Leg Mode

Description

precision floatingpoint values from

xmm2/m128 to xmm1.

$''68%36[PP[PPP

>@

[PP>@

[PPP>@

>@ >@ >@ >@

>@

[PP>@[PP

P>@

>@

[PP>@

[PPP>@

>@

[PP>@

[PPP>@

[PP P

5(68/7 [PP

20

Figure 3-4. ADDSUBPS—Packed Single-FP Add/Subtract

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

ADDSUBPS—Packed Single-FP Add/Subtract

Vol. 2A 3-49

INSTRUCTION SET REFERENCE, A-M

Operation

xmm1[31:0] = xmm1[31:0] − xmm2/m128[31:0]; xmm1[63:32] xmm1[95:64] xmm1[127:96]

= xmm1[63:32] + xmm2/m128[63:32]; = xmm1[95:64] − xmm2/m128[95:64];

= xmm1[127:96] + xmm2/m128[127:96];

Intel C/C++ Compiler Intrinsic Equivalent

ADDSUBPS __m128 _mm_addsub_ps(__m128 a, __m128 b)

Exceptions

When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.

SIMD Floating-Point Exceptions

Overflow, Underflow , Inv alid, Precision, Denormal.

Protected Mode Exceptions

#GP(0) For an illegal memory operand effective address in the CS, DS,

ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary ,

regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM For an unmasked Streaming SIMD Extensions numeric excep-

tion, CR4.OSXMMEXCPT[bit 10] = 1. #UD If CR0.EM[bit 2] = 1.

For an unmasked Streaming SIMD Extensions numeric excep-

tion (CR4.OSXMMEXCPT[bit 10] = 0).

If CR4.OSFXSR[bit 9] = 0.

If CPUID.01H:ECX.SSE3[bit 0] = 0.

If the LOCK prefix is used.

Real Address Mode Exceptions

GP(0) If any part of the operand would lie outside of the effective

address space from 0 to 0FFFFH.

If a memory operand is not aligned on a 16-byte boundary ,

regardless of segment. #NM If CR0.TS[bit 3] = 1.

3-50 Vol. 2A ADDSUBPS—Packed Single-FP Add/Subtract

INSTRUCTION SET REFERENCE, A-M

#XM For an unmasked Streaming SIMD Extensions numeric excep-

tion, CR4.OSXMMEXCPT[bit 10] = 1.

#UD If CR0.EM[bit 2] = 1.

For an unmasked Streaming SIMD Extensions numeric ex ception (CR4.OSXMMEXCPT[bit 10] = 0).

If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.

Virtual 8086 Mode Exceptions

GP(0) If any part of the operand would lie outside of the effective

address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary ,

regardless of segment. #NM If CR0.TS[bit 3] = 1. #XM For an unmasked Streaming SIMD Extensions numeric excep-

tion, CR4.OSXMMEXCPT[bit 10] = 1. #UD If CR0.EM[bit 2] = 1.

For an unmasked Streaming SIMD Extensions numeric ex cep-

tion (CR4.OSXMMEXCPT[bit 10] = 0).

If CR4.OSFXSR[bit 9] = 0.

If CPUID.01H:ECX.SSE3[bit 0] = 0.

If the LOCK prefix is used.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-

canonical form. #GP(0) If the memory address is in a non-canonical form.

If memory operand is not aligned on a 16-byte boundary ,

regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1.

ADDSUBPS—Packed Single-FP Add/Subtract

Vol. 2A 3-51

INSTRUCTION SET REFERENCE, A-M

#UD If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used.

3-52 Vol. 2A ADDSUBPS—Packed Single-FP Add/Subtract

INSTRUCTION SET REFERENCE, A-M

AND—Logical AND

Opcode Instruction 64-Bit

Mode

24 ib AND AL, imm8 Valid Valid AL AND imm8.

25 iw AND AX, imm16 Valid Valid AX AND imm16.

25 id AND EAX, imm32 Valid Valid EAX AND imm32.

REX.W + 25 id AND RAX, imm32 Valid N.E. RAX AND imm32 sign-

80 /4 ib AND r/m8, imm8 Valid Valid r/m8 AND imm8.

REX + 80 /4 ib AND r/m8

, imm8 Valid N.E. r/m64 AND imm8 (sign-

81 /4 iw AND r/m16, imm16 Valid Valid r/m16 AND imm16.

81 /4 id AND r/m32, imm32 Valid Valid r/m32 AND imm32.

REX.W + 81 /4 idAND r/m64, imm32 Valid N.E. r/m64 AND imm32 sign

83 /4 ib AND r/m16, imm8 Valid Valid r/m16 AND imm8 (sign-

83 /4 ib AND r/m32, imm8 Valid Valid r/m32 AND imm8 (sign-

REX.W + 83 /4 ibAND r/m64, imm8 Valid N.E. r/m64 AND imm8 (sign-

20 /r AND r/m8, r8 Valid Valid r/m8 AND r8.

REX + 20 /r AND r/m8

, r8

Valid N.E. r/m64 AND r8 (sign-

21 /r AND r/m16, r16 Valid Valid r/m16 AND r16.

21 /r AND r/m32, r32 Valid Valid r/m32 AND r32.

REX.W + 21 /r AND r/m64, r64 Valid N.E. r/m64 AND r32.

22 /r AND r8, r/m8 Valid Valid r8 AND r/m8.

REX + 22 /r AND r8

, r/m8

Valid N.E. r/m64 AND r8 (sign-

23 /r AND r16, r/m16 Valid Valid r16 AND r/m16.

23 /r AND r32, r/m32 Valid Valid r32 AND r/m32.

REX.W + 23 /r AND r64, r/m64 Valid N.E. r64 AND r/m64.

NOTES:

* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is

used: AH, BH, CH, DH.

Comp/Leg Mode

Description

extended to 64-bits.

extended).

extended to 64-bits.

extended).

AND—Logical AND

Vol. 2A 3-53

INSTRUCTION SET REFERENCE, A-M

Description

Performs a bitwise AND operation on the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result is set to 1 if both corresponding bits of the first and second operands are 1; otherwise, it is set to 0.

This instruction can be used with a LOCK prefix to allow the it to be executed atomically.

Operation

DEST ← DEST AND SRC;

Flags Affected

The OF and CF flags are cleared; the SF, ZF , and PF flags are set according to the result. The state of the AF flag is undefined.

Protected Mode Exceptions

#GP(0) If the destination operand points to a non-writable segment.

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0) If a memory operand effective address is outside the SS

segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory

reference is made while the current privilege level is 3. #UD If the LOCK prefix is used but the destination is not a memory

operand.

Real-Address Mode Exceptions

#GP If a memory operand effective address is outside the CS, DS,

ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS

segment limit.

3-54 Vol. 2A AND—Logical AND

Intel 253666-024US User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 IA-32 PROCESSORS COVERED IN THIS MANUAL

1.3 NOTATIONAL CONVENTIONS

1.3.1 Bit and Byte Order

1.3.2 Reserved Bits and Software Compatibility

1.3.3 Instruction Operands

1.3.4 Hexadecimal and Binary Numbers

1.3.5 Segmented Addressing

1.3.6 Exceptions

1.3.7 A New Syntax for CPUID, CR, and MSR Values

1.4 RELATED LITERATURE

2.1 INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE, AND VIRTUAL-8086 MODE

2.1.1 Instruction Prefixes

2.1.2 Opcodes

2.1.3 ModR/M and SIB Bytes

2.1.4 Displacement and Immediate Bytes

2.1.5 Addressing-Mode Encoding of ModR/M and SIB Bytes

2.2 IA-32E MODE

2.2.1 REX Prefixes

2.2.1.1 Encoding

2.2.1.2 More on REX Prefix Fields

2.2.1.3 Displacement

2.2.1.4 Direct Memory-Offset MOVs

2.2.1.5 Immediates

2.2.1.6 RIP-Relative Addressing

2.2.1.7 Default 64-Bit Operand Size

2.2.2 Additional Encodings for Control and Debug Registers

3.1 INTERPRETING THE INSTRUCTION REFERENCE PAGES

3.1.1 Instruction Format

3.1.1.1 Opcode Column in the Instruction Summary Table

3.1.1.2 Instruction Column in the Opcode Summary Table

3.1.1.3 64-bit Mode Column in the Instruction Summary Table

3.1.1.5 Description Column in the Instruction Summary Table

3.1.1.6 Description Section

3.1.1.7 Operation Section

3.1.1.8 Intel® C/C++ Compiler Intrinsics Equivalents Section

3.1.1.9 Flags Affected Section

3.1.1.10 FPU Flags Affected Section

3.1.1.11 Protected Mode Exceptions Section

3.1.1.12 Real-Address Mode Exceptions Section

3.1.1.13 Virtual-8086 Mode Exceptions Section

3.1.1.14 Floating-Point Exceptions Section

3.1.1.15 SIMD Floating-Point Exceptions Section

3.1.1.16 Compatibility Mode Exceptions Section

3.1.1.17 64-Bit Mode Exceptions Section

3.2 INSTRUCTIONS (A-M)