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Table of Contents
Page
Specifications 3
Test and Alignment Procedure 8
Block Diagram 13
Schematic Diagram 14
Printed Circuit Board 23
Channel Frequency Charts 25
Parts List 40
Semiconductor Voltage Chart 45
Semiconductor Lead Assignment and Block Diagram 53
Exploded View Parts List 56
Exploded View 57
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Frequency Range………………………………...…………………………..……………......25.615 to 30.105 MHz
FrequencyControl………………………………………………………………………………..…………..…….……PLL
Operating Temperature Range……………………………………..……..……………………………-10° / +50°C
DC Input Voltage…………………………………………………....………………………..………....9.0 V DC ±15%
Size………………………………………………………………….……..………..….…140(L) X 60(W) X 30(H) mm
Weight………………………………………………………………………………..…………..……...……..……0.50 kg
2. RECEIVER
Receiving System……………………………….…………………………....Dual Conversion Super Heterodyne
Intermediate Frequency…………………………………………...…….…1
Sensitivity……………………………………….…..............................….0.5 µV for 20 db SINAD in FM mode
Audio Distortion……………………………………………………….….……..…………….Less Than 8% @ 1 KHz
Image Rejection……………………………………….…………………..………………………………………...60 dB
Adjacent Channel Rejection………………………………………….…………………………………………....60 dB
Signal/ Noise Ratio…………………………….…………………………….…………………………………..….45 dB
Current Drain at standby……………………….…………………………………………………………..……..60 mA
3. TRANSMITTER
Output Power…………………………………………………………………………………..……...….4W @ 9.0 V DC
Modulation………………………………………………………………..………….…...………FM: 1.6 KHz ±0.2 KHz
Frequency response…………………………………………….…................................From 300 Hz to 3.0 KHz
Output impedance………………………………………………………………………………RF 50 ohm Unbalance
Signal/ Noise Ratio…………………………………………………………………………………..………..40 dB MIN
Current Drain…………………………………………………………………………………………….….…….1300 mA
st
IF: 10.695 MHz, 2nd IF: 455 MHZ
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OPERATION INSTRUCTIONS
Having properly installed your batteries and hooked-up the antenna, you are now ready to operate your radio for
optimum reception and voice transmission.
Turn the power “ON” with ON/OFF switch.
Set the desired channel.
Adjust the squelch control knob to reduce any undesirable background noise when no signal is being received. To
do this, select a channel where no signal are present, or wait until signals cease on your channel. Then, rotate
the squelch control knob clockwise to a point where the background noise disappears.
Note: When the squelch is set properly, the speaker will remain quiet until a signal is
received. In order to receive weak signals, do not set the squelch too high.
Adjust the volume to the desired listening level.
To Transmit
Press and hold the push-to-talk button. Speak slowly and clearly in a normal voice two to three inches from the
microphone. A buit-in modulation control circuit will automatically adjust the microphone input level. There is no
need to speak loudly.
To Receive
Release the push-to-talk button.
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THEORY OF OPERATIONS
TRANSMITTER
A. RF Amplification
The output of double AMP Q201 is fed through tuning T203 and T204 to the base of pre driver AMP Q202. The
output is then supplied to RF driver AMP Q203. The output of Q203 is supplied with tuning circuit L204 and C214,
C215, C216 and goes to the base of final RF AMP Q204. The output of Q204 is supplied to the antenna through
L-C tuning circuit.
B. Circuit for Suppression of Spurious Radiation
The tuning circuit between the output of final AMP Q204 and antenna, 5-stage “PHI” network C221, C219, C220,
L206, C223, C245, L207, C241, C228, C240, L208, C242, C230, C229, L209, C234, C233, C232, L210, C243,
C235, C236 serves as a spurious radiation suppressor . This network also serves to match the impedance
between TX power AMP Q204 and the antenna.
C. Circuit for Limiting Power
After finished all alignment, the constant voltage supply circuit limits the available power 4 W or slightly less.
RV501 and corresponding three transistors Q509, Q502, Q501 control supply voltage of RF amplifier and other
circuits.
Tune all the trimmer parts for maximum indication of RF power meter and adjust RV501 to make 4 w indication
of RF power meter.
The tuning is adjusted so that the actual power is from 3.8 to 4.0 W. There are no other additional controls for
adjusting the TX output power.
D. Modulation Control
a. FM
The mic input is fed to audio amplifier IC KIA324 which drives modulation varicap diode D302 in the VCO circuit.
RV701 limits the incoming modulation audio levels to inhibit over modulation. While reading the modulation factor
on the modulation analyzing equipment, adjust RV701 shall not exceed +/-1.6 KHz/Dev. After 20 dB up from
1.25 KHz/1.2 KHz/Dev. Audio level
b. AM
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Modulation signal is fed to audio amplifier IC KIA324 and goes to TX voltage regulate circuit Q509, Q502, Q501 to
make nominal signal level to achieve wanted modulation. To control incoming audio signal, R272 and
corresponding ALC circuit limits the modulation shall not exceed +/-60% adjust RV702 +/-60% modulation under
1.0 KHz AF 60% mod plus 20 dB of audio signal.
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E. Receiver
CB receiver is dual conversion supper-heterodyne type with the first IF 10.695 MHz and second IF 455 KHz.
Receiver is separated two blocks, 1
The PLL synthesizer supplies first local frequency 16.270 ~ 16.710 MHz.(for EU) and 16.90625 MHz ~ 17.29625
MHz (for UK) With the provided first local frequencies Q102,Q103 mixes the incoming RF signal to generate first
IF signal. Mixed signals were filtered with the CF101 (10.695 MHz) crystal filter and other tuning circuits. Output
signal of mixer is filtered with CF102 (455 KHz ceramic filter). The 455 KHz signal from the 2
amplified and limits internally. After amplification the signals fed the quadrature detector loop T104. Then we can
see the recovered audio signals on Pin 12 for FM and Pin 13 for AM of IC1.
st
IF section and 2nd IF section.
nd
IF filter was
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TROUBLE SHOOTING HINTS
Symptom Probable Cause Remedy
Unit does not work
at all
No output from
speaker at all
• Defective power switch VR601.
• Empty Battery.
• Broken wire Battery.
• Defective D501.
• Defective external speaker jack.
• Wire speaker open.
• Defective internal speaker.
• Defective VR601, IC601, Q601 other components.
• Replace
• Replace
• Replace
• Replace
• Repair or replace
• Replace
• Replace
• Replace the defective
components.
No noise on
speaker
Squelch does not
work
No modulation
LCD display does
not work
• Measure all the voltage of IC601,102 with voltage
chart
Connect RF power meter
With dummy load to
spectrum analyzer through
coupler /-40 dB
Attenuator to EXT-ANT jack
on the set
(Figure 4).
Connect dummy load and
frequency counter though
coupler to RF power meter.
Connect RF power meter to
EXT-ANT jack on the set
(Figure 5).
Connect dummy load and
oscilloscope through
Coupler to RF power meter
connect audio generator to
microphone jack
(Figure 6).
At no modulation,
compare the level o
fundamental frequency
to the level of harmonic
frequency. Suppression
of the 2
frequency level must be
X302 Be sure that the
indication of the
transmitter frequency is
27.185MHz±300Hz on
the frequency counter.
RV501 Adjust until
3.6-4 Watts
nd
harmonic
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Figure 3
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Figure 4
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Auto Squelch adjustment
MIC : Receive
Volume : 600mV
Squelch : Auto Squelch on
CH selector : 19
3
RFSG:27.185MHz, 1kHZ
1uV, 1.2K DEV.
Connect RF signal
generator to EXT-ANT
Jack. Connect SSVM and
distortion meter to EXT
speaker jack with 8 ohm
dummy load
(Figure 7).
Connect RF signal
generator to EXT-ANT
Jack. Connect SSVM and
distortion meter to EXT
speaker jack with 8 ohm
dummy load
(Figure 7).
RV101 Adjust until the audio
output appears.
RV103 Adjust until the audio
output disappears.
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Figure 5
Figure 6
Figure 7
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T
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PLL CIRCUIT BLOCK DIAGRAM
1. INTRODUCTION
The frequencies for transmitter and receiver first local frequencies are all derived from a single 10.240 MHz
crystal by means of a phase locked loop. The first local oscillator frequencies are 16.270 MHz (CH 1) to 16.710
MHz (CH 40) for EU and 16.90625 MHz (CH 1) to 17.29625 MHz (CH 40) for UK. The second local frequency is
fixed at 10.240 MHz to generate second IF 455 KHz. During transmit, The VCO of the PLL operates 13.4825 MHz
(CH 1) to 13.7025 MHz (CH 40) for EU, 13.800625 MHz (CH 1) to 13.995625 MHz (CH 40) for UK the VCO
frequency goes to the double circuit Q201, T203, T204 which doubles the frequency to generate 26.965 MHz (CH
1) to 27.405 MHz (CH 40) for EU and 27.60125 MHz (CH 1) to 27.99125 MHz (CH 40) for UK
Q 201
VCO
T203,T204
Doubler
o Transmitter
13.4825 MHz (CH 1) EU 26.965 MHz (CH 1)
13.7025 MHz (CH 40) EU 27.405 MHz (CH 40)
13.800625 MHz (CH 1) UK 27.60125 MHz (CH 1)
13.995625 MHz (CH 40) UK 27.99125 MHz (CH 40)
The VCO operating frequency for the receiver is 16.270, 16.90625 MHz (CH 1) to 16.710, 17.29625 MHz (CH 40)
as the first local oscillator, injected through the buffer AMP Q302 into the first fed balanced mixer Q102, Q103.
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2. BASIC SYNTHESIZER SCHEME
The crystal frequency (10.240MHz) is divided by 1800 times to make 2.5 KHz which is fed to one side of the
phase detector. The VCO output is divided by a programmable divider, and fed to other side of the phase
detector Pin 11 of IC302. The feedback loop is closed by passing the phase detector output through an active low
pass filter and using the output to control the VCO frequency through varicap diode D301.
Under locked conditions, both of phase detector input signal must be indential at 2.5 KHz. The VCO frequency is
then given by:
FVCO / N = 0.0025 MHz or FVCO = 0.0025 x N MHz
Since “N” is an integer, the VCO frequency can be stepped up with 2.5 KHz increments. By suitable choice of “N”
the desired output frequency can be obtained.
Channel 1 Channel 40
Function
N FVCO N FVCO
Transmit 5393 13.4825 5481 13.7025
EU
Receive 6508 16.2700 6684 16.7100
Transmit 5520.25 13.800625 5598.25 13.995625
UK
Receive 6762.50 16.90625 6918.5 17.29625
(SEE TABLE FOR OTHER CHANNELS)
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The VCO frequency goes to the double circuit, which doubles the incoming signals.
Transmit
_______
Transmit
_______
Since all frequencies are obtained from the crystal controlled PLL oscillator, all outputs are coherent with the
CH 1, 13.4825 MHz
CH 1, 13.800625 MHz
CH 40, 13.7025 MHz
CH 40, 13.995625 MHz
Double output Frequency
26.965 MHz
27.60125 MHz
27.405 MHz
27.99125 MHz
crystal oscillator frequency and maintaining the same percentage accuracy.
INTERNAL BLOCK DIAGRAM
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