INFINEON XC886, XC888CLM User Manual

8-Bit

XC886/888CLM

8-Bit Single Chip Microcontroller

Data Sheet

V1.2 2009-07

Microcontrollers

Edition 2009-07

Published by Infineon Technologies AG 81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

8-Bit

XC886/888CLM

8-Bit Single Chip Microcontroller

Data Sheet

V1.2 2009-07

Microcontrollers

XC886/888CLM

XC886/888 Data Sheet

Revision History: V1.2 2009-07

Previous Versions: V1.0, V1.1

Page Subjects (major changes since last revision)

Changes from V1.1 2009-01 to V1.2 2009-07

89 Note on LIN baud rate detection is added.

92 RXD slave line in SSC block diagram is updated.

108 Electrical parameters are now valid for all variants, previous note on

exclusion of ROM variants is removed.

116 Symbol for ADC error parameters are updated.

120 Power supply current parameters for ROM variants are updated.

128 Test condition for the on-chip oscillator short term deviation is updated.

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:

mcdocu.comments@infineon.com

Data Sheet V1.2, 2009-07

XC886/888CLM

Table of Contents

1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1 Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.1 Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2.1.1 Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2.2 Special Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2.2.1 Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2.2.2 Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2.3 Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2.3.1 Password Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2.4 XC886/888 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2.4.1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2.4.2 MDU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2.4.3 CORDIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.2.4.4 System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.2.4.5 WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.2.4.6 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.2.4.7 ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.2.4.8 Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.2.4.9 Timer 21 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.2.4.10 CCU6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.2.4.11 UART1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.2.4.12 SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2.4.13 MultiCAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2.4.14 OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.3 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.3.1 Flash Bank Sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.3.2 Parallel Read Access of P-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.3.3 Flash Programming Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.4 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.4.1 Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.4.2 Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.4.3 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.5 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Data Sheet I-1 V1.2, 2009-07

XC886/888CLM

Table of Contents

3.6 Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . . 68

3.7 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.7.1 Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.7.2 Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.8 Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.8.1 Recommended External Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . 75

3.8.2 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.9 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.10 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.11 Multiplication/Division Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.12 CORDIC Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.13 UART and UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.13.1 Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.13.2 Baud Rate Generation using Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.14 Normal Divider Mode (8-bit Auto-reload Timer) . . . . . . . . . . . . . . . . . . . . . 88

3.15 LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.15.1 LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.16 High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . 91

3.17 Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.18 Timer 2 and Timer 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.19 Capture/Compare Unit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

3.20 Controller Area Network (MultiCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

3.21 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

3.21.1 ADC Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

3.21.2 ADC Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

3.22 On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

3.22.1 JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

3.23 Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.1.2 Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

4.1.3 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.2.1 Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.2.2 Supply Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

4.2.3 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.2.3.1 ADC Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

4.2.4 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

4.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

4.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

4.3.2 Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Data Sheet I-2 V1.2, 2009-07

XC886/888CLM

Table of Contents

4.3.3 Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4.3.4 On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

4.3.5 External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

4.3.6 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

4.3.7 SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5 Package and Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.2 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.3 Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Data Sheet I-3 V1.2, 2009-07

XC886/888CLM8-Bit Single Chip Microcontroller

1 Summary of Features

The XC886/888 has the following features:

• High-performance XC800 Core – compatible with standard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers

• On-chip memory – 12 Kbytes of Boot ROM – 256 bytes of RAM – 1.5 Kbytes of XRAM – 24/32 Kbytes of Flash; or

24/32 Kbytes of ROM, with additional 4 Kbytes of Flash (includes memory protection strategy)

• I/O port supply at 3.3 V or 5.0 V and core logic supply at 2.5 V (generated by embedded voltage regulator)

(more features on next page)

Flash or ROM

24K/32K x 8

Boot ROM

12K x 8

XRAM

1.5K x 8

RAM

256 x 8

1) All ROM devices come with an additional 4K x 8 Flash

Timer 0

16-bit

On-Chip Debug Support

XC800 Core

Timer 1

16-bit

Timer 2

16-bit

Timer 21

16-bit

UART

Capture/Compare Unit

Compare Unit

Watchdog

Timer

UART1

SSC

16-bit

ADC

10-bit

8-channel

8-bit Digital I/O

Port 0

Port 1

Port 2

Port 3

Port 4Port 5MDU CORDIC MultiCAN

8-bit Digital I/O

8-bit Digital/ Analog Input

8-bit Digital I/O

Figure 1 XC886/888 Functional Units

Data Sheet 1 V1.2, 2009-07

XC886/888CLM

Summary of Features

Features: (continued)

• Power-on reset generation

• Brownout detection for core logic supply

• On-chip OSC and PLL for clock generation – PLL loss-of-lock detection

• Power saving modes – slow-down mode – idle mode – power-down mode with wake-up capability via RXD or EXINT0 – clock gating control to each peripheral

• Programmable 16-bit Watchdog Timer (WDT)

•Six ports – Up to 48 pins as digital I/O – 8 pins as digital/analog input

• 8-channel, 10-bit ADC

• Four 16-bit timers – Timer 0 and Timer 1 (T0 and T1) – Timer 2 and Timer 21 (T2 and T21)

• Multiplication/Division Unit for arithmetic operations (MDU)

• Software libraries to support floating point and MDU calculations

• CORDIC Coprocessor for computation of trigonometric, hyperbolic and linear functions

• MultiCAN with 2 nodes, 32 message objects

• Capture/compare unit for PWM signal generation (CCU6)

• Two full-duplex serial interfaces (UART and UART1)

• Synchronous serial channel (SSC)

• On-chip debug support – 1 Kbyte of monitor ROM (part of the 12-Kbyte Boot ROM) – 64 bytes of monitor RAM

• Packages: – PG-TQFP-48 – PG-TQFP-64

• Temperature range – SAF (-40 to 85 °C) – SAK (-40 to 125 °C)

Data Sheet 2 V1.2, 2009-07

XC886/888CLM

Summary of Features

XC886/888 Variant Devices

The XC886/888 product family features devices with different configurations, program memory sizes, package options, power supply voltage, temperature and quality profiles (Automotive or Industrial), to offer cost-effective solutions for different application requirements.

The list of XC886/888 device configurations are summarized in Table 1. For each configuration, 2 types of packages are available:

• PG-TQFP-48, which is denoted by XC886 and;

• PG-TQFP-64, which is denoted by XC888.

Table 1 Device Configuration

Device Name CAN

Module

LIN BSL Support

MDU Module

XC886/888 No No No

XC886/888C Yes No No

XC886/888CM Yes No Yes

XC886/888LM No Yes Yes

XC886/888CLM Yes Yes Yes

Note: For variants with LIN BSL support, only LIN BSL is available regardless of the

availability of the CAN module.

From these 10 different combinations of configuration and package type, each are further made available in many sales types, which are grouped according to device type, program memory sizes, power supply voltage, temperature and quality profile (Automotive or Industrial), as shown in Table 2.

Table 2 Device Profile

Sales Type Device

Type

Program Memory (Kbytes)

Power Supply (V)

Temperature (°C)

Quality Profile

SAK-XC886*/888*-8FFA 5V Flash 32 5.0 -40 to 125 Automotive

SAK-XC886*/888*-6FFA 5V Flash 24 5.0 -40 to 125 Automotive

SAF-XC886*/888*-8FFA 5V Flash 32 5.0 -40 to 85 Automotive

SAF-XC886*/888*-6FFA 5V Flash 24 5.0 -40 to 85 Automotive

SAF-XC886*/888*-8FFI 5V Flash 32 5.0 -40 to 85 Industrial

SAF-XC886*/888*-6FFI 5V Flash 24 5.0 -40 to 85 Industrial

Data Sheet 3 V1.2, 2009-07

Table 2 Device Profile (cont’d)

XC886/888CLM

Summary of Features

Sales Type Device

Type

Program Memory (Kbytes)

Power Supply (V)

Temperature (°C)

Quality Profile

SAK-XC886*/888*-8FFA 3V3 Flash 32 3.3 -40 to 125 Automotive

SAK-XC886*/888*-6FFA 3V3 Flash 24 3.3 -40 to 125 Automotive

SAF-XC886*/888*-8FFA 3V3 Flash 32 3.3 -40 to 85 Automotive

SAF-XC886*/888*-6FFA 3V3 Flash 24 3.3 -40 to 85 Automotive

SAF-XC886*/888*-8FFI 3V3 Flash 32 3.3 -40 to 85 Industrial

SAF-XC886*/888*-6FFI 3V3 Flash 24 3.3 -40 to 85 Industrial

Note: The asterisk (*) above denotes the device configuration letters from Table 1.

Corresponding ROM derivatives will be available on request.

Note: For variants with LIN BSL support, only LIN BSL is available regardless of the

availability of the CAN module.

As this document refers to all the derivatives, some description may not apply to a specific product. For simplicity, all versions are referred to by the term XC886/888 throughout this document.

Ordering Information

The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temperature range, and the supply voltage

• The package and the type of delivery

For the available ordering codes for the XC886/888, please refer to your responsible sales representative or your local distributor.

Note: The ordering codes for the Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Data Sheet 4 V1.2, 2009-07

XC886/888CLM

General Device Information

2 General Device Information

Chapter 2 contains the block diagram, pin configurations, definitions and functions of the

XC886/888.

2.1 Block Diagram

The block diagram of the XC886/888 is shown in Figure 2.

TMS

MBC

RESET

DDP

SSP

DDC

SSC

XTAL1 XTAL2

XC886/888

12-Kbyte

Boot ROM

256-byte RAM

64-byte monitor

1.5-Kbyte XRAM

24/32-Kbyte

Flash or ROM

Clock Generator

9.6 MHz

On-chip OSC

RAM

PLL

Internal Bus

XC800 Core

T0 & T1 UART

UART1CORDIC

SSCMDU

WDT

OCDS

Timer 2

Timer 21

CCU6

MultiCAN

Port 0Port 1Port 2Port 3

ADC

Port 4Port 5

P0.0 - P0.7

P1.0 - P1.7

P2.0 - P2.7

AREF

AGND

P3.0 - P3.7

P4.0 - P4.7

1) Includes 1-Kbyte monitor ROM

P5.0 - P5.7

2) The 24/32-Kbyte ROM has an additional 4-Kbyte Flash

Figure 2 XC886/888 Block Diagram

Data Sheet 5 V1.2, 2009-07

General Device Information

2.2 Logic Symbol

The logic symbols of the XC886/888 are shown in Figure 3.

XC886/888CLM

AREF

AGND

RESET

MBC

TMS

XTAL1

XTAL2

DDP

XC886

DDC

SSP

DDP

SSP

Port 0 8-Bi

Port 0 7-Bit

Port 1 8-Bit

Port 2 8-Bit

Port 3 8-Bit

Port 4 3-Bit

SSC

AREF

AGND

RESET

MBC

TMS

XTAL1

XTAL2

DDC

XC888

Port 1 8-Bi

Port 2 8-Bi

Port 3 8-Bi

Port 4 8-Bi

Port 5 8-Bi

SSC

Figure 3 XC886/888 Logic Symbol

Data Sheet 6 V1.2, 2009-07

XC886/888CLM

General Device Information

2.3 Pin Configuration

The pin configuration of the XC886, which is based on the PG-TQFP-48 package, is shown in package, is shown in Figure 5.

Figure 4, while that of the XC888, which is based on the PG-TQFP-64

P1.3

P1.4

P3.0

P3.1

P3.6

P3.7

P1.5

P4.3

36 35 34 33 32 31 30 29 28 27 26 25

P1.2

P1.0

P1.1

P2.7

P3.2

P3.3

P3.4

P3.5

RESET

SSP

DDP

MBC

P4.0

P4.1

P0.7

P0.3

XC886

123 456789101112

P0. 4

P0. 5

XTA L2

XTA L1

SSCVDDC

P1. 6

P1. 7

DDP

TMS

P0. 0

P0. 2

AREF

AGND

P2.6

P2.5

P2.4

P2.3

SSP

DDP

P2.2

P2.0

Figure 4 XC886 Pin Configuration, PG-TQFP-48 Package (top view)

Data Sheet 7 V1.2, 2009-07

XC886/888CLM

General Device Information

P1.3

P1.4

P3.0

P4.5

P4.6

P4.7

P3.1

P4.4

P3.6

P3.7

P1.5

P4.3

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P1.2

P1.0

P1.1

P2.7

P3.2

P3.3

P3.4

P3.5

RESET

SSP

DDP

MBC

P4.0

P4.1

P4.2

P0.7

P0.3

P0.4

XC888

1 2 3 4 5 6 7 8 9 10111213141516

AREF

AGND

P2.6

P2.5

P2.4

P2.3

SSP

DDP

P2.2

P2.0

P5.7

P5.6

P0.2

P0.0

P5.0

P0.5

XTA L2

P0.6

XTA L1

SSCVDDC

DDP

P5.1

P1.6

P1.7

P5.2

P5.4

P5.3

TMS

P5.5

Note: The pi ns shaded in blue are not av ailable in the PG-TQFP -48 package.

Figure 5 XC888 Pin Configuration, PG-TQFP-64 Package (top view)

Data Sheet 8 V1.2, 2009-07

XC886/888CLM

General Device Information

2.4 Pin Definitions and Functions

The functions and default states of the XC886/888 external pins are provided in Table 3.

Table 3 Pin Definitions and Functions

Symbol Pin Number

(TQFP-48/64)

Type Reset

State

Function

P0 I/O Port 0

Port 0 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, UART1, Timer Timer

P0.0 11/17 Hi-Z TCK_0

T12HR_1

CC61_1

CLKOUT_0 RXDO_1

P0.1 13/21 Hi-Z TDI_0

T13HR_1

RXD_1 RXDC1_0 COUT61_1

EXF2_1

21, MultiCAN and SSC.

JTAG Clock Input CCU6 Timer 12 Hardware Run Input Input/Output of Capture/Compare channel 1 Clock Output UART Transmit Data Output

JTAG Serial Data Input CCU6 Timer 13 Hardware Run Input UART Receive Data Input MultiCAN Node 1 Receiver Input Output of Capture/Compare channel 1 Timer 2 External Flag Output

P0.2 12/18 PU CTRAP_2

TDO_0 TXD_1

CCU6 Trap Input JTAG Serial Data Output UART Transmit Data Output/Clock Output

TXDC1_0

MultiCAN Node 1 Transmitter Output

P0.3 48/63 Hi-Z SCK_1

COUT63_1

SSC Clock Input/Output Output of Capture/Compare channel 3

RXDO1_0

Data Sheet 9 V1.2, 2009-07

UART1 Transmit Data Output

Table 3 Pin Definitions and Functions (cont’d)

XC886/888CLM

General Device Information

Symbol Pin Number

(TQFP-48/64)

P0.4 1/64 Hi-Z MTSR_1

Type Reset

State

Function

SSC Master Transmit Output/ Slave Receive Input

CC62_1

Input/Output of Capture/Compare channel 2

TXD1_0

UART1 Transmit Data Output/Clock Output

P0.5 2/1 Hi-Z MRST_1

SSC Master Receive Input/Slave

Transmit Output EXINT0_0 T2EX1_1 RXD1_0 COUT62_1

External Interrupt Input 0

Timer 21 External Trigger Input

UART1 Receive Data Input

Output of Capture/Compare

channel 2

P0.6 –/2 PU GPIO

P0.7 47/62 PU CLKOUT_1 Clock Output

Data Sheet 10 V1.2, 2009-07

Table 3 Pin Definitions and Functions (cont’d)

XC886/888CLM

General Device Information

Symbol Pin Number

(TQFP-48/64)

Type Reset

State

Function

P1 I/O Port 1

Port 1 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, Timer 0, Timer 1, Timer 2, Timer 21, MultiCAN and SSC.

P1.0 26/34 PU RXD_0

T2EX RXDC0_0

P1.1 27/35 PU EXINT3

T0_1 TDO_1 TXD_0

UART Receive Data Input

Timer 2 External Trigger Input

MultiCAN Node 0 Receiver Input

External Interrupt Input 3

Timer 0 Input

JTAG Serial Data Output

UART Transmit Data

Output/Clock Output TXDC0_0

MultiCAN Node 0 Transmitter

Output

P1.2 28/36 PU SCK_0 SSC Clock Input/Output

P1.3 29/37 PU MTSR_0

TXDC1_3

P1.4 30/38 PU MRST_0

EXINT0_1 RXDC1_3

P1.5 31/39 PU CCPOS0_1

EXINT5 T1_1 EXF2_0 RXDO_0

SSC Master Transmit

Output/Slave Receive Input

MultiCAN Node 1 Transmitter

Output

SSC Master Receive Input/

Slave Transmit Output

External Interrupt Input 0

MultiCAN Node 1 Receiver Input

CCU6 Hall Input 0

External Interrupt Input 5

Timer 1 Input

Timer 2 External Flag Output

UART Transmit Data Output

Data Sheet 11 V1.2, 2009-07

Table 3 Pin Definitions and Functions (cont’d)

XC886/888CLM

General Device Information

Symbol Pin Number

(TQFP-48/64)

Type Reset

State

Function

P1.6 8/10 PU CCPOS1_1

T12HR_0

EXINT6_0 RXDC0_2 T21_1

P1.7 9/11 PU CCPOS2_1

T13HR_0

T2_1 TXDC0_2

P1.5 and P1.6 can be used as a software chip select output for the SSC.

CCU6 Hall Input 1

CCU6 Timer 12 Hardware Run

Input

External Interrupt Input 6

MultiCAN Node 0 Receiver Input

Timer 21 Input

CCU6 Hall Input 2

CCU6 Timer 13 Hardware Run

Input

Timer 2 Input

MultiCAN Node 0 Transmitter

Output

Data Sheet 12 V1.2, 2009-07

Table 3 Pin Definitions and Functions (cont’d)

XC886/888CLM

General Device Information

Symbol Pin Number

(TQFP-48/64)

Type Reset

State

Function

P2 I Port 2

Port 2 is an 8-bit general purpose input-only port. It can be used as alternate functions for the digital inputs of the JTAG and CCU6. It is also used as the analog inputs for the ADC.

P2.0 14/22 Hi-Z CCPOS0_0

EXINT1_0 T12HR_2

TCK_1 CC61_3

AN0

P2.1 15/23 Hi-Z CCPOS1_0

EXINT2_0 T13HR_2

TDI_1 CC62_3

AN1

CCU6 Hall Input 0

External Interrupt Input 1

CCU6 Timer 12 Hardware Run

Input

JTAG Clock Input

Input of Capture/Compare

channel 1

Analog Input 0

CCU6 Hall Input 1

External Interrupt Input 2

CCU6 Timer 13 Hardware Run

Input

JTAG Serial Data Input

Input of Capture/Compare

channel 2

Analog Input 1

P2.2 16/24 Hi-Z CCPOS2_0

CTRAP_1 CC60_3

CCU6 Hall Input 2

CCU6 Trap Input

Input of Capture/Compare

channel 0 AN2

Analog Input 2

P2.3 19/27 Hi-Z AN3 Analog Input 3

P2.4 20/28 Hi-Z AN4 Analog Input 4

P2.5 21/29 Hi-Z AN5 Analog Input 5

P2.6 22/30 Hi-Z AN6 Analog Input 6

P2.7 25/33 Hi-Z AN7 Analog Input 7

Data Sheet 13 V1.2, 2009-07

Table 3 Pin Definitions and Functions (cont’d)

XC886/888CLM

General Device Information

Symbol Pin Number

(TQFP-48/64)

Type Reset

State

Function

P3 I/O Port 3

Port 3 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, UART1, Timer 21 and MultiCAN.

P3.0 35/43 Hi-Z CCPOS1_2

CC60_0

RXDO1_1

P3.1 36/44 Hi-Z CCPOS0_2

CC61_2

COUT60_0

TXD1_1

P3.2 37/49 Hi-Z CCPOS2_2

RXDC1_1 RXD1_1 CC61_0

CCU6 Hall Input 1

Input/Output of

Capture/Compare channel 0

UART1 Transmit Data Output

CCU6 Hall Input 0

Input/Output of

Capture/Compare channel 1

Output of Capture/Compare

channel 0

UART1 Transmit Data

Output/Clock Output

CCU6 Hall Input 2

MultiCAN Node 1 Receiver Input

UART1 Receive Data Input

Input/Output of

Capture/Compare channel 1

P3.3 38/50 Hi-Z COUT61_0

Output of Capture/Compare

channel 1 TXDC1_1

MultiCAN Node 1 Transmitter

Output

P3.4 39/51 Hi-Z CC62_0

Input/Output of

Capture/Compare channel 2 RXDC0_1 T2EX1_0

P3.5 40/52 Hi-Z COUT62_0

MultiCAN Node 0 Receiver Input

Timer 21 External Trigger Input

Output of Capture/Compare

channel 2 EXF21_0 TXDC0_1

Timer 21 External Flag Output

MultiCAN Node 0 Transmitter

Output

P3.6 33/41 PD CTRAP_0 CCU6 Trap Input

Data Sheet 14 V1.2, 2009-07

Table 3 Pin Definitions and Functions (cont’d)

XC886/888CLM

General Device Information

Symbol Pin Number

(TQFP-48/64)

Type Reset

State

Function

P3.7 34/42 Hi-Z EXINT4

COUT63_0

External Interrupt Input 4

Output of Capture/Compare

channel 3

Data Sheet 15 V1.2, 2009-07

Table 3 Pin Definitions and Functions (cont’d)

XC886/888CLM

General Device Information

Symbol Pin Number

(TQFP-48/64)

Type Reset

State

Function

P4 I/O Port 4

Port 4 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, Timer 0, Timer 1, Timer 21 and MultiCAN.

P4.0 45/59 Hi-Z RXDC0_3

CC60_1

P4.1 46/60 Hi-Z TXDC0_3

COUT60_1

P4.2 –/61 PU EXINT6_1

T21_0

P4.3 32/40 Hi-Z EXF21_1

COUT63_2

MultiCAN Node 0 Receiver Input

Output of Capture/Compare

channel 0

MultiCAN Node 0 Transmitter

Output

Output of Capture/Compare

channel 0

External Interrupt Input 6

Timer 21 Input

Timer 21 External Flag Output

Output of Capture/Compare

channel 3

P4.4 –/45 Hi-Z CCPOS0_3

T0_0 CC61_4

P4.5 –/46 Hi-Z CCPOS1_3

T1_0 COUT61_2

P4.6 –/47 Hi-Z CCPOS2_3

T2_0 CC62_2

P4.7 –/48 Hi-Z CTRAP_3

COUT62_2

CCU6 Hall Input 0

Timer 0 Input

Output of Capture/Compare

channel 1

CCU6 Hall Input 1

Timer 1 Input

Output of Capture/Compare

channel 1

CCU6 Hall Input 2

Timer 2 Input

Output of Capture/Compare

channel 2

CCU6 Trap Input

Output of Capture/Compare

channel 2

Data Sheet 16 V1.2, 2009-07

Table 3 Pin Definitions and Functions (cont’d)

XC886/888CLM

General Device Information

Symbol Pin Number

(TQFP-48/64)

Type Reset

State

Function

P5 I/O Port 5

Port 5 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for UART, UART1 and JTAG.

P5.0 –/8 PU EXINT1_1 External Interrupt Input 1

P5.1 –/9 PU EXINT2_1 External Interrupt Input 2

P5.2 –/12 PU RXD_2 UART Receive Data Input

P5.3 –/13 PU TXD_2 UART Transmit Data

Output/Clock Output

P5.4 –/14 PU RXDO_2 UART Transmit Data Output

P5.5 –/15 PU TDO_2

TXD1_2

JTAG Serial Data Output

UART1 Transmit Data Output/

Clock Output

P5.6 –/19 PU TCK_2

RXDO1_2

JTAG Clock Input

UART1 Transmit Data Output

P5.7 –/20 PU TDI_2

RXD1_2

JTAG Serial Data Input

UART1 Receive Data Input

Data Sheet 17 V1.2, 2009-07

Table 3 Pin Definitions and Functions (cont’d)

XC886/888CLM

General Device Information

Symbol Pin Number

(TQFP-48/64)

DDP

7, 17, 43/ 7, 25, 55

Type Reset

Function

State

– – I/O Port Supply (3.3 or 5.0 V)

Also used by EVR and analog modules. All pins must be connected.

SSP

18, 42/26, 54 – – I/O Port Ground

All pins must be connected.

DDC

SSC

AREF

AGND

6/6 – – Core Supply Monitor (2.5 V)

5/5 – – Core Supply Ground

24/32 – – ADC Reference Voltage

23/31 – – ADC Reference Ground

XTAL1 4/4 I Hi-Z External Oscillator Input

(backup for on-chip OSC, normally NC)

XTAL2 3/3 O Hi-Z External Oscillator Output

(backup for on-chip OSC, normally NC)

TMS 10/16 I PD Test Mode Select

RESET 41/53 I PU Reset Input

MBC

44/58 I PU Monitor & BootStrap Loader Control

NC –/56, 57 – – No Connection

1) An external pull-up device in the range of 4.7 kΩ to 100 kΩ. is required to enter user mode. Alternatively MBC can be tied to high if alternate functions (for debugging) of the pin are not utilized.

Data Sheet 18 V1.2, 2009-07

XC886/888CLM

Functional Description

3 Functional Description

Chapter 3 provides an overview of the XC886/888 functional description.

3.1 Processor Architecture

The XC886/888 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the XC886/888 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. Access to the Flash memory, however, requires an additional wait state (one machine cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions.

The XC886/888 CPU provides a range of debugging features, including basic stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory and Special Function Registers (SFRs).

Figure 6 shows the CPU functional blocks.

Core SFRs

External Data

Memory

16-bit R egisters & Memory Interface

Program Memory

CCLK

Memory Wait

Reset

Opcode & Immediate

Registers

Opcode D ecoder

State Machine &

Power Saving

Internal Data

Memory

External SFRs

ALU

Multiplier / Divider

Timer 0 / Timer 1

UART

Legacy External Interrupts (IEN0, IEN1)

External Interrupts

Non-Maskable Interrupt

Interrupt

Controller

Figure 6 CPU Block Diagram

Data Sheet 19 V1.2, 2009-07

XC886/888CLM

Functional Description

3.2 Memory Organization

The XC886/888 CPU operates in the following five address spaces:

• 12 Kbytes of Boot ROM program memory

• 256 bytes of internal RAM data memory

• 1.5 Kbytes of XRAM memory

(XRAM can be read/written as program memory or external data memory)

• A 128-byte Special Function Register area

• 24/32 Kbytes of Flash program memory (Flash devices); or

24/32 Kbytes of ROM program memory, with additional 4 Kbytes of Flash (ROM devices)

Figure 7 illustrates the memory address spaces of the 32-Kbyte Flash devices. For the

24-Kbyte Flash devices, the shaded banks are not available.

XRAM

1.5 Kby tes

Boot ROM

12 Kby tes

D-Fl ash B ank 1

4 Kby tes

D-Fl ash B ank 0

4 Kby tes

D-Fl ash B ank 0

4 Kby tes

D-Fl ash B ank 1

4 Kby tes

P-Flas h Bank s 4 and 5

2 x 4 K bytes

P-Flas h Bank s 2 and 3

2 x 4 K bytes

P-Flas h Bank s 0 and 1

2 x 4 K bytes

FFFF

F600

F000

C000

B000

A000

8000

7000

6000

5000

4000

2000

0000

XRAM

1.5 Kby tes

FFFF

F600

F000

0000

Indirect

Addr ess

Internal RAM

In 24-K byte Flash dev ic es, the upper 2Kby te of Bank s 4 and 5 ar e not avai labl e.

Direct

Addr ess

Special Function

Registers

Internal RA M

Program Spac e Ex ternal Data Spac e Internal Data Spac e

Figure 7 Memory Map of XC886/888 Flash Device

For both 24-Kbyte and 32-Kbyte ROM devices, the last four bytes of the ROM from 7FFC

Data Sheet 20 V1.2, 2009-07

to 7FFFH are reserved for the ROM signature and cannot be used to store user

XC886/888CLM

Functional Description

code or data. Therefore, even though the ROM device contains either a 24-Kbyte or 32Kbyte ROM, the maximum size of code that can be placed in the ROM is the given size less four bytes.

3.2.1 Memory Protection Strategy

The XC886/888 memory protection strategy includes:

• Read-out protection: The user is able to protect the contents in the Flash (for Flash

devices) and ROM (for ROM devices) memory from being read – Flash protection is enabled by programming a valid password (8-bit non-zero

value) via BSL mode 6.

– ROM protection is fixed with the ROM mask and is always enabled.

• Flash program and erase protection: This feature is available only for Flash devices.

3.2.1.1 Flash Memory Protection

As long as a valid password is available, all external access to the device, including the Flash, will be blocked.

For additional security, the Flash hardware protection can be enabled to implement a second layer of read-out protection, as well as to enable program and erase protection.

Flash hardware protection is available only for Flash devices and comes in two modes:

• Mode 0: Only the P-Flash is protected; the D-Flash is unprotected

• Mode 1: Both the P-Flash and D-Flash are protected

The selection of each protection mode and the restrictions imposed are summarized in

Table 4.

Table 4 Flash Protection Modes

Flash Protection Without hardware

protection

Hardware Protection Mode

Activation Program a valid password via BSL mode 6

Selection Bit 4 of password = 0 Bit 4 of password = 1

-01

With hardware protection

Bit 4 of password = 1

MSB of password = 0

MSB of password = 1

P-Flash contents can be read by

External access to P-Flash

Data Sheet 21 V1.2, 2009-07

Read instructions in any program memory

Not possible Not possible Not possible

Read instructions in the P-Flash

Read instructions in the P-Flash or DFlash

Table 4 Flash Protection Modes (cont’d)

XC886/888CLM

Functional Description

Flash Protection Without hardware

With hardware protection

protection

P-Flash program

Possible Not possible Not possible

and erase

D-Flash contents can be

Read instructions in any program memory

read by

External access

Not possible Not possible Not possible

to D-Flash

D-Flash

Possible Possible Not possible

program

D-Flash erase Possible Possible, on

condition that bit DFLASHEN in register MISC_CON is set to 1 prior to each erase operation

Read instructions in the P-Flash or DFlash

Not possible

BSL mode 6, which is used for enabling Flash protection, can also be used for disabling Flash protection. Here, the programmed password must be provided by the user. A password match triggers an automatic erase of the protected P-Flash and D-Flash contents, including the programmed password. The Flash protection is then disabled upon the next reset.

For the ROM device, the ROM is protected at all times and BSL mode 6 is used only to block external access to the device. However, unlike the Flash device, it is not possible to disable the memory protection of the ROM device. Here, entering BSL mode 6 will result in a protection error.

Note: If ROM read-out protection is enabled, only read instructions in the ROM memory

can target the ROM contents.

Although no protection scheme can be considered infallible, the XC886/888 memory protection strategy provides a very high level of protection for a general purpose microcontroller.

Data Sheet 22 V1.2, 2009-07

XC886/888CLM

Functional Description

3.2.2 Special Function Register

The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80

to FFH. All registers, except the program counter, reside in the SFR area. The

SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR range is less than the total number of registers required, address extension mechanisms are required to increase the number of addressable SFRs. The address extension mechanisms include:

• Mapping

•Paging

3.2.2.1 Address Extension by Mapping

Address extension is performed at the system level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80 addressable SFRs to 256. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit RMAP in the system control register SYSCON0 at address 8F

. To access SFRs in the mapped area, bit RMAP in SFR

SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 8.

to FFH, bringing the number of

As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, before standard/mapped registers are accessed, bit RMAP must be cleared/set, respectively, by software.

Data Sheet 23 V1.2, 2009-07

+ 114 hidden pages