The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
8-Bit
XC886/888CLM
8-Bit Single Chip Microcontroller
Data Sheet
V1.2 2009-07
Microcontrollers
XC886/888CLM
XC886/888 Data Sheet
Revision History: V1.2 2009-07
Previous Versions: V1.0, V1.1
PageSubjects (major changes since last revision)
Changes from V1.1 2009-01 to V1.2 2009-07
89Note on LIN baud rate detection is added.
92RXD slave line in SSC block diagram is updated.
108Electrical parameters are now valid for all variants, previous note on
exclusion of ROM variants is removed.
116Symbol for ADC error parameters are updated.
120Power supply current parameters for ROM variants are updated.
128Test condition for the on-chip oscillator short term deviation is updated.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
• High-performance XC800 Core
– compatible with standard 8051 processor
– two clocks per machine cycle architecture (for memory access without wait state)
– two data pointers
• On-chip memory
– 12 Kbytes of Boot ROM
– 256 bytes of RAM
– 1.5 Kbytes of XRAM
– 24/32 Kbytes of Flash; or
24/32 Kbytes of ROM, with additional 4 Kbytes of Flash
(includes memory protection strategy)
•I/O port supply at 3.3 V or 5.0 V and core logic supply at 2.5 V (generated by
embedded voltage regulator)
(more features on next page)
Flash or ROM
24K/32K x 8
Boot ROM
12K x 8
XRAM
1.5K x 8
RAM
256 x 8
1) All ROM devices come with an additional 4K x 8 Flash
1)
Timer 0
16-bit
On-Chip Debug Support
XC800 Core
Timer 1
16-bit
Timer 2
16-bit
Timer 21
16-bit
UART
Capture/Compare Unit
Compare Unit
Watchdog
Timer
UART1
SSC
16-bit
16-bit
ADC
10-bit
8-channel
8-bit Digital I/O
Port 0
Port 1
Port 2
Port 3
Port 4Port 5MDUCORDICMultiCAN
8-bit Digital I/O
8-bit Digital I/O
8-bit Digital/
Analog Input
8-bit Digital I/O
8-bit Digital I/O
.
Figure 1XC886/888 Functional Units
Data Sheet1V1.2, 2009-07
XC886/888CLM
Summary of Features
Features: (continued)
•Power-on reset generation
•Brownout detection for core logic supply
•On-chip OSC and PLL for clock generation
– PLL loss-of-lock detection
•Power saving modes
– slow-down mode
– idle mode
– power-down mode with wake-up capability via RXD or EXINT0
– clock gating control to each peripheral
•Programmable 16-bit Watchdog Timer (WDT)
•Six ports
– Up to 48 pins as digital I/O
– 8 pins as digital/analog input
•8-channel, 10-bit ADC
•Four 16-bit timers
– Timer 0 and Timer 1 (T0 and T1)
– Timer 2 and Timer 21 (T2 and T21)
•Multiplication/Division Unit for arithmetic operations (MDU)
•Software libraries to support floating point and MDU calculations
•CORDIC Coprocessor for computation of trigonometric, hyperbolic and linear
functions
•MultiCAN with 2 nodes, 32 message objects
•Capture/compare unit for PWM signal generation (CCU6)
•Two full-duplex serial interfaces (UART and UART1)
•Synchronous serial channel (SSC)
•On-chip debug support
– 1 Kbyte of monitor ROM (part of the 12-Kbyte Boot ROM)
– 64 bytes of monitor RAM
•Packages:
– PG-TQFP-48
– PG-TQFP-64
T
•Temperature range
– SAF (-40 to 85 °C)
– SAK (-40 to 125 °C)
:
A
Data Sheet2V1.2, 2009-07
XC886/888CLM
Summary of Features
XC886/888 Variant Devices
The XC886/888 product family features devices with different configurations, program
memory sizes, package options, power supply voltage, temperature and quality profiles
(Automotive or Industrial), to offer cost-effective solutions for different application
requirements.
The list of XC886/888 device configurations are summarized in Table 1. For each
configuration, 2 types of packages are available:
•PG-TQFP-48, which is denoted by XC886 and;
•PG-TQFP-64, which is denoted by XC888.
Table 1Device Configuration
Device NameCAN
Module
LIN BSL
Support
MDU
Module
XC886/888NoNoNo
XC886/888CYesNoNo
XC886/888CMYesNoYes
XC886/888LMNoYesYes
XC886/888CLMYesYesYes
Note: For variants with LIN BSL support, only LIN BSL is available regardless of the
availability of the CAN module.
From these 10 different combinations of configuration and package type, each are
further made available in many sales types, which are grouped according to device type,
program memory sizes, power supply voltage, temperature and quality profile
(Automotive or Industrial), as shown in Table 2.
Table 2Device Profile
Sales TypeDevice
Type
Program
Memory
(Kbytes)
Power
Supply
(V)
Temperature
(°C)
Quality
Profile
SAK-XC886*/888*-8FFA 5VFlash325.0-40 to 125Automotive
SAK-XC886*/888*-6FFA 5VFlash245.0-40 to 125Automotive
SAF-XC886*/888*-8FFA 5VFlash325.0-40 to 85Automotive
SAF-XC886*/888*-6FFA 5VFlash245.0-40 to 85Automotive
SAF-XC886*/888*-8FFI 5VFlash325.0-40 to 85Industrial
SAF-XC886*/888*-6FFI 5VFlash245.0-40 to 85Industrial
Data Sheet3V1.2, 2009-07
Table 2Device Profile (cont’d)
XC886/888CLM
Summary of Features
Sales TypeDevice
Type
Program
Memory
(Kbytes)
Power
Supply
(V)
Temperature
(°C)
Quality
Profile
SAK-XC886*/888*-8FFA 3V3 Flash323.3-40 to 125Automotive
SAK-XC886*/888*-6FFA 3V3 Flash243.3-40 to 125Automotive
SAF-XC886*/888*-8FFA 3V3 Flash323.3-40 to 85Automotive
SAF-XC886*/888*-6FFA 3V3 Flash243.3-40 to 85Automotive
SAF-XC886*/888*-8FFI 3V3Flash323.3-40 to 85Industrial
SAF-XC886*/888*-6FFI 3V3Flash243.3-40 to 85Industrial
Note: The asterisk (*) above denotes the device configuration letters from Table 1.
Corresponding ROM derivatives will be available on request.
Note: For variants with LIN BSL support, only LIN BSL is available regardless of the
availability of the CAN module.
As this document refers to all the derivatives, some description may not apply to a
specific product. For simplicity, all versions are referred to by the term XC886/888
throughout this document.
Ordering Information
The ordering code for Infineon Technologies microcontrollers provides an exact
reference to the required product. This ordering code identifies:
•The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
•The package and the type of delivery
For the available ordering codes for the XC886/888, please refer to your responsible
sales representative or your local distributor.
Note: The ordering codes for the Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Data Sheet4V1.2, 2009-07
XC886/888CLM
General Device Information
2General Device Information
Chapter 2 contains the block diagram, pin configurations, definitions and functions of the
XC886/888.
2.1Block Diagram
The block diagram of the XC886/888 is shown in Figure 2.
TMS
MBC
RESET
V
DDP
V
SSP
V
DDC
V
SSC
XTAL1
XTAL2
XC886/888
12-Kbyte
Boot ROM
256-byte RAM
64-byte monitor
1.5-Kbyte XRAM
24/32-Kbyte
Flash or ROM
Clock Generator
9.6 MHz
On-chip OSC
1)
+
RAM
PLL
Internal Bus
XC800 Core
T0 & T1UART
UART1CORDIC
SSCMDU
2)
WDT
OCDS
Timer 2
Timer 21
CCU6
MultiCAN
Port 0Port 1Port 2Port 3
ADC
Port 4Port 5
P0.0 - P0.7
P1.0 - P1.7
P2.0 - P2.7
V
AREF
V
AGND
P3.0 - P3.7
P4.0 - P4.7
1) Includes 1-Kbyte monitor ROM
P5.0 - P5.7
2) The 24/32-Kbyte ROM has an additional 4-Kbyte Flash
Figure 2XC886/888 Block Diagram
Data Sheet5V1.2, 2009-07
General Device Information
t
t
t
t
t
t
2.2Logic Symbol
The logic symbols of the XC886/888 are shown in Figure 3.
XC886/888CLM
V
AREF
V
AGND
RESET
MBC
TMS
XTAL1
XTAL2
V
V
DDP
XC886
DDC
V
SSP
V
DDP
V
SSP
Port 0 8-Bi
V
Port 0 7-Bit
Port 1 8-Bit
Port 2 8-Bit
Port 3 8-Bit
Port 4 3-Bit
V
SSC
AREF
V
AGND
RESET
MBC
TMS
XTAL1
XTAL2
V
DDC
XC888
Port 1 8-Bi
Port 2 8-Bi
Port 3 8-Bi
Port 4 8-Bi
Port 5 8-Bi
V
SSC
Figure 3XC886/888 Logic Symbol
Data Sheet6V1.2, 2009-07
XC886/888CLM
General Device Information
2.3Pin Configuration
The pin configuration of the XC886, which is based on the PG-TQFP-48 package, is
shown in
package, is shown in Figure 5.
Figure 4, while that of the XC888, which is based on the PG-TQFP-64
The functions and default states of the XC886/888 external pins are provided in Table 3.
Table 3Pin Definitions and Functions
Symbol Pin Number
(TQFP-48/64)
Type Reset
State
Function
P0I/OPort 0
Port 0 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for the JTAG, CCU6, UART, UART1, Timer
Timer
P0.011/17Hi-ZTCK_0
T12HR_1
CC61_1
CLKOUT_0
RXDO_1
P0.113/21Hi-ZTDI_0
T13HR_1
RXD_1
RXDC1_0
COUT61_1
EXF2_1
2,
21, MultiCAN and SSC.
JTAG Clock Input
CCU6 Timer 12 Hardware Run
Input
Input/Output of
Capture/Compare channel 1
Clock Output
UART Transmit Data Output
JTAG Serial Data Input
CCU6 Timer 13 Hardware Run
Input
UART Receive Data Input
MultiCAN Node 1 Receiver Input
Output of Capture/Compare
channel 1
Timer 2 External Flag Output
P0.212/18PUCTRAP_2
TDO_0
TXD_1
CCU6 Trap Input
JTAG Serial Data Output
UART Transmit Data
Output/Clock Output
TXDC1_0
MultiCAN Node 1 Transmitter
Output
P0.348/63Hi-ZSCK_1
COUT63_1
SSC Clock Input/Output
Output of Capture/Compare
channel 3
RXDO1_0
Data Sheet9V1.2, 2009-07
UART1 Transmit Data Output
Table 3Pin Definitions and Functions (cont’d)
XC886/888CLM
General Device Information
Symbol Pin Number
(TQFP-48/64)
P0.41/64Hi-ZMTSR_1
Type Reset
State
Function
SSC Master Transmit Output/
Slave Receive Input
CC62_1
Input/Output of
Capture/Compare channel 2
TXD1_0
UART1 Transmit Data
Output/Clock Output
P0.52/1Hi-ZMRST_1
SSC Master Receive Input/Slave
Transmit Output
EXINT0_0
T2EX1_1
RXD1_0
COUT62_1
External Interrupt Input 0
Timer 21 External Trigger Input
UART1 Receive Data Input
Output of Capture/Compare
channel 2
P0.6–/2PUGPIO
P0.747/62PUCLKOUT_1Clock Output
Data Sheet10V1.2, 2009-07
Table 3Pin Definitions and Functions (cont’d)
XC886/888CLM
General Device Information
Symbol Pin Number
(TQFP-48/64)
Type Reset
State
Function
P1I/OPort 1
Port 1 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for the JTAG, CCU6, UART, Timer 0, Timer 1,
Timer 2, Timer 21, MultiCAN and SSC.
P1.026/34PURXD_0
T2EX
RXDC0_0
P1.127/35PUEXINT3
T0_1
TDO_1
TXD_0
UART Receive Data Input
Timer 2 External Trigger Input
MultiCAN Node 0 Receiver Input
External Interrupt Input 3
Timer 0 Input
JTAG Serial Data Output
UART Transmit Data
Output/Clock Output
TXDC0_0
MultiCAN Node 0 Transmitter
Output
P1.228/36PUSCK_0SSC Clock Input/Output
P1.329/37PUMTSR_0
TXDC1_3
P1.430/38PUMRST_0
EXINT0_1
RXDC1_3
P1.531/39PUCCPOS0_1
EXINT5
T1_1
EXF2_0
RXDO_0
SSC Master Transmit
Output/Slave Receive Input
MultiCAN Node 1 Transmitter
Output
SSC Master Receive Input/
Slave Transmit Output
External Interrupt Input 0
MultiCAN Node 1 Receiver Input
CCU6 Hall Input 0
External Interrupt Input 5
Timer 1 Input
Timer 2 External Flag Output
UART Transmit Data Output
Data Sheet11V1.2, 2009-07
Table 3Pin Definitions and Functions (cont’d)
XC886/888CLM
General Device Information
Symbol Pin Number
(TQFP-48/64)
Type Reset
State
Function
P1.68/10PUCCPOS1_1
T12HR_0
EXINT6_0
RXDC0_2
T21_1
P1.79/11PUCCPOS2_1
T13HR_0
T2_1
TXDC0_2
P1.5 and P1.6 can be used as a software chip
select output for the SSC.
CCU6 Hall Input 1
CCU6 Timer 12 Hardware Run
Input
External Interrupt Input 6
MultiCAN Node 0 Receiver Input
Timer 21 Input
CCU6 Hall Input 2
CCU6 Timer 13 Hardware Run
Input
Timer 2 Input
MultiCAN Node 0 Transmitter
Output
Data Sheet12V1.2, 2009-07
Table 3Pin Definitions and Functions (cont’d)
XC886/888CLM
General Device Information
Symbol Pin Number
(TQFP-48/64)
Type Reset
State
Function
P2IPort 2
Port 2 is an 8-bit general purpose input-only
port. It can be used as alternate functions for
the digital inputs of the JTAG and CCU6. It is
also used as the analog inputs for the ADC.
P2.014/22Hi-ZCCPOS0_0
EXINT1_0
T12HR_2
TCK_1
CC61_3
AN0
P2.115/23Hi-ZCCPOS1_0
EXINT2_0
T13HR_2
TDI_1
CC62_3
AN1
CCU6 Hall Input 0
External Interrupt Input 1
CCU6 Timer 12 Hardware Run
Input
JTAG Clock Input
Input of Capture/Compare
channel 1
Analog Input 0
CCU6 Hall Input 1
External Interrupt Input 2
CCU6 Timer 13 Hardware Run
Input
JTAG Serial Data Input
Input of Capture/Compare
channel 2
Analog Input 1
P2.216/24Hi-ZCCPOS2_0
CTRAP_1
CC60_3
CCU6 Hall Input 2
CCU6 Trap Input
Input of Capture/Compare
channel 0
AN2
Analog Input 2
P2.319/27Hi-ZAN3Analog Input 3
P2.420/28Hi-ZAN4Analog Input 4
P2.521/29Hi-ZAN5Analog Input 5
P2.622/30Hi-ZAN6Analog Input 6
P2.725/33Hi-ZAN7Analog Input 7
Data Sheet13V1.2, 2009-07
Table 3Pin Definitions and Functions (cont’d)
XC886/888CLM
General Device Information
Symbol Pin Number
(TQFP-48/64)
Type Reset
State
Function
P3I/OPort 3
Port 3 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for CCU6, UART1, Timer 21 and MultiCAN.
P3.035/43Hi-ZCCPOS1_2
CC60_0
RXDO1_1
P3.136/44Hi-ZCCPOS0_2
CC61_2
COUT60_0
TXD1_1
P3.237/49Hi-ZCCPOS2_2
RXDC1_1
RXD1_1
CC61_0
CCU6 Hall Input 1
Input/Output of
Capture/Compare channel 0
UART1 Transmit Data Output
CCU6 Hall Input 0
Input/Output of
Capture/Compare channel 1
Output of Capture/Compare
channel 0
UART1 Transmit Data
Output/Clock Output
CCU6 Hall Input 2
MultiCAN Node 1 Receiver Input
UART1 Receive Data Input
Input/Output of
Capture/Compare channel 1
P3.338/50Hi-ZCOUT61_0
Output of Capture/Compare
channel 1
TXDC1_1
MultiCAN Node 1 Transmitter
Output
P3.439/51Hi-ZCC62_0
Input/Output of
Capture/Compare channel 2
RXDC0_1
T2EX1_0
P3.540/52Hi-ZCOUT62_0
MultiCAN Node 0 Receiver Input
Timer 21 External Trigger Input
Output of Capture/Compare
channel 2
EXF21_0
TXDC0_1
Timer 21 External Flag Output
MultiCAN Node 0 Transmitter
Output
P3.633/41PDCTRAP_0CCU6 Trap Input
Data Sheet14V1.2, 2009-07
Table 3Pin Definitions and Functions (cont’d)
XC886/888CLM
General Device Information
Symbol Pin Number
(TQFP-48/64)
Type Reset
State
Function
P3.734/42Hi-ZEXINT4
COUT63_0
External Interrupt Input 4
Output of Capture/Compare
channel 3
Data Sheet15V1.2, 2009-07
Table 3Pin Definitions and Functions (cont’d)
XC886/888CLM
General Device Information
Symbol Pin Number
(TQFP-48/64)
Type Reset
State
Function
P4I/OPort 4
Port 4 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for CCU6, Timer 0, Timer 1, Timer 21 and
MultiCAN.
P4.045/59Hi-ZRXDC0_3
CC60_1
P4.146/60Hi-ZTXDC0_3
COUT60_1
P4.2–/61PUEXINT6_1
T21_0
P4.332/40Hi-ZEXF21_1
COUT63_2
MultiCAN Node 0 Receiver Input
Output of Capture/Compare
channel 0
MultiCAN Node 0 Transmitter
Output
Output of Capture/Compare
channel 0
External Interrupt Input 6
Timer 21 Input
Timer 21 External Flag Output
Output of Capture/Compare
channel 3
P4.4–/45Hi-ZCCPOS0_3
T0_0
CC61_4
P4.5–/46Hi-ZCCPOS1_3
T1_0
COUT61_2
P4.6–/47Hi-ZCCPOS2_3
T2_0
CC62_2
P4.7–/48Hi-ZCTRAP_3
COUT62_2
CCU6 Hall Input 0
Timer 0 Input
Output of Capture/Compare
channel 1
CCU6 Hall Input 1
Timer 1 Input
Output of Capture/Compare
channel 1
CCU6 Hall Input 2
Timer 2 Input
Output of Capture/Compare
channel 2
CCU6 Trap Input
Output of Capture/Compare
channel 2
Data Sheet16V1.2, 2009-07
Table 3Pin Definitions and Functions (cont’d)
XC886/888CLM
General Device Information
Symbol Pin Number
(TQFP-48/64)
Type Reset
State
Function
P5I/OPort 5
Port 5 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for UART, UART1 and JTAG.
P5.0–/8PUEXINT1_1External Interrupt Input 1
P5.1–/9PUEXINT2_1External Interrupt Input 2
P5.2–/12PURXD_2UART Receive Data Input
P5.3–/13PUTXD_2UART Transmit Data
Output/Clock Output
P5.4–/14PURXDO_2UART Transmit Data Output
P5.5–/15PUTDO_2
TXD1_2
JTAG Serial Data Output
UART1 Transmit Data Output/
Clock Output
P5.6–/19PUTCK_2
RXDO1_2
JTAG Clock Input
UART1 Transmit Data Output
P5.7–/20PUTDI_2
RXD1_2
JTAG Serial Data Input
UART1 Receive Data Input
Data Sheet17V1.2, 2009-07
Table 3Pin Definitions and Functions (cont’d)
XC886/888CLM
General Device Information
Symbol Pin Number
(TQFP-48/64)
V
DDP
7, 17, 43/
7, 25, 55
Type Reset
Function
State
––I/O Port Supply (3.3 or 5.0 V)
Also used by EVR and analog modules. All
pins must be connected.
V
SSP
18, 42/26, 54––I/O Port Ground
All pins must be connected.
V
V
V
V
DDC
SSC
AREF
AGND
6/6––Core Supply Monitor (2.5 V)
5/5––Core Supply Ground
24/32––ADC Reference Voltage
23/31––ADC Reference Ground
XTAL14/4IHi-ZExternal Oscillator Input
(backup for on-chip OSC, normally NC)
XTAL23/3OHi-ZExternal Oscillator Output
(backup for on-chip OSC, normally NC)
TMS10/16IPDTest Mode Select
RESET41/53IPUReset Input
1)
MBC
44/58IPUMonitor & BootStrap Loader Control
NC–/56, 57––No Connection
1) An external pull-up device in the range of 4.7 kΩ to 100 kΩ. is required to enter user mode. Alternatively MBC
can be tied to high if alternate functions (for debugging) of the pin are not utilized.
Data Sheet18V1.2, 2009-07
XC886/888CLM
Functional Description
3Functional Description
Chapter 3 provides an overview of the XC886/888 functional description.
3.1Processor Architecture
The XC886/888 is based on a high-performance 8-bit Central Processing Unit (CPU)
that is compatible with the standard 8051 processor. While the standard 8051 processor
is designed around a 12-clock machine cycle, the XC886/888 CPU uses a 2-clock
machine cycle. This allows fast access to ROM or RAM memories without wait state.
Access to the Flash memory, however, requires an additional wait state (one machine
cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte
instructions.
The XC886/888 CPU provides a range of debugging features, including basic stop/start,
single-step execution, breakpoint support and read/write access to the data memory,
program memory and Special Function Registers (SFRs).
Figure 6 shows the CPU functional blocks.
Core SFRs
External Data
Memory
16-bit R egisters &
Memory Interface
Program Memory
f
CCLK
Memory Wait
Reset
Opcode &
Immediate
Registers
Opcode D ecoder
State Machine &
Power Saving
Internal Data
Memory
Register Interface
External SFRs
ALU
Multiplier / Divider
Timer 0 / Timer 1
UART
Legacy External Interrupts (IEN0, IEN1)
External Interrupts
Non-Maskable Interrupt
Interrupt
Controller
Figure 6CPU Block Diagram
Data Sheet19V1.2, 2009-07
XC886/888CLM
Functional Description
3.2Memory Organization
The XC886/888 CPU operates in the following five address spaces:
•12 Kbytes of Boot ROM program memory
•256 bytes of internal RAM data memory
•1.5 Kbytes of XRAM memory
(XRAM can be read/written as program memory or external data memory)
•A 128-byte Special Function Register area
•24/32 Kbytes of Flash program memory (Flash devices); or
24/32 Kbytes of ROM program memory, with additional 4 Kbytes of Flash
(ROM devices)
Figure 7 illustrates the memory address spaces of the 32-Kbyte Flash devices. For the
24-Kbyte Flash devices, the shaded banks are not available.
XRAM
1.5 Kby tes
Boot ROM
12 Kby tes
D-Fl ash B ank 1
4 Kby tes
D-Fl ash B ank 0
4 Kby tes
D-Fl ash B ank 0
4 Kby tes
D-Fl ash B ank 1
4 Kby tes
P-Flas h Bank s 4 and 5
2 x 4 K bytes
P-Flas h Bank s 2 and 3
2 x 4 K bytes
P-Flas h Bank s 0 and 1
2 x 4 K bytes
1)
FFFF
F600
F000
C000
B000
A000
8000
7000
6000
5000
4000
2000
0000
H
H
H
H
H
H
H
H
H
H
H
H
H
XRAM
1.5 Kby tes
FFFF
F600
F000
0000
H
H
H
H
1)
Indirect
Addr ess
Internal RAM
7F
H
00
H
In 24-K byte Flash dev ic es, the upper 2Kby te of Bank s 4 and 5 ar e not avai labl e.
Direct
Addr ess
Special Function
Registers
Internal RA M
FF
H
80
H
Program Spac eEx ternal Data Spac eInternal Data Spac e
Figure 7Memory Map of XC886/888 Flash Device
For both 24-Kbyte and 32-Kbyte ROM devices, the last four bytes of the ROM from
7FFC
Data Sheet20V1.2, 2009-07
to 7FFFH are reserved for the ROM signature and cannot be used to store user
H
XC886/888CLM
Functional Description
code or data. Therefore, even though the ROM device contains either a 24-Kbyte or 32Kbyte ROM, the maximum size of code that can be placed in the ROM is the given size
less four bytes.
3.2.1Memory Protection Strategy
The XC886/888 memory protection strategy includes:
•Read-out protection: The user is able to protect the contents in the Flash (for Flash
devices) and ROM (for ROM devices) memory from being read
– Flash protection is enabled by programming a valid password (8-bit non-zero
value) via BSL mode 6.
– ROM protection is fixed with the ROM mask and is always enabled.
•Flash program and erase protection: This feature is available only for Flash devices.
3.2.1.1Flash Memory Protection
As long as a valid password is available, all external access to the device, including the
Flash, will be blocked.
For additional security, the Flash hardware protection can be enabled to implement a
second layer of read-out protection, as well as to enable program and erase protection.
Flash hardware protection is available only for Flash devices and comes in two modes:
•Mode 0: Only the P-Flash is protected; the D-Flash is unprotected
•Mode 1: Both the P-Flash and D-Flash are protected
The selection of each protection mode and the restrictions imposed are summarized in
Table 4.
Table 4Flash Protection Modes
Flash Protection Without hardware
protection
Hardware
Protection Mode
ActivationProgram a valid password via BSL mode 6
SelectionBit 4 of password = 0 Bit 4 of password = 1
-01
With hardware protection
Bit 4 of password = 1
MSB of password = 0
MSB of password = 1
P-Flash
contents can be
read by
External access
to P-Flash
Data Sheet21V1.2, 2009-07
Read instructions in
any program memory
Not possibleNot possibleNot possible
Read instructions in
the P-Flash
Read instructions in
the P-Flash or DFlash
Table 4Flash Protection Modes (cont’d)
XC886/888CLM
Functional Description
Flash Protection Without hardware
With hardware protection
protection
P-Flash program
PossibleNot possibleNot possible
and erase
D-Flash
contents can be
Read instructions in
any program memory
Read instructions in
any program memory
read by
External access
Not possibleNot possibleNot possible
to D-Flash
D-Flash
PossiblePossibleNot possible
program
D-Flash erasePossiblePossible, on
condition that bit
DFLASHEN in
register MISC_CON
is set to 1 prior to
each erase operation
Read instructions in
the P-Flash or DFlash
Not possible
BSL mode 6, which is used for enabling Flash protection, can also be used for disabling
Flash protection. Here, the programmed password must be provided by the user. A
password match triggers an automatic erase of the protected P-Flash and D-Flash
contents, including the programmed password. The Flash protection is then disabled
upon the next reset.
For the ROM device, the ROM is protected at all times and BSL mode 6 is used only to
block external access to the device. However, unlike the Flash device, it is not possible
to disable the memory protection of the ROM device. Here, entering BSL mode 6 will
result in a protection error.
Note: If ROM read-out protection is enabled, only read instructions in the ROM memory
can target the ROM contents.
Although no protection scheme can be considered infallible, the XC886/888 memory
protection strategy provides a very high level of protection for a general purpose
microcontroller.
Data Sheet22V1.2, 2009-07
XC886/888CLM
Functional Description
3.2.2Special Function Register
The Special Function Registers (SFRs) occupy direct internal data memory space in the
range 80
to FFH. All registers, except the program counter, reside in the SFR area. The
H
SFRs include pointers and registers that provide an interface between the CPU and the
on-chip peripherals. As the 128-SFR range is less than the total number of registers
required, address extension mechanisms are required to increase the number of
addressable SFRs. The address extension mechanisms include:
•Mapping
•Paging
3.2.2.1Address Extension by Mapping
Address extension is performed at the system level by mapping. The SFR area is
extended into two portions: the standard (non-mapped) SFR area and the mapped SFR
area. Each portion supports the same address range 80
addressable SFRs to 256. The extended address range is not directly controlled by the
CPU instruction itself, but is derived from bit RMAP in the system control register
SYSCON0 at address 8F
. To access SFRs in the mapped area, bit RMAP in SFR
H
SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed
by clearing bit RMAP. The SFR area can be selected as shown in Figure 8.
to FFH, bringing the number of
H
As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not
cleared automatically by hardware. Thus, before standard/mapped registers are
accessed, bit RMAP must be cleared/set, respectively, by software.
Data Sheet23V1.2, 2009-07
Functional Description
Standard Area (RMAP = 0)
Module 1 SFRs
XC886/888CLM
FF
H
SFR Data
(to/from CPU)
SYSCON0.RMAP
rw
Module 2 SFRs
…...
Module n SFRs
Mapped Area (RMAP = 1)
Module (n+1) SFRs
Module (n+2) SFRs
…...
80
FF
H
H
Module m SFRs
80
H
Direct
Internal Data
Memory Address
Figure 8Address Extension by Mapping
Data Sheet24V1.2, 2009-07
XC886/888CLM
Functional Description
SYSCON0
System Control Register 0Reset Value: 04
76543210
0IMODE010RMAP
rrwrrrrw
FieldBitsTypeDescription
RMAP0rwInterrupt Node XINTR0 Enable
0The access to the standard SFR area is
enabled
1The access to the mapped SFR area is
enabled
H
12rReserved
Returns 1 if read; should be written with 1.
0[7:5],
3,1
rReserved
Returns 0 if read; should be written with 0.
Note: The RMAP bit should be cleared/set by ANL or ORL instructions.
3.2.2.2Address Extension by Paging
Address extension is further performed at the module level by paging. With the address
extension by mapping, the XC886/888 has a 256-SFR address range. However, this is
still less than the total number of SFRs needed by the on-chip peripherals. To meet this
requirement, some peripherals have a built-in local address extension mechanism for
increasing the number of addressable SFRs. The extended address range is not directly
controlled by the CPU instruction itself, but is derived from bit field PAGE in the module
page register MOD_PAGE. Hence, the bit field PAGE must be programmed before
accessing the SFR of the target module. Each module may contain a different number
of pages and a different number of SFRs per page, depending on the specific
requirement. Besides setting the correct RMAP bit value to select the SFR area, the user
must also ensure that a valid PAGE is selected to target the desired SFR. A page inside
the extended address range can be selected as shown in Figure 9.
Data Sheet25V1.2, 2009-07
SFR Address
(from CPU)
XC886/888CLM
Functional Description
PAGE 0
SFR Data
(to/from CPU)
MOD_PAGE.PAGE
rw
SFR0
SFR1
…...
SFRx
PAGE 1
SFR0
SFR1
…...
SFRy
…...
PAGE q
SFR0
SFR1
…...
SFRz
Module
Figure 9Address Extension by Paging
In order to access a register located in a page different from the actual one, the current
page must be exited. This is done by reprogramming the bit field PAGE in the page
register. Only then can the desired access be performed.
If an interrupt routine is initiated between the page register access and the module
register access, and the interrupt needs to access a register located in another page, the
current page setting can be saved, the new one programmed and the old page setting
restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore
action of the current page setting. By indicating which storage bit field should be used in
parallel with the new page value, a single write operation can:
•Save the contents of PAGE in STx before overwriting with the new value
(this is done in the beginning of the interrupt routine to save the current page setting
and program the new page number); or
Data Sheet26V1.2, 2009-07
XC886/888CLM
Functional Description
•Overwrite the contents of PAGE with the contents of STx, ignoring the value written
to the bit positions of PAGE
(this is done at the end of the interrupt routine to restore the previous page setting
before the interrupt occurred)
ST3
ST2
ST1
ST0
STNR
value update
PAGE
from CPU
Figure 10Storage Elements for Paging
With this mechanism, a certain number of interrupt routines (or other routines) can
perform page changes without reading and storing the previously used page information.
The use of only write operations makes the system simpler and faster. Consequently,
this mechanism significantly improves the performance of short interrupt routines.
The XC886/888 supports local address extension for:
•Parallel Ports
•Analog-to-Digital Converter (ADC)
•Capture/Compare Unit 6 (CCU6)
•System Control Registers
Data Sheet27V1.2, 2009-07
XC886/888CLM
Functional Description
The page register has the following definition:
MOD_PAGE
Page Register for module MODReset Value: 00
76543210
OPSTNR0PAGE
wwrrw
FieldBitsTypeDescription
PAGE[2:0]rwPage Bits
When written, the value indicates the new page.
When read, the value indicates the currently active
page.
H
STNR[5:4]wStorage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10
,
B
the contents of PAGE are saved in STx before being
overwritten with the new value.
If OP = 11
,
B
the contents of PAGE are overwritten by the
contents of STx. The value written to the bit positions
of PAGE is ignored.
00ST0 is selected.
01ST1 is selected.
10ST2 is selected.
11ST3 is selected.
Data Sheet28V1.2, 2009-07
FieldBitsTypeDescription
OP[7:6]wOperation
0XManual page mode. The value of STNR is
ignored and PAGE is directly written.
10New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field STx indicated by STNR.
11Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field STx indicated
by STNR.
XC886/888CLM
Functional Description
03rReserved
Returns 0 if read; should be written with 0.
3.2.3Bit Protection Scheme
The bit protection scheme prevents direct software writing of selected bits (i.e., protected
bits) using the PASSWD register. When the bit field MODE is 11
bit field PASS opens access to writing of all protected bits, and writing 10101
field PASS closes access to writing of all protected bits. In both cases, the value of the
bit field MODE is not changed even if PASSWD register is written with 98
only be changed when bit field PASS is written with 11000
, for example, writing D0H to
B
PASSWD register disables the bit protection scheme.
Note that access is opened for maximum 32 CCLKs if the “close access” password is not
written. If “open access” password is written again before the end of 32 CCLK cycles,
there will be a recount of 32 CCLK cycles. The protected bits include the N- and KDivider bits, NDIV and KDIV; the Watchdog Timer enable bit, WDTEN; and the powerdown and slow-down enable bits, PD and SD.
, writing 10011B to the
B
to the bit
B
or A8H. It can
H
Data Sheet29V1.2, 2009-07
XC886/888CLM
Functional Description
3.2.3.1Password Register
PASSWD
Password Register Reset Value: 07
76543210
H
PASS
whrhrw
PROTECT
_S
FieldBitsTypeDescription
MODE[1:0]rwBit Protection Scheme Control Bits
00Scheme disabled - direct access to the
protected bits is allowed.
11Scheme enabled - the bit field PASS has to be
written with the passwords to open and close
the access to protected bits. (default)
Others:Scheme Enabled.
These two bits cannot be written directly. To change
the value between 11
must be written with 11000
and 00B, the bit field PASS
B
; only then, will the
B
MODE[1:0] be registered.
PROTECT_S2rhBit Protection Signal Status Bit
This bit shows the status of the protection.
0Software is able to write to all protected bits.
1Software is unable to write to any protected
bits.
MODE
PASS[7:3]whPassword Bits
The Bit Protection Scheme only recognizes three
patterns.
11000B Enables writing of the bit field MODE.
10011
10101
Data Sheet30V1.2, 2009-07
Opens access to writing of all protected bits.
B
Closes access to writing of all protected bits
B
XC886/888CLM
Functional Description
3.2.4XC886/888 Register Overview
The SFRs of the XC886/888 are organized into groups according to their functional units.
The contents (bits) of the SFRs are summarized in Chapter 3.2.4.1 to Chapter 3.2.4.14.
Note: The addresses of the bitaddressable SFRs appear in bold typeface.
3.2.4.1CPU Registers
The CPU SFRs can be accessed in both the standard and mapped memory areas
(RMAP = 0 or 1).
Table 5CPU Register Overview
Addr Register NameBit76543210
RMAP = 0 or 1
81
82
83
87
88
89
8A
8B
8C
8D
98
99
A2
SPReset: 07
H
Stack Pointer Register
DPLReset: 00
H
Data Pointer Register Low
DPHReset: 00
H
Data Pointer Register High
PCONReset: 00
H
Power Control Register
TCONReset: 00
H
Timer Control Register
TMODReset: 00
H
Timer Mode Register
TL0Reset: 00
H
Timer 0 Register Low
TL1Reset: 00
H
Timer 1 Register Low
TH0Reset: 00
H
Timer 0 Register High
TH1Reset: 00
H
Timer 1 Register High
SCONReset: 00
H
Serial Channel Control Register
SBUFReset: 00
H
Serial Data Buffer Register
EOReset: 00
H
Extended Operation Register
Bit Field
H
Typerw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrrwrwrrw
Bit Field
H
Typerwhrwrwhrwrwhrwrwhrw
Bit Field
H
Typerwrwrwrwrwrw
Bit Field
H
Typerwh
Bit Field
H
Typerwh
Bit Field
H
Typerwh
Bit Field
H
Typerwh
Bit Field
H
Typerwrwrwrwrwrwhrwhrwh
Bit Field
H
Typerwh
Bit Field
H
Typerrwrrw
DPL7DPL6DPL5DPL4DPL3DPL2DPL1DPL0
DPH7DPH6DPH5DPH4DPH3DPH2DPH1DPH0
SMOD0GF1GF00IDLE
TF1TR1TF0TR0IE1IT1IE0IT0
GATE1T1ST1MGATE0T0ST0M
SM0SM1SM2RENTB8RB8TIRI
0TRAP_
SP
VAL
VAL
VAL
VAL
VAL
0DPSE
EN
L0
Data Sheet31V1.2, 2009-07
XC886/888CLM
Functional Description
Table 5CPU Register Overview (cont’d)
Addr Register NameBit76543210
A8
B8
B9
D0
E0
E8
F0
F8
F9
IEN0Reset: 00
H
Interrupt Enable Register 0
IPReset: 00
H
Interrupt Priority Register
IPHReset: 00
H
Interrupt Priority High Register
PSWReset: 00
H
Program Status Word Register
ACCReset: 00
H
Accumulator Register
IEN1Reset: 00
H
Interrupt Enable Register 1
BReset: 00
H
B Register
IP1Reset: 00
H
Interrupt Priority 1 Register
IPH1Reset: 00
H
Interrupt Priority 1 High Register
Bit Field
H
Type rw r rwrwrwrwrwrw
Bit Field
H
Typerrwrwrwrwrwrw
Bit Field
H
Typerrwrwrwrwrwrw
Bit Field
H
Typerwhrwhrwrwrwrwhrwrh
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
EA0ET2ESET1EX1ET0EX0
0PT2PSPT1PX1PT0PX0
0PT2HPSHPT1HPX1HPT0HPX0H
CYACF0RS1RS0OVF1P
ACC7ACC6ACC5ACC4ACC3ACC2ACC1ACC0
ECCIP3ECCIP2ECCIP1ECCIP0EXMEX2ESSCEADC
B7B6B5B4B3B2B1B0
PCCIP3PCCIP2PCCIP1PCCIP0PXMPX2PSSCPADC
PCCIP3HPCCIP2HPCCIP1HPCCIP0HPXMHPX2HPSSCHPADC
H
3.2.4.2MDU Registers
The MDU SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 6MDU Register Overview
Addr Register NameBit76543210
RMAP = 1
B0
B1
B2
B2
B3
MDUSTATReset: 00
H
MDU Status Register
MDUCONReset: 00
H
MDU Control Register
MD0Reset: 00
H
MDU Operand Register 0
MR0Reset: 00
H
MDU Result Register 0
MD1Reset: 00
H
MDU Operand Register 1
Bit Field
H
Typerrhrwhrwh
Bit Field
H
Typerwrwrwrwhrw
Bit Field
H
Typerw
Bit Field
H
Typerh
Bit Field
H
Typerw
IEIRRSELSTAR
0BSYIERRIRDY
OPCODE
T
DATA
DATA
DATA
Data Sheet32V1.2, 2009-07
XC886/888CLM
Functional Description
Table 6MDU Register Overview (cont’d)
Addr Register NameBit76543210
B3
B4
B4
B5
B5
B6
B6
B7
B7
MR1Reset: 00
H
MDU Result Register 1
MD2Reset: 00
H
MDU Operand Register 2
MR2Reset: 00
H
MDU Result Register 2
MD3Reset: 00
H
MDU Operand Register 3
MR3Reset: 00
H
MDU Result Register 3
MD4Reset: 00
H
MDU Operand Register 4
MR4Reset: 00
H
MDU Result Register 4
MD5Reset: 00
H
MDU Operand Register 5
MR5Reset: 00
H
MDU Result Register 5
Bit Field
H
Typerh
Bit Field
H
Typerw
Bit Field
H
Typerh
Bit Field
H
Typerw
Bit Field
H
Typerh
Bit Field
H
Typerw
Bit Field
H
Typerh
Bit Field
H
Typerw
Bit Field
H
Typerh
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
3.2.4.3CORDIC Registers
The CORDIC SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 7CORDIC Register Overview
Addr Register NameBit76543210
RMAP = 1
9A
9B
9C
9D
9E
9F
CD_CORDXLReset: 00
H
CORDIC X Data Low Byte
CD_CORDXHReset: 00
H
CORDIC X Data High Byte
CD_CORDYLReset: 00
H
CORDIC Y Data Low Byte
CD_CORDYHReset: 00
H
CORDIC Y Data High Byte
CD_CORDZLReset: 00
H
CORDIC Z Data Low Byte
CD_CORDZHReset: 00
H
CORDIC Z Data High Byte
Bit Field
H
Typerw
Bit Field
H
Typerw
Bit Field
H
Typerw
Bit Field
H
Typerw
Bit Field
H
Typerw
Bit Field
H
Typerw
DATAL
DATAH
DATAL
DATAH
DATAL
DATAH
Data Sheet33V1.2, 2009-07
XC886/888CLM
Functional Description
Table 7CORDIC Register Overview (cont’d)
Addr Register NameBit76543210
A0
A1
CD_STATCReset: 00
H
CORDIC Status and Data
Control Register
CD_CONReset: 00
H
CORDIC Control Register
Bit Field
H
Typerwrwrwrwrwrwhrhrh
Bit Field
H
Typerwrwrwrwrwrwh
KEEPZKEEPYKEEPXDMAPINT_ENEOCERRORBSY
MPSX_USIGNST_M
ODE
ROTV
EC
MODEST
3.2.4.4System Control Registers
The system control SFRs can be accessed in the mapped memory area (RMAP = 0).
Table 8SCU Register Overview
Addr Register NameBit76543210
RMAP = 0 or 1
8F
RMAP = 0
BF
RMAP = 0, PAGE 0
B3
B4
B5
B6
B7
BA
BB
SYSCON0Reset: 04
H
System Control Register 0
SCU_PAGEReset: 00
H
Page Register
MODPISELReset: 00
H
Peripheral Input Select Register
IRCON0Reset: 00
H
Interrupt Request Register 0
IRCON1Reset: 00
H
Interrupt Request Register 1
IRCON2Reset: 00
H
Interrupt Request Register 2
EXICON0Reset: F0
H
External Interrupt Control
Register 0
EXICON1Reset: 3F
H
External Interrupt Control
Register 1
NMICONReset: 00
H
NMI Control Register
Bit Field
H
Typerrwrrrrw
Bit Field
H
Typewwrrw
Bit Field
H
Type r rwrwrwrwrwrwrw
Bit Field
H
Typerrwhrwhrwhrwhrwhrwhrwh
Bit Field
H
Typerrwhrwhrwhrwhrwhrwhrwh
Bit Field
H
Type rrwhrrwh
Bit Field
H
Typerwrwrwrw
Bit Field
H
Typer rwrwrw
Bit Field
H
Type r rwrwrwrwrwrwrw
0URRISHJTAGT
0EXINT6EXINT5EXINT4EXINT3EXINT2EXINT1EXINT
0CANS
0NMI
0IMOD
OPSTNR0PAGE
DIS
RC2
EXINT3EXINT2EXINT1EXINT0
0EXINT6EXINT5EXINT4
ECC
CANS
RC1
0CANS
NMI
VDDP
E
JTAGT
CKS
ADCSR1ADCSR0RIRTIREIR
RC3
NMI
VDD
010RMAP
EXINT
NMI
OCDS
2IS
EXINT
FLASH
EXINT
1IS
0CANS
NMI
0IS
NMI
PLL
URRIS
0
RC0
NMI
WDT
Data Sheet34V1.2, 2009-07
XC886/888CLM
Functional Description
Table 8SCU Register Overview (cont’d)
Addr Register NameBit76543210
BC
BD
BE
E9
EA
EB
RMAP = 0, PAGE 1
B3
B4
B5
B6
B7
BA
BB
BC
BD
NMISRReset: 00
H
NMI Status Register
BCONReset: 00
H
Baud Rate Control Register
BGReset: 00
H
Baud Rate Timer/Reload
Register
FDCONReset: 00
H
Fractional Divider Control
Register
FDSTEPReset: 00
H
Fractional Divider Reload
Register
FDRESReset: 00
H
Fractional Divider Result
Register
IDReset: UU
H
Identity Register
PMCON0Reset: 00
H
Power Mode Control Register 0
PMCON1Reset: 00
H
Power Mode Control Register 1
OSC_CONReset: 08
H
OSC Control Register
PLL_CONReset: 90
H
PLL Control Register
CMCONReset: 10
H
Clock Control Register
PASSWDReset: 07
H
Password Register
FEALReset: 00
H
Flash Error Address Register
Low
FEAHReset: 00
H
Flash Error Address Register
High
Bit Field
H
Typerrwhrwhrwhrwhrwhrwhrwh
Bit Field
H
Typerwrrwrwrw
Bit Field
H
Typerwh
Bit Field
H
Typerwrwrwhrwhrwhrwhrwrw
Bit Field
H
Typerw
Bit Field
H
Typerh
Bit Field
H
Typerr
Bit Field
H
Typerrwhrwhrwrwrwhrw
Bit Field
H
Type r rwrwrwrwrwrwrw
Bit Field
H
Typerrwrwrwrwhrh
Bit Field
H
Typerwrwrwrwhrh
Bit Field
H
Typerwrwrrwrw
Bit Field
H
Typewhrhrw
Bit Field
H
Typerh
Bit Field
H
Typerh
0FNMI
ECC
BGSEL0BRDISBRPRER
BGSSYNENERRSYNEOFSYNBRKNDOVFDMFDEN
0WDT
RST
0CDC_
VCO
SEL
DIS
KDIV0FCCF
FNMI
VDDP
PRODIDVERID
WKRSWK
CAN_
DIS
0OSCPDXPDOSCSSORD
NDIVVCO
PASSPROT
FNMI
VDD
SEL
MDU_
DIS
ECCERRADDR
ECCERRADDR
FNMI
OCDS
BR_VALUE
STEP
RESULT
SDPDWS
T2_
DIS
BYP
G
FNMI
FLASH
CCU_
DIS
OSC
DISC
CLKREL
ECT_S
FNMI
PLL
SSC_
DIS
RES
RESLDLOCK
MODE
FNMI
WDT
ADC_
DIS
OSCR
Data Sheet35V1.2, 2009-07
XC886/888CLM
Functional Description
Table 8SCU Register Overview (cont’d)
Addr Register NameBit76543210
BE
E9
RMAP = 0, PAGE 3
B3
B4
B5
B7
BA
BB
BD
COCONReset: 00
H
Clock Output Control Register
MISC_CONReset: 00
H
Miscellaneous Control Register
XADDRHReset: F0
H
On-chip XRAM Address Higher
Order
IRCON3Reset: 00
H
Interrupt Request Register 3
IRCON4Reset: 00
H
Interrupt Request Register 4
MODPISEL1Reset: 00
H
Peripheral Input Select Register
1
MODPISEL2Reset: 00
H
Peripheral Input Select Register
2
PMCON2Reset: 00
H
Power Mode Control Register 2
MODSUSPReset: 01
H
Module Suspend Control
Register
Bit Field
H
Typerrwrwrw
Bit Field
H
Typerrwh
Bit Field
H
Typerw
Bit Field
H
Typerrwhrwhrrwhrwh
Bit Field
H
Typerrwhrwhrrwhrwh
Bit Field
H
Typerwrrwrwrwrw
Bit Field
H
Typerrwrwrwrw
Bit Field
H
Typerrwrw
Bit Field
H
Typerrwrwrwrwrw
0TLENCOUT
0CANS
0CANS
EXINT
6IS
0UR1RIST21EXISJTAGT
0T21IST2IST1IST0IS
0T21SUSPT2SUSPT13SUSPT12SUSPWDTS
S
0DFLAS
ADDRH
RC5
RC7
CCU6
SR1
CCU6
SR3
0UART
0CANS
0CANS
COREL
RC4
RC6
DIS1
1_DIS
HEN
CCU6
SR0
CCU6
SR2
JTAGT
CKS1
T21_D
USP
IS
3.2.4.5WDT Registers
The WDT SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 9WDT Register Overview
Addr Register NameBit76543210
RMAP = 1
BB
BC
BD
WDTCONReset: 00
H
Watchdog Timer Control
Register
WDTRELReset: 00
H
Watchdog Timer Reload
Register
WDTWINBReset: 00
H
Watchdog Window-Boundary
Count Register
Bit Field
H
Typerrwrhrrwrwhrw
Bit Field
H
Typerw
Bit Field
H
Typerw
Data Sheet36V1.2, 2009-07
0WINBENWDTP
R
WDTREL
WDTWINB
0WDTENWDTRSWDTI
N
XC886/888CLM
Functional Description
Table 9WDT Register Overview (cont’d)
Addr Register NameBit76543210
BE
BF
WDTLReset: 00
H
Watchdog Timer Register Low
WDTHReset: 00
H
Watchdog Timer Register High
Bit Field
H
Typerh
Bit Field
H
Typerh
WDT
WDT
3.2.4.6Port Registers
The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Table 10Port Register Overview
Addr Register NameBit76543210
RMAP = 0
B2
RMAP = 0, PAGE 0
80
86
90
91
92
93
A0
A1
B0
B1
C8
C9
PORT_PAGEReset: 00
H
Page Register
P0_DATAReset: 00
H
P0 Data Register
P0_DIRReset: 00
H
P0 Direction Register
P1_DATAReset: 00
H
P1 Data Register
P1_DIRReset: 00
H
P1 Direction Register
P5_DATAReset: 00
H
P5 Data Register
P5_DIRReset: 00
H
P5 Direction Register
P2_DATAReset: 00
H
P2 Data Register
P2_DIRReset: 00
H
P2 Direction Register
P3_DATAReset: 00
H
P3 Data Register
P3_DIRReset: 00
H
P3 Direction Register
P4_DATAReset: 00
H
P4 Data Register
P4_DIRReset: 00
H
P4 Direction Register
Bit Field
H
Typewwrrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
OPSTNR0PAGE
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
Data Sheet37V1.2, 2009-07
XC886/888CLM
Functional Description
Table 10Port Register Overview (cont’d)
Addr Register NameBit76543210
RMAP = 0, PAGE 1
80
86
90
91
92
93
A0
A1
B0
B1
C8
C9
RMAP = 0, PAGE 2
80
86
90
91
92
P0_PUDSELReset: FF
H
P0 Pull-Up/Pull-Down Select
Register
P0_PUDENReset: C4
H
P0 Pull-Up/Pull-Down Enable
Register
P1_PUDSELReset: FF
H
P1 Pull-Up/Pull-Down Select
Register
P1_PUDENReset: FF
H
P1 Pull-Up/Pull-Down Enable
Register
P5_PUDSELReset: FF
H
P5 Pull-Up/Pull-Down Select
Register
P5_PUDENReset: FF
H
P5 Pull-Up/Pull-Down Enable
Register
P2_PUDSELReset: FF
H
P2 Pull-Up/Pull-Down Select
Register
P2_PUDENReset: 00
H
P2 Pull-Up/Pull-Down Enable
Register
P3_PUDSELReset: BF
H
P3 Pull-Up/Pull-Down Select
Register
P3_PUDENReset: 40
H
P3 Pull-Up/Pull-Down Enable
Register
P4_PUDSELReset: FF
H
P4 Pull-Up/Pull-Down Select
Register
P4_PUDENReset: 04
H
P4 Pull-Up/Pull-Down Enable
Register
P0_ALTSEL0Reset: 00
H
P0 Alternate Select 0 Register
P0_ALTSEL1Reset: 00
H
P0 Alternate Select 1 Register
P1_ALTSEL0Reset: 00
H
P1 Alternate Select 0 Register
P1_ALTSEL1Reset: 00
H
P1 Alternate Select 1 Register
P5_ALTSEL0Reset: 00
H
P5 Alternate Select 0 Register
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
Data Sheet38V1.2, 2009-07
XC886/888CLM
Functional Description
Table 10Port Register Overview (cont’d)
Addr Register NameBit76543210
93
B0
B1
C8
C9
RMAP = 0, PAGE 3
80
90
92
B0
C8
P5_ALTSEL1Reset: 00
H
P5 Alternate Select 1 Register
P3_ALTSEL0Reset: 00
H
P3 Alternate Select 0 Register
P3_ALTSEL1Reset: 00
H
P3 Alternate Select 1 Register
P4_ALTSEL0Reset: 00
H
P4 Alternate Select 0 Register
P4_ALTSEL1Reset: 00
H
P4 Alternate Select 1 Register
P0_ODReset: 00
H
P0 Open Drain Control Register
P1_ODReset: 00
H
P1 Open Drain Control Register
P5_ODReset: 00
H
P5 Open Drain Control Register
P3_ODReset: 00
H
P3 Open Drain Control Register
P4_ODReset: 00
H
P4 Open Drain Control Register
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
3.2.4.7ADC Registers
The ADC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 11ADC Register Overview
AddrRegister NameBit 76543210
RMAP = 0
D1
RMAP = 0, PAGE 0
CA
CB
CC
ADC_PAGEReset: 00
H
Page Register
ADC_GLOBCTR Reset: 30
H
Global Control Register
ADC_GLOBSTR Reset: 00
H
Global Status Register
ADC_PRARReset: 00
H
Priority and Arbitration Register
Data Sheet39V1.2, 2009-07
Bit Field
H
Typewwrrw
Bit Field
H
Typerwrwrwr
Bit Field
H
Typerrhrrhrh
Bit Field
H
Typerwrwrrwrwrwrwrw
OPSTNR0PAGE
ANONDWCTC0
0CHNR0SAMPLEBUSY
ASEN1ASEN
0
0ARBMCSM1PRIO1CSM0PRIO0
XC886/888CLM
Functional Description
Table 11ADC Register Overview (cont’d)
AddrRegister NameBit 76543210
CD
CE
CF
RMAP = 0, PAGE 1
CA
CB
CC
CD
CE
CF
D2
D3
RMAP = 0, PAGE 2
CA
CB
CC
CD
CE
CF
D2
ADC_LCBRReset: B7
H
Limit Check Boundary Register
ADC_INPCR0Reset: 00
H
Input Class 0 Register
ADC_ETRCRReset: 00
H
External Trigger Control
Register
ADC_CHCTR0Reset: 00
H
Channel Control Register 0
ADC_CHCTR1Reset: 00
H
Channel Control Register 1
ADC_CHCTR2Reset: 00
H
Channel Control Register 2
ADC_CHCTR3Reset: 00
H
Channel Control Register 3
ADC_CHCTR4Reset: 00
H
Channel Control Register 4
ADC_CHCTR5Reset: 00
H
Channel Control Register 5
ADC_CHCTR6Reset: 00
H
Channel Control Register 6
ADC_CHCTR7Reset: 00
H
Channel Control Register 7
ADC_RESR0LReset: 00
H
Result Register 0 Low
ADC_RESR0HReset: 00
H
Result Register 0 High
ADC_RESR1LReset: 00
H
Result Register 1 Low
ADC_RESR1HReset: 00
H
Result Register 1 High
ADC_RESR2LReset: 00
H
Result Register 2 Low
ADC_RESR2HReset: 00
H
Result Register 2 High
ADC_RESR3LReset: 00
H
Result Register 3 Low
Bit Field
H
Typerwrw
Bit Field
H
Typerw
Bit Field
H
Typerwrwrwrw
Bit Field
H
Typerrwrrw
Bit Field
H
Typerrwrrw
Bit Field
H
Typerrwrrw
Bit Field
H
Typerrwrrw
Bit Field
H
Typerrwrrw
Bit Field
H
Typerrwrrw
Bit Field
H
Typerrwrrw
Bit Field
H
Typerrwrrw
Bit Field
H
Typerhrrhrhrh
Bit Field
H
Typerh
Bit Field
H
Typerhrrhrhrh
Bit Field
H
Typerh
Bit Field
H
Typerhrrhrhrh
Bit Field
H
Typerh
Bit Field
H
Typerhrrhrhrh
SYNEN1SYNE
0LCC0RESRSEL
0LCC0RESRSEL
0LCC0RESRSEL
0LCC0RESRSEL
0LCC0RESRSEL
0LCC0RESRSEL
0LCC0RESRSEL
0LCC0RESRSEL
RESULT0VFDRCCHNR
RESULT0VFDRCCHNR
RESULT0VFDRCCHNR
RESULT0VFDRCCHNR
BOUND1BOUND0
STC
ETRSEL1ETRSEL0
N0
RESULT
RESULT
RESULT
Data Sheet40V1.2, 2009-07
XC886/888CLM
Functional Description
Table 11ADC Register Overview (cont’d)
AddrRegister NameBit 76543210
D3
RMAP = 0, PAGE 3
CA
CB
CC
CD
CE
CF
D2
D3
RMAP = 0, PAGE 4
CA
CB
CC
CD
CE
RMAP = 0, PAGE 5
CA
CB
ADC_RESR3HReset: 00
H
Result Register 3 High
ADC_RESRA0L Reset: 00
H
Result Register 0, View A Low
ADC_RESRA0H Reset: 00
H
Result Register 0, View A High
ADC_RESRA1L Reset: 00
H
Result Register 1, View A Low
ADC_RESRA1H Reset: 00
H
Result Register 1, View A High
ADC_RESRA2L Reset: 00
H
Result Register 2, View A Low
ADC_RESRA2H Reset: 00
H
Result Register 2, View A High
ADC_RESRA3L Reset: 00
H
Result Register 3, View A Low
ADC_RESRA3H Reset: 00
H
Result Register 3, View A High
ADC_RCR0Reset: 00
H
Result Control Register 0
ADC_RCR1Reset: 00
H
Result Control Register 1
ADC_RCR2Reset: 00
H
Result Control Register 2
ADC_RCR3Reset: 00
H
Result Control Register 3
ADC_VFCRReset: 00
H
Valid Flag Clear Register
ADC_CHINFRReset: 00
H
Channel Interrupt Flag Register
ADC_CHINCRReset: 00
H
Channel Interrupt Clear Register
Bit Field
H
Typerh
Bit Field
H
Typerhrhrhrh
Bit Field
H
Typerh
Bit Field
H
Typerhrhrhrh
Bit Field
H
Typerh
Bit Field
H
Typerhrhrhrh
Bit Field
H
Typerh
Bit Field
H
Typerhrhrhrh
Bit Field
H
Typerh
Bit Field
H
Typerwrwrrwrrw
Bit Field
H
Typerwrwrrwrrw
Bit Field
H
Typerwrwrrwrrw
Bit Field
H
Typerwrwrrwrrw
Bit Field
H
Typerwwww
Bit Field
H
Typerhrhrhrhrhrhrhrh
Bit Field
H
Typewwwwwwww
CHINF7CHINF6CHINF5CHINF4CHINF3CHINF2CHINF1CHINF
CHINC7CHINC6CHINC5CHINC4CHINC3CHINC2CHINC1CHINC
RESULTVFDRCCHNR
RESULTVFDRCCHNR
RESULTVFDRCCHNR
RESULTVFDRCCHNR
VFCTRWFR0IEN0DRCT
VFCTRWFR0IEN0DRCT
VFCTRWFR0IEN0DRCT
VFCTRWFR0IEN0DRCT
0VFC3VFC2VFC1VFC0
RESULT
RESULT
RESULT
RESULT
RESULT
R
R
R
R
0
0
Data Sheet41V1.2, 2009-07
XC886/888CLM
Functional Description
Table 11ADC Register Overview (cont’d)
AddrRegister NameBit 76543210
CC
CD
CE
CF
D2
D3
RMAP = 0, PAGE 6
CA
CB
CC
CD
CE
CF
D2
D2
ADC_CHINSRReset: 00
H
Channel Interrupt Set Register
ADC_CHINPRReset: 00
H
Channel Interrupt Node Pointer
Register
ADC_EVINFRReset: 00
H
Event Interrupt Flag Register
ADC_EVINCRReset: 00
H
Event Interrupt Clear Flag
Register
ADC_EVINSRReset: 00
H
Event Interrupt Set Flag Register
ADC_EVINPRReset: 00
H
Event Interrupt Node Pointer
Register
ADC_CRCR1Reset: 00
H
Conversion Request Control
Register 1
ADC_CRPR1Reset: 00
H
Conversion Request Pending
Register 1
ADC_CRMR1Reset: 00
H
Conversion Request Mode
Register 1
ADC_QMR0Reset: 00
H
Queue Mode Register 0
ADC_QSR0Reset: 20
H
Queue Status Register 0
ADC_Q0R0Reset: 00
H
Queue 0 Register 0
ADC_QBUR0Reset: 00
H
Queue Backup Register 0
ADC_QINR0Reset: 00
H
Queue Input Register 0
Bit Field
H
Typewwwwwwww
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerhrhrhrhrrhrh
Bit Field
H
Typewwwwrww
Bit Field
H
Typewwwwrww
Bit Field
H
Typerwrwrwrwrrwrw
Bit Field
H
Typerwhrwhrwhrwhr
Bit Field
H
Typerwhrwhrwhrwhr
Bit Field
H
Typerwwrwrwrwrrw
Bit Field
H
Typewwww rrwrrw
Bit Field
H
Typerrrhrhrrh
Bit Field
H
Typerhrhrhrhrrh
Bit Field
H
Typerhrhrhrhrrh
Bit Field
H
Typewwwrw
CHINS7CHINS6CHINS5CHINS4CHINS3CHINS2CHINS1CHINS
CHINP7CHINP6CHINP5CHINP4CHINP3CHINP2CHINP1CHINP
EVINF7EVINF6EVINF5EVINF
4
EVINC7EVINC6EVINC5EVINC
4
EVINS7EVINS6EVINS5EVINS
4
EVINP7EVINP6EVINP5EVINP
4
CH7CH6CH5CH40
CHP7CHP6CHP5CHP40
RsvLDEVCLRPNDSCANENSIENTR0ENGT
CEVTREVFLUSHCLRV0ENTR0ENGT
Rsv0EMPTYEV0FILL
EXTRENSIRFV0REQCHNR
EXTRENSIRFV0REQCHNR
EXTRENSIRF0REQCHNR
0EVINF1EVINF
0EVINC1EVINC
0EVINS1EVINS
0EVINP1EVINP
0
0
0
0
0
0
Data Sheet42V1.2, 2009-07
XC886/888CLM
Functional Description
3.2.4.8Timer 2 Registers
The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 12T2 Register Overview
Addr Register NameBit76543210
RMAP = 0
C0
C1
C2
C3
C4
C5
T2_T2CONReset: 00
H
Timer 2 Control Register
T2_T2MODReset: 00
H
Timer 2 Mode Register
T2_RC2LReset: 00
H
Timer 2 Reload/Capture
Register Low
T2_RC2HReset: 00
H
Timer 2 Reload/Capture
Register High
T2_T2LReset: 00
H
Timer 2 Register Low
T2_T2HReset: 00
H
Timer 2 Register High
Bit Field
H
Typerwhrwhrrwrwhrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwh
Bit Field
H
Typerwh
Bit Field
H
Typerwh
Bit Field
H
Typerwh
TF2EXF20EXEN2TR2C/T2CP/
T2REGST2RHENEDGE
SEL
PRENT2PREDCEN
RC2
RC2
THL2
THL2
RL2
3.2.4.9Timer 21 Registers
The Timer 21 SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 13T21 Register Overview
Addr Register NameBit76543210
RMAP = 1
C0
C1
C2
C3
C4
T21_T2CONReset: 00
H
Timer 2 Control Register
T21_T2MODReset: 00
H
Timer 2 Mode Register
T21_RC2LReset: 00
H
Timer 2 Reload/Capture
Register Low
T21_RC2HReset: 00
H
Timer 2 Reload/Capture
Register High
T21_T2LReset: 00
H
Timer 2 Register Low
Bit Field
H
Typerwhrwhrrwrwhrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwh
Bit Field
H
Typerwh
Bit Field
H
Typerwh
TF2EXF20EXEN2TR2C/T2CP/
T2REGST2RHENEDGE
SEL
PRENT2PREDCEN
RC2
RC2
THL2
RL2
Data Sheet43V1.2, 2009-07
XC886/888CLM
Functional Description
Table 13T21 Register Overview (cont’d)
Addr Register NameBit76543210
C5
T21_T2HReset: 00
H
Timer 2 Register High
Bit Field
H
Typerwh
THL2
3.2.4.10CCU6 Registers
The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 14CCU6 Register Overview
AddrRegister NameBit 76543210
RMAP = 0
A3
RMAP = 0, PAGE 0
9A
9B
9C
9D
9E
9F
A4
A5
A6
A7
CCU6_PAGEReset: 00
H
Page Register
CCU6_CC63SRLReset: 00
H
Capture/Compare Shadow Register
for Channel CC63 Low
CCU6_CC63SRHReset: 00
H
Capture/Compare Shadow Register
for Channel CC63 High
CCU6_TCTR4LReset: 00
H
Timer Control Register 4 Low
CCU6_TCTR4HReset: 00
H
Timer Control Register 4 High
CCU6_MCMOUTSLReset: 00
H
Multi-Channel Mode Output Shadow
Register Low
CCU6_MCMOUTSHReset: 00
H
Multi-Channel Mode Output Shadow
Register High
CCU6_ISRLReset: 00
H
Capture/Compare Interrupt Status
Reset Register Low
CCU6_ISRHReset: 00
H
Capture/Compare Interrupt Status
Reset Register High
CCU6_CMPMODIFLReset: 00
H
Compare State Modification Register
Low
CCU6_CMPMODIFHReset: 00
H
Compare State Modification Register
High
Bit Field
H
Typewwrrw
Bit Field
H
Typerw
Bit Field
H
Typerw
Bit Field
H
Type wwrwwww
Bit Field
H
Type wwrwww
Bit Field
H
Typewrrw
Bit Field
H
Typewrrwrw
Bit Field
H
Type wwwwwwww
Bit Field
H
Type wwww r www
Bit Field
H
Type r wrwww
Bit Field
H
Type r wrwww
OPSTNR0PAGE
CC63SL
CC63SH
T12
STD
T13
STD
STRMCM0MCMPS
STRHP0CURHSEXPHS
RT12PMRT12OMRCC62FRCC62RRCC61FRCC61RRCC60FRCC6
RSTR RIDLERWHERCHE0RTRPFRT13PMRT13
T12
STR
T13
STR
0MCC6
3S
0MCC6
3R
0DT
RES
0T13
0MCC62SMCC61SMCC6
0MCC62RMCC61RMCC6
T12
RES
RES
T12RST12R
T13RST13R
R
R
0R
CM
0S
0R
Data Sheet44V1.2, 2009-07
XC886/888CLM
Functional Description
Table 14CCU6 Register Overview (cont’d)
AddrRegister NameBit 76543210
FA
FB
FC
FD
FE
FF
RMAP = 0, PAGE 1
9A
9B
9C
9D
9E
9F
A4
A5
A6
A7
FA
CCU6_CC60SRLReset: 00
H
Capture/Compare Shadow Register
for Channel CC60 Low
CCU6_CC60SRHReset: 00
H
Capture/Compare Shadow Register
for Channel CC60 High
CCU6_CC61SRLReset: 00
H
Capture/Compare Shadow Register
for Channel CC61 Low
CCU6_CC61SRHReset: 00
H
Capture/Compare Shadow Register
for Channel CC61 High
CCU6_CC62SRLReset: 00
H
Capture/Compare Shadow Register
for Channel CC62 Low
CCU6_CC62SRHReset: 00
H
Capture/Compare Shadow Register
for Channel CC62 High
Capture/Compare Interrupt Node
Pointer Register High
CCU6_ISSLReset: 00
H
Capture/Compare Interrupt Status
Set Register Low
CCU6_ISSHReset: 00
H
Capture/Compare Interrupt Status
Set Register High
CCU6_PSLRReset: 00
H
Passive State Level Register
CCU6_MCMCTRReset: 00
H
Multi-Channel Mode Control Register
CCU6_TCTR2LReset: 00
H
Timer Control Register 2 Low
Bit Field
H
Typerh
Bit Field
H
Typerh
Bit Field
H
Typerh
Bit Field
H
Typerh
Bit Field
H
Typerh
Bit Field
H
Typerwrw
Bit Field
H
Typerwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrrwrwrw
Bit Field
H
Typerwrwrwrw
Bit Field
H
Typerrwrwrw
Bit Field
H
Type wwwwwwww
Bit Field
H
Type wwwwwwww
Bit Field
H
Typerwhrrwh
Bit Field
H
Typerrwrrw
Bit Field
H
Typerrwrwrwrw
DBYPHSYNCMSEL62
ENT1
2
PM
EN
STRENIDLEENWHEENCHE
INPCHEINPCC62INPCC61INPCC60
ST12PMST12OMSCC62FSCC62RSCC61FSCC61RSCC60FSCC6
SSTRSIDLE SWHE SCHESWHCSTRPFST13PMST13
PSL630PSL
0T13TEDT13TECT13
MSEL61MSEL60
ENT1
0INPT13INPT12INPERR
0SWSYN0SWSEL
2
OM
ENCC
62F
CC60VH
CC61VL
CC61VH
CC62VL
CC62VH
ENCC
62R
ENCC
61F
0EN
ENCC
61R
TRPF
ENCC
60F
ENT1
3PM
SSC
ENCC
ENT1
60R
3CM
0R
CM
T12
SSC
Data Sheet46V1.2, 2009-07
XC886/888CLM
Functional Description
Table 14CCU6 Register Overview (cont’d)
AddrRegister NameBit 76543210
FB
FC
FD
FE
FF
RMAP = 0, PAGE 3
9A
9B
9C
9D
9E
9F
A4
FA
FB
FC
FD
CCU6_TCTR2HReset: 00
H
Timer Control Register 2 High
CCU6_MODCTRLReset: 00
H
Modulation Control Register Low
CCU6_MODCTRHReset: 00
H
Modulation Control Register High
CCU6_TRPCTRLReset: 00
H
Trap Control Register Low
CCU6_TRPCTRHReset: 00
H
Trap Control Register High
CCU6_MCMOUTLReset: 00
H
Multi-Channel Mode Output Register
Low
CCU6_MCMOUTHReset: 00
H
Multi-Channel Mode Output Register
High
CCU6_ISLReset: 00
H
Capture/Compare Interrupt Status
Register Low
CCU6_ISHReset: 00
H
Capture/Compare Interrupt Status
Register High
CCU6_PISEL0LReset: 00
H
Port Input Select Register 0 Low
CCU6_PISEL0HReset: 00
H
Port Input Select Register 0 High
CCU6_PISEL2Reset: 00
H
Port Input Select Register 2
CCU6_T12LReset: 00
H
Timer T12 Counter Register Low
CCU6_T12HReset: 00
H
Timer T12 Counter Register High
CCU6_T13LReset: 00
H
Timer T13 Counter Register Low
CCU6_T13HReset: 00
H
Timer T13 Counter Register High
Bit Field
H
Typerrwrw
Bit Field
H
Typerwrrw
Bit Field
H
Typerwrrw
Bit Field
H
Typerrwrwrw
Bit Field
H
Typerwrwrw
Bit Field
H
Typerrhrh
Bit Field
H
Typerrhrh
Bit Field
H
Typerhrhrhrhrhrhrhrh
Bit Field
H
Typerhrhrhrhrhrhrhrh
Bit Field
H
Typerwrwrwrw
Bit Field
H
Typerwrwrwrw
Bit Field
H
Typerrw
Bit Field
H
Typerwh
Bit Field
H
Typerwh
Bit Field
H
Typerwh
Bit Field
H
Typerwh
MCM
EN
ECT1
3O
TRPPENTRPE
0RMCMP
0CURHEXPH
T12PMT12OMICC62FICC62RICC61FICC61RICC60FICC60
STRIDLEWHECHETRPSTRPFT13PMT13
ISTRPISCC62ISCC61ISCC60
IST12HRISPOS2ISPOS1ISPOS0
0T13RSELT12RSEL
0T12MODEN
0T13MODEN
0TRPM2TRPM1TRPM
TRPEN
N13
0IST13HR
T12CVL
T12CVH
T13CVL
T13CVH
0
R
CM
Data Sheet47V1.2, 2009-07
XC886/888CLM
Functional Description
Table 14CCU6 Register Overview (cont’d)
AddrRegister NameBit 76543210
FE
FF
CCU6_CMPSTATLReset: 00
H
Compare State Register Low
CCU6_CMPSTATHReset: 00
H
Compare State Register High
Bit Field
H
Type r rhrhrhrhrhrhrh
Bit Field
H
Typerwhrwhrwhrwhrwhrwhrwhrwh
0CC63STCC
T13IM COUT
63PS
POS2CCPOS1CCPOS0
COUT
62PS
CC62PSCOUT
61PS
CC62STCC61STCC60
CC61PSCOUT
60PS
CC60
ST
PS
3.2.4.11UART1 Registers
The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 15UART1 Register Overview
Addr Register NameBit76543210
RMAP = 1
C8
C9
CA
CB
CC
CD
CE
SCONReset: 00
H
Serial Channel Control Register
SBUFReset: 00
H
Serial Data Buffer Register
BCONReset: 00
H
Baud Rate Control Register
BGReset: 00
H
Baud Rate Timer/Reload
Register
FDCONReset: 00
H
Fractional Divider Control
Register
FDSTEPReset: 00
H
Fractional Divider Reload
Register
FDRESReset: 00
H
Fractional Divider Result
Register
Bit Field
H
Typerwrwrwrwrwrwhrwhrwh
Bit Field
H
Typerwh
Bit Field
H
Typerrwrw
Bit Field
H
Typerwh
Bit Field
H
Typerrwhrwrw
Bit Field
H
Typerw
Bit Field
H
Typerh
SM0SM1SM2RENTB8RB8TIRI
VAL
0BRPRER
BR_VALUE
0NDOVFDMFDEN
STEP
RESULT
Data Sheet48V1.2, 2009-07
XC886/888CLM
Functional Description
3.2.4.12SSC Registers
The SSC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 16SSC Register Overview
Addr Register NameBit76543210
RMAP = 0
A9
AA
AA
AB
AB
AC
AD
AE
AF
SSC_PISELReset: 00
H
Port Input Select Register
SSC_CONLReset: 00
H
Control Register Low
Programming Mode
SSC_CONLReset: 00
H
Control Register Low
Operating Mode
SSC_CONHReset: 00
H
Control Register High
Programming Mode
SSC_CONHReset: 00
H
Control Register High
Operating Mode
SSC_TBLReset: 00
H
Transmitter Buffer Register Low
SSC_RBLReset: 00
H
Receiver Buffer Register Low
SSC_BRLReset: 00
H
Baud Rate Timer Reload
Register Low
SSC_BRHReset: 00
H
Baud Rate Timer Reload
Register High
Bit Field
H
Typerrwrwrw
Bit Field
H
Typerwrwrwrwrw
Bit Field
H
Typerrh
Bit Field
H
Typerwrwrrwrwrwrwrw
Bit Field
H
Typerwrwrrhrwhrwhrwhrwh
Bit Field
H
Typerw
Bit Field
H
Typerh
Bit Field
H
Typerw
Bit Field
H
Typerw
LBPOPHHBBM
ENMS0ARENBENPENRENTEN
ENMS0BSYBEPERETE
0CISSISMIS
0BC
TB_VALUE
RB_VALUE
BR_VALUE
BR_VALUE
3.2.4.13MultiCAN Registers
The MultiCAN SFRs can be accessed in the standard memory area (RMAP = 0).
Table 17CAN Register Overview
Addr Register NameBit76543210
RMAP = 0
D8
D9
DA
Data Sheet49V1.2, 2009-07
ADCONReset: 00
H
CAN Address/Data Control
Register
ADLReset: 00
H
CAN Address Register Low
ADHReset: 00
H
CAN Address Register High
Bit Field
H
Typerwrwrwrwrwrhrw
Bit Field
H
Typerwhrwhrwhrwhrwhrwhrwhrwh
Bit Field
H
Typerrwhrwhrwhrwh
V3V2V1V0AUADBSYRWEN
CA9CA8CA7CA6CA5CA4CA3CA2
0CA13CA12CA11CA10
XC886/888CLM
Functional Description
Table 17CAN Register Overview (cont’d)
Addr Register NameBit76543210
DB
DC
DD
DE
DATA0Reset: 00
H
CAN Data Register 0
DATA1Reset: 00
H
CAN Data Register 1
DATA2Reset: 00
H
CAN Data Register 2
DATA3Reset: 00
H
CAN Data Register 3
Bit Field
H
Typerwh
Bit Field
H
Typerwh
Bit Field
H
Typerwh
Bit Field
H
Typerwh
CD
CD
CD
CD
3.2.4.14OCDS Registers
The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 18OCDS Register Overview
Addr Register NameBit76543210
RMAP = 1
E9
F1
F2
F3
F4
F5
F6
F7
EB
MMCR2Reset: 1U
H
Monitor Mode Control 2
Register
MMCRReset: 00
H
Monitor Mode Control Register
MMSRReset: 00
H
Monitor Mode Status Register
MMBPCRReset: 00
H
Breakpoints Control Register
MMICRReset: 00
H
Monitor Mode Interrupt Control
Register
MMDRReset: 00
H
Monitor Mode Data Transfer
Register
Receive
HWBPSRReset: 00
H
Hardware Breakpoints Select
Register
HWBPDRReset: 00
H
Hardware Breakpoints Data
Register
MMWR1Reset: 00
H
Monitor Work Register 1
Bit Field
H
Typerwrwrwrwhrwrwhrhrh
Bit Field
H
Typewrwhrrwwrwhrhrh
Bit Field
H
Typerwrwhrwhrwhrwhrwhrwhrwh
Bit Field
H
Typerwrwrwrwrw
Bit Field
H
Typerwhrwhrwhrhwrwwrw
Bit Field
H
Typerh
Bit Field
H
Typerwrw
Bit Field
H
Typerw
Bit Field
H
Typerw
STMODEEXBCDSUSPMBCONALTDIMMEP MMODEJENA
MEXIT_PMEXIT0MSTEPMRAM
MBCAMMBCINEXBFSWBFHWB3FHWB2FHWB1FHWB0
SWBCHWB3CHWB2CHWB1
DVECTDRETRCOMRSTMSTSELMMUI
MMRR
0BPSEL
_P
HWBPxx
MMWR1
MRAMSTRFRRF
S_P
C
MMUIERRIE_PRRIE
E_P
BPSEL
HWB0C
F
Data Sheet50V1.2, 2009-07
XC886/888CLM
Functional Description
Table 18OCDS Register Overview (cont’d)
Addr Register NameBit76543210
EC
MMWR2Reset: 00
H
Monitor Work Register 2
Bit Field
H
Typerw
MMWR2
Data Sheet51V1.2, 2009-07
XC886/888CLM
Functional Description
3.3Flash Memory
The Flash memory provides an embedded user-programmable non-volatile memory,
allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V
supply from the Embedded Voltage Regulator (EVR) and does not require additional
programming or erasing voltage. The sectorization of the Flash memory allows each
sector to be erased independently.
Features
•In-System Programming (ISP) via UART
•In-Application Programming (IAP)
•Error Correction Code (ECC) for dynamic correction of single-bit errors
•Background program and erase operations for CPU load minimization
•Support for aborting erase operation
1)
•Minimum program width
•1-sector minimum erase width
•1-byte read access
•Flash is delivered in erased state (read all zeros)
•Operating supply voltage: 2.5 V ± 7.5 %
•Read access time: 3 ×
•Program time: 248256 / f
•Erase time: 9807360 / f
of 32-byte for D-Flash and 64-byte for P-Flash
t
CCLK
SYS
SYS
= 125 ns
= 2.6 ms
= 102 ms
2)
3)
3)
1) P-Flash: 64-byte wordline can only be programmed once, i.e., one gate disturb allowed.
D-Flash: 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed.
2) Values shown here are typical values.
frequency range for Flash read access.
3) Values shown here are typical values.
programming and erasing.
f
is used for obtaining the worst case timing.
sysmin
f
=96MHz±7.5% (f
sys
f
= 96 MHz ± 7.5% is the only frequency range for Flash
sys
= 24 MHz ± 7.5 %) is the maximum
CCLK
Data Sheet52V1.2, 2009-07
XC886/888CLM
Functional Description
Table 19 shows the Flash data retention and endurance targets.
Table 19Flash Data Retention and Endurance (Operating Conditions apply)
RetentionEndurance
1)
Program Flash
20 years1,000 cyclesup to 32 Kbytes
20 years 1,000 cyclesup to 24 Kbytes
Data Flash
20 years1,000 cycles4 Kbytes
5 years10,000 cycles1 Kbyte
2 years70,000 cycles512 bytes
2 years100,000 cycles128 bytes
1) One cycle refers to the programming of all wordlines in a sector and erasing of sector. The Flash endurance
data specified in Table 19 is valid only if the following conditions are fulfilled:
- the maximum number of erase cycles per Flash sector must not exceed 100,000 cycles.
- the maximum number of erase cycles per Flash bank must not exceed 300,000 cycles.
- the maximum number of program cycles per Flash bank must not exceed 2,500,000 cycles.
2) If no Flash is used for data, the Program Flash size can be up to the maximum Flash size available in the
device variant. Having more Data Flash will mean less Flash is available for Program Flash.
SizeRemarks
2)
2)
for 32-Kbyte Variant
for 24-Kbyte Variant
3.3.1Flash Bank Sectorization
The XC886/888 product family offers Flash devices with either 24 Kbytes or 32 Kbytes
of embedded Flash memory. Each Flash device consists of Program Flash (P-Flash)
and Data Flash (D-Flash) bank(s) with different sectorization shown in Figure 11. Both
types can be used for code and data storage. The label “Data” neither implies that the
D-Flash is mapped to the data memory region, nor that it can only be used for data
storage. It is used to distinguish the different Flash bank sectorizations.
The 32-Kbyte Flash device consists of 6 P-Flash and 2 D-Flash banks, while the 24Kbyte Flash device consists of also of 6 P-Flash banks but with the upper 2 banks only
2 Kbytes each, and only 1 D-Flash bank. The XC886/888 ROM devices offer a single 4Kbyte D-Flash bank.
The P-Flash banks are always grouped in pairs. As such, the P-Flash banks are also
sometimes referred to as P-Flash bank pair. Each sector in a P-Flash bank is grouped
with the corresponding sector from the other bank within a bank pair to form a P-Flash
bank pair sector.
The internal structure of each Flash bank represents a sector architecture for flexible
erase capability. The minimum erase width is always a complete sector, and sectors can
be erased separately or in parallel. Contrary to standard EPROMs, erased Flash
memory cells contain 0s.
The D-Flash bank is divided into more physical sectors for extended erasing and
reprogramming capability; even numbers for each sector size are provided to allow
greater flexibility and the ability to adapt to a wide range of application requirements.
3.3.2Parallel Read Access of P-Flash
To enhance system performance, the P-Flash banks are configured for parallel read to
allow two bytes of linear code to be read in 4 x CCLK cycles, compared to 6 x CCLK
cycles if serial read is performed. This is achieved by reading two bytes in parallel from
a P-Flash bank pair within the 3 x CCLK cycles access time and storing them in a cache.
Subsequent read from the cache by the CPU does not require a wait state and can be
completed within 1 x CCLK cycle. The result is the average instruction fetch time from
the P-Flash banks is reduced and thus, the MIPS (Mega Instruction Per Second) of the
system is increased.
However, if the parallel read feature is not desired due to certain timing constraints, it can
be disabled by calling the parallel read disable subroutine.
Data Sheet54V1.2, 2009-07
XC886/888CLM
Functional Description
3.3.3Flash Programming Width
For the P-Flash banks, a programmed wordline (WL) must be erased before it can be
reprogrammed as the Flash cells can only withstand one gate disturb. This means that
the entire sector containing the WL must be erased since it is impossible to erase a
single WL.
For the D-Flash bank, the same WL can be programmed twice before erasing is required
as the Flash cells are able to withstand two gate disturbs. This means if the number of
data bytes that needs to be written is smaller than the 32-byte minimum programming
width, the user can opt to program this number of data bytes (x; where x can be any
integer from 1 to 31) first and program the remaining bytes (32 - x) later. Hence, it is
possible to program the same WL, for example, with 16 bytes of data two times (see
Figure 12)
32 bytes (1 WL)
0000 ….. 0000
0000 ….. 0000
1111 ….. 0000
H
H
H
0000 ….. 0000
1111 ….. 1111
1111 ….. 1111
H
H
H
Program 1
Program 2
16 bytes16 bytes
0000 ….. 0000
1111 ….. 0000
Note: A Flash memory cell can be programmed
from 0 to 1, but not from 1 to 0.
H
H
1111 ….. 1111
0000 ….. 0000
H
H
Flash memory cells32-byte write buffers
Figure 12D-Flash Programming
Note: When programming a D-Flash WL the second time, the previously programmed
Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain
its original contents and to prevent “over-programming”.
Data Sheet55V1.2, 2009-07
XC886/888CLM
Functional Description
3.4Interrupt System
The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt
requests. In addition to the standard interrupt functions supported by the core, e.g.,
configurable interrupt priority and interrupt masking, the XC886/888 interrupt system
provides extended interrupt support capabilities such as the mapping of each interrupt
vector to several interrupt sources to increase the number of interrupt sources
supported, and additional status registers for detecting and determining the interrupt
source.
3.4.1Interrupt Source
Figure 13 to Figure 17 give a general overview of the interrupt sources and nodes, and
their corresponding control and status flags.
WDT Overflow
PLL Loss of Loc k
Flash Oper ation
Complete
VDD Pre-Warning
VDDP Pre-WarningFNMIVDDP
Flash ECC Error
FNMIWDT
NMIISR.0
FNMIPLL
NMIISR.1
FNMIFLASH
NMIISR.2
FNMIVDD
NMIISR.4
NMIISR.5
FNMIECC
NMIISR.6
NMIWDT
NMICON.0
NMIPLL
NMICON.1
NMIFLASH
NMIVDD
NMICON.4
NMIVDDP
NMICON.5
NMIECC
NMICON.6
>=1
0073
H
Non
Maskable
Interrupt
Figure 13Non-Maskable Interrupt Request Sources
Data Sheet56V1.2, 2009-07
XC886/888CLM
l
Functional Description
Highest
EINT0
Timer 0
Overfl ow
Timer 1
Overflow
UART
Receive
UART
Transmit
EXINT 0
EXICON0.0/1
RI
SCON.0
TI
SCON.1
IT0
TCON.0
TF0
TCON.5
TF1
TCON.7
>=1
IE0
TCON.1
ET0
IEN0.1
ET1
IEN0.3
ES
IEN0.4
EX0
IEN0.0
000B
001B
0023
0003
Lowest
H
IP.1/
IPH.1
H
IP.3/
IPH.3
Priority Leve
P
o
l
l
i
n
g
H
IP.4/
IPH.4
S
e
q
u
e
n
c
e
H
IP.0/
IPH.0
EINT1
IT1
TCON.2
EXIN T1
EXIC ON0.2/ 3
IE1
TCON.3
EX1
IEN0.2
0013
EA
H
IP.2/
IPH.2
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 14Interrupt Request Sources (Part 1)
Data Sheet57V1.2, 2009-07
l
Timer 2
Overflow
T2EX
EDGES
T2_T2MOD.5
End of
Sy nch B yte
Sy nch B yte
Error
EL
EOFSYN
FDCON.4
ERRSYN
FDCON.5
MultiCAN_0
EXEN2
T2_T2CON. 3
Normal Divider
Overflow
TF2
T2_T2CON. 7
EXF2
T2_T2CON. 6
>=1
>=1
NDOV
FDCON.2
SYNEN
CANS RC0
IRCON2.0
>=1
ET2
IEN0.5
002B
XC886/888CLM
Functional Description
Highest
Lowest
Priority Leve
H
IP.5/
IPH.5
P
o
l
l
i
n
g
ADC_0
ADC_1
MultiCAN_1
MultiCAN_2
ADCSR0
IRCON1.3
ADCSR1
IRCON1.4
CANS RC1
IRCON1.5
CANS RC2
IRCON1.6
>=1
EADC
IEN1.0
Bit-addressable
Request flag is cleared by hardware
Figure 15Interrupt Request Sources (Part 2)
0033
EA
IEN0.7
S
e
q
u
e
n
H
IP1.0/
IPH1.0
c
e
Data Sheet58V1.2, 2009-07
l
Timer 21
Overflow
T21EX
T21_T 2MOD.5
EDGES
EL
EINT2
UART1
SSC_EIR
SSC_TIR
SS C_RIR
T21_T 2CON.3
Cordic
MDU_0
MDU_1
EXINT 2
EXICON0.4/5
RI
UART1_S CON.0
TI
UART1_S CON.1
TF2
T21_T2CON.7
EXF2
T21_T2CON.6
EXEN2
Normal Divider
Overflow
Bit-addressable
EIR
IRCON1.0
TIR
IRCON1.1
RIR
IRCON1.2
EXINT 2
IRCON0.2
>=1
>=1
NDOV
UART1_FDCON.2
EOC
CDSTATC.2
IRDY
MDUSTAT.0
IERR
MDUSTAT.1
>=1
>=1
ESSC
IEN1.1
EX2
IEN1.2
003B
0043
EA
IEN0.7
XC886/888CLM
Functional Description
Highest
Lowest
Priority Leve
H
IP1.1/
IPH1.1
P
o
l
l
i
n
g
S
e
q
u
e
n
H
IP1.2/
IPH1.2
c
e
Request flag is cleared by hardware
Figure 16Interrupt Request Sources (Part 3)
Data Sheet59V1.2, 2009-07
EINT3
EXINT 3
EXICON0.6/ 7
EXIN T3
IRCON0.3
XC886/888CLM
Functional Description
Highest
Lowest
Priority Level
EINT4
EINT5
EINT6
MultiCAN_3
Bit-addressable
EXIN T3
EXICON1.0/1
EXIN T5
EXICON1.2/3
EXIN T6
EXICON1.4/5
EXINT 4
IRCON0.4
EXIN T5
IRCON0.5
EXIN T6
IRCON0.6
CANSRC3
IRCON2.4
>=1
EXM
IEN1.3
004B
H
EA
IEN0.7
IP1.3/
IPH1.3
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
Request flag is cleared by hardware
Figure 17Interrupt Request Sources (Part 4)
Data Sheet60V1.2, 2009-07
l
CCU6 interrupt node 0
MultiCAN_4
CCU6 interrupt node 1
MultiCA N_5
CCU6 interrupt node 2
MutliCA N_6
CCU6S R0
IRCON3.0
CANS RC4
IRCON3.1
CCU6S R1
IRCON3.4
CANSRC5
IRCON3.5
CCU6S R2
IRCON4.0
CANSRC6
IRCON4.1
>=1
>=1
>=1
ECCIP0
IEN1.4
ECCIP1
IEN1.5
ECCIP2
IEN1.6
0053
005B
0063
XC886/888CLM
Functional Description
Highest
Lowest
Priority Leve
H
IP1.4/
IPH1.4
H
IP1.5/
IPH1.5
H
IP1.6/
IPH1.6
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
CCU6 interrupt node 3
MultiCAN_7
CCU6S RC3
IRCON4.4
CANS RC7
IRCON4.5
>=1
ECCIP3
IEN1.7
Bit-addressable
Request flag is cleared by hardware
Figure 18Interrupt Request Sources (Part 5)
006B
H
EA
IEN0.7
IP1.7/
IPH1.7
Data Sheet61V1.2, 2009-07
XC886/888CLM
Functional Description
3.4.2Interrupt Source and Vector
Each interrupt event source has an associated interrupt vector address for the interrupt
node it belongs to. This vector is accessed to service the corresponding interrupt node
request. The interrupt service of each interrupt source can be individually enabled or
disabled via an enable bit. The assignment of the XC886/888 interrupt sources to the
interrupt vector address and the corresponding interrupt node enable bits are
summarized in Table 20.
An interrupt that is currently being serviced can only be interrupted by a higher-priority
interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of
the highest priority cannot be interrupted by any other interrupt request.
If two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. If requests of the same priority are
received simultaneously, then an internal polling sequence determines which request is
serviced first. Thus, within each priority level, there is a second priority structure
determined by the polling sequence shown in Table 21.
The XC886 has 34 port pins organized into five parallel ports, Port 0 (P0) to Port 4 (P4),
while the XC888 has 48 port pins organized into six parallel ports, Port 0 (P0) to Port 5
(P5). Each pin has a pair of internal pull-up and pull-down devices that can be individually
enabled or disabled. Ports P0, P1, P3, P4 and P5 are bidirectional and can be used as
general purpose input/output (GPIO) or to perform alternate input/output functions for the
on-chip peripherals. When configured as an output, the open drain mode can be
selected. Port P2 is an input-only port, providing general purpose input functions,
alternate input functions for the on-chip peripherals, and also analog inputs for the
Analog-to-Digital Converter (ADC).
Bidirectional Port Features
•Configurable pin direction
•Configurable pull-up/pull-down devices
•Configurable open drain mode
•Transfer of data through digital inputs and outputs (general purpose I/O)
•Alternate input/output for on-chip peripherals
Input Port Features
•Configurable input driver
•Configurable pull-up/pull-down devices
•Receive of data through digital input (general purpose input)
•Alternate input for on-chip peripherals
•Analog input for ADC module
Data Sheet65V1.2, 2009-07
Figure 19 shows the structure of a bidirectional port pin.
XC886/888CLM
Functional Description
Internal Bus
AltDataO ut 3
AltDataO ut 2
AltDataO ut1
Px_PUDSEL
Pull-up/Pull-down
Select Register
Px_PUDEN
Pull-up/Pull-down
Enable Register
Px_OD
Open Dr ain
Control Register
Px_DIR
Direction Register
Px_ALTSEL0
Alternate Select
Register 0
Px_ALTSEL1
Alternate Select
Register 1
Px_Data
Data Register
Out
VDDP
Pull
enable
Up
Device
11
10
01
00
In
enable
enable
Output
Driver
Pin
Input
Driver
AltDat aIn
Schmitt Trigger
enable
Pull
Down
Device
Pad
Figure 19General Structure of Bidirectional Port
Data Sheet66V1.2, 2009-07
Figure 20 shows the structure of an input-only port pin.
XC886/888CLM
Functional Description
AltDataIn
AnalogIn
Interna l Bus
Px_PUDSEL
Pul l-u p/Pul l -down
Select Register
Px_PUDEN
Pul l-u p/Pul l -down
Enable Regis ter
Px_DIR
Directi on Register
Px_DATA
Data Register
VDDP
Pull
enable
Up
enable
In
Input
Dri ve r
Schmitt Trigger
Device
Pin
Figure 20General Structure of Input Port
enable
Pull
Down
Device
Pad
Data Sheet67V1.2, 2009-07
XC886/888CLM
Functional Description
3.6Power Supply System with Embedded Voltage Regulator
The XC886/888 microcontroller requires two different levels of power supply:
•3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports
•2.5 V for the core, memory, on-chip oscillator, and peripherals
Figure 21 shows the XC886/888 power supply system. A power supply of 3.3 V or 5.0 V
must be provided from the external power supply pin. The 2.5 V power supply for the
logic is generated by the EVR. The EVR helps to reduce the power consumption of the
whole chip and the complexity of the application board design.
The EVR consists of a main voltage regulator and a low power voltage regulator. In
active mode, both voltage regulators are enabled. In power-down mode, the main
voltage regulator is switched off, while the low power voltage regulator continues to
function and provide power supply to the system with low power consumption.
CPU &
Memory
GPIO Ports
(P0-P5)
On-chip
OSC
V
EVR
DDC
(2.5V)
Peripheral
logic
V
DDP
V
SSP
Figure 21XC886/888 Power Supply System
ADC
FLASH
PLL
XTAL1&
XTAL2
(3.3V/5.0V)
EVR Features
V
•Input voltage (
•Output voltage (
): 3.3 V/5.0 V
DDP
V
): 2.5 V ± 7.5%
DDC
•Low power voltage regulator provided in power-down mode
V
•
•
Data Sheet68V1.2, 2009-07
and V
DDC
V
brownout detection
DDC
prewarning detection
DDP
XC886/888CLM
Functional Description
3.7Reset Control
The XC886/888 has five types of reset: power-on reset, hardware reset, watchdog timer
reset, power-down wake-up reset, and brownout reset.
When the XC886/888 is first powered up, the status of certain pins (see Table 23) must
be defined to ensure proper start operation of the device. At the end of a reset sequence,
the sampled values are latched to select the desired boot option, which cannot be
modified until the next power-on reset or hardware reset. This guarantees stable
conditions during the normal operation of the device.
In order to power up the system properly, the external reset pin RESET
V
until
capacitor at RESET
0.4 V, but not before
reaches 0.9*V
DDC
pin. This capacitor value must be selected so that V
V
A typical application example is shown in Figure 22. The V
V
while the
capacitor value is 220 nF. The capacitor connected to RESET pin is
DDC
. The delay of external reset can be realized by an external
DDC
reaches 0.9* V
DDC
DDC.
capacitor value is 100 nF
DDP
100 nF.
Typically, the time taken for
2.3V. Hence, based on the condition that 10% to 90%
500 µs, the RESET
V
pin should be held low for 500 µs typically. See Figure 23.
IN
V
to reach 0.9*V
DDC
3.3 / 5V
is less than 50 µs once V
DDC
V
(slew rate) is less than
DDP
VR
100nF
220nF
must be asserted
reaches
RESET
reaches
DDP
typ.
V
SSP
RESET
V
DDP
V
DDC
V
SSC
100nF
EVR
30k
XC886/888
Figure 22Reset Circuitry
Data Sheet69V1.2, 2009-07
h
Voltage
XC886/888CLM
Functional Description
5V
2.5V
2.3V
0.9*V
DDC
Voltage
5V
< 0.4V
0V
Figure 23V
typ. < 50 µs
DDP, VDDC
and V
during Power-on Reset
RESET
V
DDP
V
DDC
Time
RESET wit
capacitor
Time
The second type of reset in XC886/888 is the hardware reset. This reset function can be
used during normal operation or when the chip is in power-down mode. A reset input pin
RESET
is provided for the hardware reset.
The Watchdog Timer (WDT) module is also capable of resetting the device if it detects
a malfunction in the system.
Another type of reset that needs to be detected is a reset while the device is in
power-down mode (wake-up reset). While the contents of the static RAM are undefined
after a power-on reset, they are well defined after a wake-up reset from power-down
mode.
Data Sheet70V1.2, 2009-07
XC886/888CLM
Functional Description
3.7.1Module Reset Behavior
Table 22 lists the functions of the XC886/888 and the various reset types that affect
these functions. The symbol “■” signifies that the particular function is reset to its default
state.
Table 22Effect of Reset on Device Functions
Module/
Function
Wake-Up
Reset
Watchdog
Reset
Hardware
Reset
Power-On
Reset
Brownout
Reset
CPU Core■■■■■
Peripherals■■■■■
On-Chip
Static RAM
Oscillator,
Not affected,
Reliable
Not affected,
Reliable
Not affected,
Reliable
Affected, unreliable
Affected, unreliable
■Not affected■■■
PLL
Port Pins■■■■■
EVRThe voltage
Not affected■■■
regulator is
switched on
FLASH■■■■■
NMIDisabledDisabled■■■
3.7.2Booting Scheme
When the XC886/888 is reset, it must identify the type of configuration with which to start
the different modes once the reset sequence is complete. Thus, boot configuration
information that is required for activation of special modes and conditions needs to be
applied by the external world through input pins. After power-on reset or hardware reset,
the pins MBC, TMS and P0.0 collectively select the different boot options. Table 23
shows the available boot options in the XC886/888.
Table 23XC886/888 Boot Selection
MBCTMSP0.0Type of ModePC Start Value
10XUser Mode
00XBSL Mode; on-chip OSC/PLL non-bypassed2)0000
010OCDS Mode; on-chip OSC/PLL non-
1)
; on-chip OSC/PLL non-bypassed 0000
0000
H
H
H
bypassed
110User (JTAG) Mode3); on-chip OSC/PLL non-
0000
H
bypassed (normal)
Data Sheet71V1.2, 2009-07
XC886/888CLM
Functional Description
1) BSL mode is automatically entered if no valid password is installed and data at memory address 0000H equals
zero.
2) OSC is bypassed in MultiCAN BSL mode
3) Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose.
Note: The boot options are valid only with the default set of UART and JTAG pins.
3.8Clock Generation Unit
The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the
XC886/888. The power consumption is indirectly proportional to the frequency, whereas
the performance of the microcontroller is directly proportional to the frequency. During
user program execution, the frequency can be programmed for an optimal ratio between
performance and power consumption. Therefore the power consumption can be
adapted to the actual application state.
Features
•Phase-Locked Loop (PLL) for multiplying clock source by different factors
•PLL Base Mode
•Prescaler Mode
•PLL Mode
•Power-down mode support
The CGU consists of an oscillator circuit and a PLL. In the XC886/888, the oscillator can
be from either of these two sources: the on-chip oscillator (9.6 MHz) or the external
oscillator (4 MHz to 12 MHz). The term “oscillator” is used to refer to both on-chip
oscillator and external oscillator, unless otherwise stated. After the reset, the on-chip
oscillator will be used by default.The external oscillator can be selected via software. In
addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock
detection. This allows emergency routines to be executed for system recovery or to
perform system shut down.
Data Sheet72V1.2, 2009-07
XC886/888CLM
Functional Description
OSC
fosc
P:1
OSCDISC
fp
fn
osc fail
detect
lock
detect
PLL
core
N:1
NDIV
fvco
VCOBYP
K:1
fsys
PLLBYP
OSCR
LOCK
Figure 24CGU Block Diagram
PLL Base Mode
When the oscillator is disconnected from the PLL, the system clock is derived from the
VCO base (free running) frequency clock (Table 25) divided by the K factor.
1
f
SYSfVCObase
----
×=
K
(3.1)
Prescaler Mode (VCO Bypass Operation)
In VCO bypass operation, the system clock is derived from the oscillator clock, divided
by the P and K factors.
1
-------------
f
SYSfOSC
×=
PK×
(3.2)
Data Sheet73V1.2, 2009-07
XC886/888CLM
Functional Description
PLL Mode
The system clock is derived from the oscillator clock, multiplied by the N factor, and
divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for
this PLL mode. The PLL mode is used during normal system operation.
N
-------------
f
SYSfOSC
System Frequency Selection
For the XC886/888, the value of P is fixed to 1. In order to obtain the required fsys, the
value of N and K can be selected by bits NDIV and KDIV respectively for different
oscillator inputs. The output frequency must always be configured for 96 MHz. Table 24
f
provides examples on how
= 96 MHz can be obtained for the different oscillator
sys
sources.
×=
PK×
(3.3)
Table 24System frequency (
f
=96MHz)
sys
OscillatorFoscNPKFsys
On-chip9.6 MHz201296 MHz
External8 MHz241296 MHz
6 MHz321296 MHz
4 MHz481296 MHz
Data Sheet74V1.2, 2009-07
Table 25 shows the VCO range for the XC886/888.
Table 25VCO Range
XC886/888CLM
Functional Description
f
VCOmin
f
VCOmax
f
VCOFREEmin
f
VCOFREEmax
Unit
1502002080MHz
1001501080MHz
3.8.1Recommended External Oscillator Circuits
The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal
oscillator or an external stable clock source. It basically consists of an inverting amplifier
and a feedback element with XTAL1 as input, and XTAL2 as output.
When using a crystal, a proper external oscillator circuitry must be connected to both
pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 4 MHz
C
to 12 MHz. Additionally, it is necessary to have two load capacitances
R
depending on the crystal type, a series resistor
, to limit the current. A test resistor R
X2
may be temporarily inserted to measure the oscillation allowance (negative resistance)
R
of the oscillator circuitry.
values are typically specified by the crystal vendor. The C
Q
and CX2 values shown in Figure 25 can be used as starting points for the negative
resistance evaluation and for non-productive systems. The exact values and related
operating range are dependent on the crystal frequency and have to be determined and
optimized together with the crystal vendor using the negative resistance method.
Oscillation measurement with the final target system is strongly recommended to verify
the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin
negative resistance) for the oscillator-crystal system.
and CX2, and
X1
X1
Q
When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is
left open (unconnected).
The oscillator can also be used in combination with a ceramic resonator. The final
circuitry must also be verified by the resonator vendor. Figure 25 shows the
recommended external oscillator circuitries for both operating modes, external crystal
mode and external input clock mode.
Data Sheet75V1.2, 2009-07
XC886/888CLM
Functional Description
XTAL1
4 - 12
MHz
R
Q
R
X2
XC886/888
Oscillator
XTAL2
C
X1
Fundamental
Mode Crystal
Crystal Frequency CX1, C
4 MHz
8 MHz
10 MHz
12 MHz
1) Not e t hat t hese are evaluat ion st ar t values!
C
X2
V
SS
1)
X2
33 pF
18 pF
15 pF
12 pF
f
OS C
External Clock
Signal
XTAL1
XC886/888
Oscilla tor
XTAL2
V
SS
1)
R
X2
0
0
0
0
Clock_EXOSC
f
OS C
Figure 25External Oscillator Circuitry
Note: For crystal operation, it is strongly recommended to measure the negative
resistance in the final target system (layout) to determine the optimum parameters
for the oscillator operation. Please refer to the minimum and maximum values of
the negative resistance specified by the crystal supplier.
Data Sheet76V1.2, 2009-07
XC886/888CLM
Functional Description
3.8.2Clock Management
The CGU generates all clock signals required within the microcontroller from a single
f
clock,
modules are as follow:
•CPU clock: CCLK, SCLK = 24 MHz
•Fast clock (used by MultiCAN): FCLK = 24 or 48 MHz
In addition, different clock frequencies can be output to pin CLKOUT (P0.0 or P0.7). The
clock output frequency, which is derived from the clock output divider (bit COREL), can
further be divided by 2 using toggle latch (bit TLEN is set to 1). The resulting output
frequency has a 50% duty cycle. Figure 26 shows the clock distribution of the
XC886/888.
. During normal system operation, the typical frequencies of the different
sys
OSC
fosc
PLL
N,P,K
fsys=
96MHz
SD
CLKREL
1
0
FCCFG
FCLK
PCLK
SCLK
/2
/2
COREL
TLEN
Toggle
Latch
CCLK
CCLK2
MultiCAN
Pe rip h e rals
CORE
FLASH
Interface
CLK OUT
COUTS
Figure 26Clock Generation from
f
sys
Data Sheet77V1.2, 2009-07
XC886/888CLM
Functional Description
For power saving purposes, the clocks may be disabled or slowed down according to
Table 26.
Table 26System frequency (
f
=96MHz)
sys
Power Saving ModeAction
IdleClock to the CPU is disabled.
Slow-downClocks to the CPU and all the peripherals are divided by a
common programmable factor defined by bit field
CMCON.CLKREL.
Power-downOscillator and PLL are switched off.
Data Sheet78V1.2, 2009-07
XC886/888CLM
Functional Description
3.9Power Saving Modes
The power saving modes of the XC886/888 provide flexible power consumption through
a combination of techniques, including:
•Stopping the CPU clock
•Stopping the clocks of individual system components
•Reducing clock speed of some peripheral components
•Power-down of the entire system with fast restart capability
After a reset, the active mode (normal operating mode) is selected by default (see
Figure 27) and the system runs in the main system clock frequency. From active mode,
different power saving modes can be selected by software. They are:
•Idle mode
•Slow-down mode
•Power-down mode
any interrupt
& SD=0
set IDLE
bit
IDLE
set IDLE
bit
any interrupt
& SD=1
ACTIVE
set SD
bit
SLOW-DOWN
clear SD
bit
Figure 27 Transition between Power Saving Modes
EXINT0/RXD pin
& SD=0
set PD
bit
POWER- DOWN
set PD
bit
EXINT0/RXD pin
& SD=1
Data Sheet79V1.2, 2009-07
XC886/888CLM
Functional Description
3.10Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failures. The WDT is reset at a regular interval that is
predefined by the user. The CPU must service the WDT within this interval to prevent the
WDT from causing an XC886/888 system reset. Hence, routine service of the WDT
confirms that the system is functioning properly. This ensures that an accidental
malfunction of the XC886/888 will be aborted in a user-specified time period.
In debug mode, the WDT is default suspended and stops counting. Therefore, there is
no need to refresh the WDT during debugging.
Features
•16-bit Watchdog Timer
•Programmable reload value for upper 8 bits of timer
•Programmable window boundary
f
•Selectable input frequency of
PCLK
/2 or f
•Time-out detection with NMI generation and reset prewarning activation (after which
a system reset will be performed)
PCLK
/128
The WDT is a 16-bit timer incremented by a count rate of f
PCLK
/2 or f
/128. This 16-bit
PCLK
timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be
preset to a user-programmable value via a watchdog service access in order to modify
the watchdog expire time period. The lower 8 bits are reset on each service access.
Figure 28 shows the block diagram of the WDT unit.
ENW DT
ENW DT_P
f
PCLK
Logic
1:2
1:128
MUX
WDTIN
WDT
Cont rol
Clear
WDT Low Byte
Overflow/Time-out Control &
Window -boundary cont rol
WDTREL
WDT High Byte
WDTWI NB
FNMIWDT
WDTRST
.
Figure 28WDT Block Diagram
Data Sheet80V1.2, 2009-07
XC886/888CLM
Functional Description
If the WDT is not serviced before the timer overflow, a system malfunction is assumed.
As a result, the WDT NMI is triggered (assert FNMIWDT) and the reset prewarning is
entered. The prewarning period lasts for 30
(assert WDTRST).
The WDT has a “programmable window boundary” which disallows any refresh during
the WDT’s count-up. A refresh during this window boundary constitutes an invalid
access to the WDT, causing the reset prewarning to be entered but without triggering the
WDT NMI. The system will still be reset after the prewarning period is over. The window
boundary is from 0000
.
00
H
to the value obtained from the concatenation of WDTWINB and
H
After being serviced, the WDT continues counting up from the value (<WDTREL> * 2
The time period for an overflow of the WDT is programmable in two ways:
count, after which the system is reset
H
8
).
•The input frequency to the WDT can be selected to be either
f
PCLK
/2 or f
PCLK
/128
•The reload value WDTREL for the high byte of WDT can be programmed in register
WDTREL
The period, P
, between servicing the WDT and the next overflow can be determined
If the Window-Boundary Refresh feature of the WDT is enabled, the period
P
WDT
between servicing the WDT and the next overflow is shortened if WDTWINB is greater
than WDTREL, see Figure 29. This period can be calculated using the same formula by
replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB cannot be
smaller than WDTREL.
Data Sheet81V1.2, 2009-07
Count
FFFF
H
WDTWINB
WDTREL
No refresh
allowed
Figure 29WDT Timing Diagram
XC886/888CLM
Functional Description
time
Refresh allowed
Table 27 lists the possible watchdog time ranges that can be achieved using a certain
module clock. Some numbers are rounded to 3 significant digits.
Table 27Watchdog Time Ranges
Reload value
In WDTREL
Prescaler for
2 (WDTIN = 0)128 (WDTIN = 1)
f
PCLK
24 MHz24 MHz
FF
7F
00
H
H
H
21.3 µs1.37 ms
2.75 ms176 ms
5.46 ms350 ms
Data Sheet82V1.2, 2009-07
XC886/888CLM
Functional Description
3.11Multiplication/Division Unit
The Multiplication/Division Unit (MDU) provides fast 16-bit multiplication, 16-bit and
32-bit division as well as shift and normalize features. It has been integrated to support
the XC886/888 Core in real-time control applications, which require fast mathematical
computations.
Features
•Fast signed/unsigned 16-bit multiplication
•Fast signed/unsigned 32-bit divide by 16-bit and 16-bit divide by 16-bit operations
•32-bit unsigned normalize operation
•32-bit arithmetic/logical shift operations
Table 28 specifies the number of clock cycles used for calculation in various operations.
Table 28MDU Operation Characteristics
OperationResultRemainderNo. of Clock Cycles
used for calculation
Signed 32-bit/16-bit32-bit16-bit33
Signed 16-bit/16bit16-bit16-bit17
Signed 16-bit x 16-bit32-bit-16
Unsigned 32-bit/16-bit32-bit16-bit32
Unsigned 16-bit/16-bit16-bit16-bit16
Unsigned 16-bit x 16-bit32-bit-16
32-bit normalize--No. of shifts + 1 (Max. 32)
32-bit shift L/R--No. of shifts + 1 (Max. 32)
Data Sheet83V1.2, 2009-07
XC886/888CLM
Functional Description
3.12CORDIC Coprocessor
The CORDIC Coprocessor provides CPU with hardware support for the solving of
circular (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions.
Features
•Modes of operation
– Supports all CORDIC operating modes for solving circular (trigonometric), linear
(multiply-add, divide-add) and hyperbolic functions
– Integrated look-up tables (LUTs) for all operating modes
•Circular vectoring mode: Extended support for values of initial X and Y data up to full
15
range of [-2
•Circular rotation mode: Extended support for values of initial Z data up to full range
15
of [-2
,(215-1)], representing angles in the range [-π,((215-1)/215)π] for solving
trigonometry
•Implementation-dependent operational frequency of up to 80 MHz
•Gated clock input to support disabling of module
•16-bit accessible data width
– 24-bit kernel data width plus 2 overflow bits for X and Y each
– 20-bit kernel data width plus 1 overflow bit for Z
– With KEEP bit to retain the last value in the kernel register for a new calculation
•16 iterations per calculation: Approximately 41 clock-cycles or less, from set of start
(ST) bit to set of end-of-calculation flag, excluding time taken for write and read
access of data bytes.
•Twos complement data processing
– Only exception: X result data with user selectable option for unsigned result
•X and Y data generally accepted as integer or rational number; X and Y must be of
the same data form
•Entries of LUTs are 20-bit signed integers
– Entries of atan and atanh LUTs are integer representations (S19) of angles with
the scaling such that [-2
– Accessible Z result data for circular and hyperbolic functions is integer in data form
of S15
•Emulated LUT for linear function
– Data form is 1 integer bit and 15-bit fractional part (1.15)
– Accessible Z result data for linear function is rational number with fixed data form
of S4.11 (signed 4Q16)
•Truncation Error
– The result of a CORDIC calculation may return an approximation due to truncation
of LSBs
– Good accuracy of the CORDIC calculated result data, especially in circular mode
•Interrupt
– On completion of a calculation
,(215-1)] for solving angle and magnitude
15
,(215-1)] represents the range [-π,((215-1)/215)π]
Data Sheet84V1.2, 2009-07
XC886/888CLM
Functional Description
– Interrupt enabling and corresponding flag
3.13UART and UART1
The XC886/888 provides two Universal Asynchronous Receiver/Transmitter (UART and
UART1) modules for full-duplex asynchronous reception/transmission. Both are also
receive-buffered, i.e., they can commence reception of a second byte before a
previously received byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second byte is complete, one of
the bytes will be lost.
Features
•Full-duplex asynchronous modes
– 8-bit or 9-bit data frames, LSB first
– Fixed or variable baud rate
•Receive buffered
•Multiprocessor communication
•Interrupt generation on the completion of a data transmission or reception
The UART modules can operate in the four modes shown in Table 29.
Table 29UART Modes
Operating ModeBaud Rate
f
Mode 0: 8-bit shift register
PCLK
/2
Mode 1: 8-bit shift UARTVariable
Mode 2: 9-bit shift UART
f
PCLK
/32 or f
PCLK
/64
1)
Mode 3: 9-bit shift UARTVariable
1) For UART1 module, the baud rate is fixed at f
PCLK
/64.
There are several ways to generate the baud rate clock for the serial port, depending on
the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at
f
/2. In mode 2, the baud rate is generated internally based on the UART input clock
PCLK
f
and can be configured to either
PCLK
/32 or f
/64. For UART1 module, only f
PCLK
PCLK
/64 is
available. The variable baud rate is set by the underflow rate on the dedicated baud-rate
generator. For UART module, the variable baud rate alternatively can be set by the
overflow rate on Timer 1.
3.13.1Baud-Rate Generator
Both UART modules have their own dedicated baud-rate generator, which is based on
a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and
Data Sheet85V1.2, 2009-07
XC886/888CLM
Functional Description
fractional divider) for generating a wide range of baud rates based on its input clock f
see Figure 30.
Fract ional Divider
8-Bit Reload Value
f
8-Bit Baud Rate Ti mer
NDOV
f
PCL K
Prescaler
FDM
FDEN
FDSTEP
1
f
DIV
0
(overflow)
‘0’
FDEN&F DM
00
01
11
10
11
10
01
00
0
1
R
01
Adder
FDRES
f
DIV
clk
f
MOD
BR
PCLK
,
Figure 30Baud-rate Generator Circuitry
The baud rate timer is a count-down timer and is clocked by either the output of the
f
fractional divider (
output of the prescaler (
) if the fractional divider is enabled (FDCON.FDEN = 1), or the
MOD
f
) if the fractional divider is disabled (FDEN = 0). For baud rate
DIV
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See Section 3.14.
f
The baud rate (
•Input clock
•Prescaling factor (2
) value is dependent on the following parameters:
BR
f
PCLK
BRPRE
) defined by bit field BRPRE in register BCON
•Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional
divider mode)
•8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG
Data Sheet86V1.2, 2009-07
XC886/888CLM
Functional Description
The following formulas calculate the final baud rate without and with the fractional divider
respectively:
The maximum baud rate that can be generated is limited to
/32. Hence, for a module
PCLK
clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud.
Standard LIN protocol can support a maximum baud rate of 20 kHz, the baud rate
accuracy is not critical and the fractional divider can be disabled. Only the prescaler is
used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of
20 kHz to 115.2 kHz, the higher baud rates require the use of the fractional divider for
greater accuracy.
Table 30 lists the various commonly used baud rates with their corresponding parameter
settings and deviation errors. The fractional divider is disabled and a module clock of
24 MHz is used.
Table 30Typical Baud rates for UART with Fractional Divider disabled
Baud ratePrescaling Factor
(2BRPRE)
19.2 kBaud1 (BRPRE=000
9600 Baud1 (BRPRE=000
4800 Baud2 (BRPRE=001
2400 Baud4 (BRPRE=010
) 78 (4E
B
)156 (9CH)0.17%
B
)156 (9CH)0.17%
B
)156 (9CH)0.17%
B
Reload Value
(BR_VALUE + 1)
)0.17%
H
Deviation Error
The fractional divider allows baud rates of higher accuracy (lower deviation error) to be
generated. Table 31 lists the resulting deviation errors from generating a baud rate of
115.2 kHz, using different module clock frequencies. The fractional divider is enabled
(fractional divider mode) and the corresponding parameter settings are shown.
Data Sheet87V1.2, 2009-07
XC886/888CLM
Functional Description
Table 31Deviation Error for UART with Fractional Divider enabled
f
PCLK
24 MHz110 (A
12 MHz16 (6
8MHz14 (4
6MHz13 (3
Prescaling Factor
(2BRPRE)
Reload Value
STEPDeviation
(BR_VALUE + 1)
)197 (C5H)+0.20 %
H
)236 (ECH)+0.03 %
H
)236 (ECH)+0.03 %
H
)236 (ECH)+0.03 %
H
Error
3.13.2Baud Rate Generation using Timer 1
In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the
variable baud rates. In theory, this timer could be used in any of its modes. But in
practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set
to the appropriate value for the required baud rate. The baud rate is determined by the
Timer 1 overflow rate and the value of SMOD as follows:
Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider
mode, while at the same time disables baud rate generation (see Figure 30). Once the
fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with
no relation to baud rate generation) and counts up from the reload value with each input
clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit
field STEP in register FDSTEP defines the reload value. At each timer overflow, an
overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives
an output clock f
that is 1/n of the input clock f
MOD
The output frequency in normal divider mode is derived as follows:
f
MODfDIV
×=
, where n is defined by 256 - STEP.
DIV
1
-----------------------------256 ST E P–
(3.8)
Data Sheet88V1.2, 2009-07
XC886/888CLM
Functional Description
3.15LIN Protocol
The UART module can be used to support the Local Interconnect Network (LIN) protocol
for both master and slave operations. The LIN baud rate detection feature, which
consists of the hardware logic for Break and Synch Byte detection, provides the
capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART
to be synchronized to the LIN baud rate for data transmission and reception.
Note: The LIN baud rate detection feature is available for use only with UART. To use
UART1 for LIN communication, software has to be implemented to detect the
Break and Synch Byte.
LIN is a holistic communication concept for local interconnected networks in vehicles.
The communication is based on the SCI (UART) data format, a single-master/multipleslave concept, a clock synchronization for nodes without stabilized time base. An
attractive feature of LIN is self-synchronization of the slave nodes without a crystal or
ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the
baud rate must be calculated and returned with every message frame.
The structure of a LIN frame is shown in Figure 31. The frame consists of the:
•Header, which comprises a Break (13-bit time low), Synch Byte (55
), and ID field
H
•Response time
•Data bytes (according to UART protocol)
•Checksum
Frame slot
Frame
Response
Header
Synch
Protected
identifier
space
Da ta 1
Response
Da ta 2Data N
Checksum
Figure 31Structure of LIN Frame
3.15.1LIN Header Transmission
LIN header transmission is only applicable in master mode. In the LIN communication,
a master task decides when and which frame is to be transferred on the bus. It also
identifies a slave task to provide the data transported by each frame. The information
Data Sheet89V1.2, 2009-07
XC886/888CLM
Functional Description
needed for the handshaking between the master and slave tasks is provided by the
master task through the header portion of the frame.
The header consists of a break and synch pattern followed by an identifier. Among these
three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data.
The break must contain a dominant value of 13 bits or more to ensure proper
synchronization of slave nodes.
In the LIN communication, a slave task is required to be synchronized at the beginning
of the protected identifier field of frame. For this purpose, every frame starts with a
sequence consisting of a break field followed by a synch byte field. This sequence is
unique and provides enough information for any slave task to detect the beginning of a
new frame and be synchronized at the start of the identifier field.
Upon entering LIN communication, a connection is established and the transfer speed
(baud rate) of the serial communication partner (host) is automatically synchronized in
the following steps:
STEP 1: Initialize interface for reception and timer for baud rate measurement
STEP 2: Wait for an incoming LIN frame from host
STEP 3: Synchronize the baud rate to the host
STEP 4: Enter for Master Request Frame or for Slave Response Frame
Note: Re-synchronization and setup of baud rate are always done for every Master
Request Header or Slave Response Header LIN frame.
Data Sheet90V1.2, 2009-07
XC886/888CLM
Functional Description
3.16High-Speed Synchronous Serial Interface
The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and
half-duplex synchronous communication. The serial clock signal can be generated by
the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be
received from an external master (slave mode). Data width, shift direction, clock polarity
and phase are programmable. This allows communication with SPI-compatible devices
or devices using other synchronous serial interfaces.
Features
•Master and slave mode operation
– Full-duplex or half-duplex operation
•Transmit and receive buffered
•Flexible data format
– Programmable number of data bits: 2 to 8 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
•Variable baud rate
•Compatible with Serial Peripheral Interface (SPI)
•Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
Data is transmitted or received on lines TXD and RXD, which are normally connected to
the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave
Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input
via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin
SCLK. Transmission and reception of data are double-buffered.
Figure 32 shows the block diagram of the SSC.
Data Sheet91V1.2, 2009-07
XC886/888CLM
Functional Description
PCLK
Baud-rate
Generator
Transmit Buffer
Register TB
Clock
Control
Shift
Clock
SSC Control Block
Register CON
ControlStatus
16-Bit Shift
Register
Receive Buffer
Internal B us
RIR
TIR
EIR
Control
Register RB
SS_CLK
MS_CLK
Re ceive In t. Request
Transmit Int. Request
Error Int. Request
TXD(Master)
RXD(Slave)
Pin
TXD(Slave)
RXD(Master)
Figure 32SSC Block Diagram
Data Sheet92V1.2, 2009-07
XC886/888CLM
Functional Description
3.17Timer 0 and Timer 1
Timer 0 and Timer 1 can function as both timers or counters. When functioning as a
timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input
clocks (or 2 PCLKs). When functioning as a counter, Timer 0 and Timer 1 are
incremented in response to a 1-to-0 transition (falling edge) at their respective external
input pins, T0 or T1.
Timer 0 and 1 are fully compatible and can be configured in four different operating
modes for use in a variety of applications, see Table 32. In modes 0, 1 and 2, the two
timers operate independently, but in mode 3, their functions are specialized.
Table 32Timer 0 and Timer 1 Modes
ModeOperation
013-bit timer
The timer is essentially an 8-bit counter with a divide-by-32 prescaler.
This mode is included solely for compatibility with Intel 8048 devices.
116-bit timer
The timer registers, TLx and THx, are concatenated to form a 16-bit
counter.
28-bit timer with auto-reload
The timer register TLx is reloaded with a user-defined 8-bit value in THx
upon overflow.
3Timer 0 operates as two 8-bit timers
The timer registers, TL0 and TH0, operate as two separate 8-bit counters.
Timer 1 is halted and retains its count even if enabled.
Data Sheet93V1.2, 2009-07
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