INFINEON XC866 User Manual

Data Sheet, V1.1, Dec. 2006

XC866

8-Bit Single-Chip Microcontroller

Microcontrollers

Edition 2006-12

Published by Infineon Technologies AG, 81726 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics.

Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, V1.1, Dec. 2006

XC866

8-Bit Single-Chip Microcontroller

Microcontrollers

XC866 Data Sheet Revision History: 2006-12 V1.1

Previous Version: V 0.1, 2005-01 V1.0, 2006-02

Page Subjects (major changes since last revision)

3 Table 2 is updated for variant devices.

38 Table 16 is updated for Flash data retention and endurance targets.

58 Section 3.8.1 is updated for the recommended external oscillator circuitry.

93 The ADC INL, DNL, GAIN and OFFSET are added.

103 Table 43 is updated for on-chip oscillator characteristics.

104 TCK clock rise time, TCK clock fall time, TDO valid output from TCK and

TDO high impedance to valid output from TCK are updated.

107 Table 47 is added for thermal characteristics of the package.

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XC8668-Bit Single-Chip Microcontroller

XC800 Family

1 Summary of Features

• High-performance XC800 Core – compatible with standard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers

• On-chip memory – 8 Kbytes of Boot ROM – 256 bytes of RAM – 512 bytes of XRAM – 4/8/16 Kbytes of Flash; or

8/16 Kbytes of ROM, with additional 4 Kbytes of Flash (includes memory protection strategy)

• I/O port supply at 3.3 V/5.0 V and core logic supply at 2.5 V (generated by embedded voltage regulator)

(further features are on next page)

4K/ 8K /16K B ytes F lash or 8K/16K By tes RO M

Boot ROM

8K B ytes

XRAM

512 By tes

RAM

256 By tes

Timer 0

16-bi t

On-C hip D ebug S upport

XC800 Core

Timer 1

16-bi t

UART

Capture/Com pare Unit

Timer 2

Watchdog

16-bi t

Timer

1) Al l RO M dev ic es i nclude 4K bytes F las h

16-bit

Com pare Uni t

16-bit

8-ch annel

SSC

ADC

10-bit

Port 0

Port 1

Port 2

Port 3

6-bit Di gital I/O

5-bit Di gital I/O

8-bit Di gital /Analog Input

8-bit Di gital I/O

Figure 1 XC866 Functional Units

Data Sheet 1 V1.1, 2006-12

Features (continued):

• Reset generation – Power-On reset – Hardware reset – Brownout reset for core logic supply – Watchdog timer reset – Power-Down Wake-up reset

• On-chip OSC and PLL for clock generation – PLL loss-of-lock detection

• Power saving modes – slow-down mode – idle mode – power-down mode with wake-up capability via RXD or EXINT0 – clock gating control to each peripheral

• Programmable 16-bit Watchdog Timer (WDT)

• Four ports – 19 pins as digital I/O – 8 pins as digital/analog input

• 8-channel, 10-bit ADC

• Three 16-bit timers – Timer 0 and Timer 1 (T0 and T1) –Timer 2

• Capture/compare unit for PWM signal generation (CCU6)

• Full-duplex serial interface (UART)

• Synchronous serial channel (SSC)

• On-chip debug support – 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM) – 64 bytes of monitor RAM

• PG-TSSOP-38 pin package

• Temperature range T

– SAF (-40 to 85 °C) – SAK (-40 to 125 °C)

XC866

Summary of Features

Data Sheet 2 V1.1, 2006-12

XC866

Summary of Features

XC866 Variant Devices

The XC866 product family features devices with different configurations and program memory sizes, temperature and quality profiles (Automotive or Industrial), offering costeffective solution for different application requirements.

The configuration of LIN BSL for XC866 devices are summarized in Table 1.

Table 1 Device Configuration for LIN BSL

Device Name LIN BSL Support

XC866 No

XC866L Yes

The list of XC866 devices and their differences are summarized in Table 2.

Table 2 Device Summary

Device Type

Flash2)SAK-XC866*-4FRA 5.0 12 4 – Automotive

Device Name Power

Supply (V)

P-Flash Size (Kbytes)

D-Flash Size (Kbytes)

ROM Size (Kbytes)

Quality Profile

SAK-XC866*-4FRI 5.0 12 4 – Industrial

SAK-XC866*-2FRA 5.0 4 4 – Automotive

SAK-XC866*-2FRI 5.0 4 4 – Industrial

SAK-XC866*-1FRA 5.0/3.3 – 4 – Automotive

SAK-XC866*-1FRI 5.0/3.3 – 4 – Industrial

SAF-XC866*-4FRA 5.0 12 4 – Automotive

SAF-XC866*-4FRI 5.0 12 4 – Industrial

SAF-XC866*-2FRA 5.0 4 4 – Automotive

SAF-XC866*-2FRI 5.0 4 4 – Industrial

SAF-XC866*-1FRA 5.0/3.3 – 4 – Automotive

SAF-XC866*-1FRI 5.0/3.3 – 4 – Industrial

SAK-XC866*-4FRA 3V 3.3 12 4 – Automotive

SAK-XC866*-4FRI 3V 3.3 12 4 – Industrial

SAK-XC866*-2FRA 3V 3.3 4 4 – Automotive

SAK-XC866*-2FRI 3V 3.3 4 4 – Industrial

SAF-XC866*-4FRA 3V 3.3 12 4 – Automotive

Data Sheet 3 V1.1, 2006-12

XC866

Summary of Features

Table 2 Device Summary

SAF-XC866*-4FRI 3V 3.3 12 4 – Industrial

SAF-XC866*-2FRA 3V 3.3 4 4 – Automotive

SAF-XC866*-2FRI 3V 3.3 4 4 – Industrial

ROM SAK-XC866*-4RRA 5.0/3.3 – 4 16 Automotive

SAK-XC866*-4RRI 5.0/3.3 – 4 16 Industrial

SAK-XC866*-2RRA 5.0/3.3 – 4 8 Automotive

SAK-XC866*-2RRI 5.0/3.3 – 4 8 Industrial

SAF-XC866*-4RRA 5.0/3.3 – 4 16 Automotive

SAF-XC866*-4RRI 5.0/3.3 – 4 16 Industrial

SAF-XC866*-2RRA 5.0/3.3 – 4 8 Automotive

SAF-XC866*-2RRI 5.0/3.3 – 4 8 Industrial

Industrial is not for Automotive usage

The flash memory (P-Flash and D-Flash) can be used for code or data.

Note: The asterisk (*) above denotes the device configuration letters from Table 1.

Ordering Information

The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery

For the available ordering codes for the XC866, please refer to your responsible sales representative or your local distributor.

As this document refers to all the derivatives, some descriptions may not apply to a specific product. For simplicity all versions are referred to by the term XC866 throughout this document.

Data Sheet 4 V1.1, 2006-12

2 General Device Information

2.1 Block Diagram

XC866

Internal Bus

XC800 Core

T0 & T1 UART

CCU6

SSC

Timer 2

WDT

OCDS

TMS MBC

RESET

DDP

SSP

DDC

SSC

XTAL1 XTAL2

8-Kbyt e

Boot R OM

256-byte RAM

64-byte monitor

RAM

512-byte X RAM

4/8/16-Kbyt e Flas h

8/16-Kby te R OM

Cloc k Generator

10 MHz

On-chip OSC

PLL

XC866

General Device Information

Port 0Port 1Port 2Port 3

ADC

P0.0 - P0.5

P1.0 - P1.1 P1.5-P1.7

P2.0 - P2.7

AREF

AGND

P3.0 - P3.7

1) Includes 1-Kby te monitor ROM

2) Includes additional 4-Kbyt e Flas h

Figure 2 XC866 Block Diagram

Data Sheet 5 V1.1, 2006-12

2.2 Logic Symbol

XC866

General Device Information

AREF

AGND

RESET

MBC

TMS

XTAL1

XTAL2

Figure 3 XC866 Logic Symbol

DDP

DDC

XC866

SSP

Port 0 6-Bit

Port 1 5-Bit

Port 2 8-Bit

Port 3 8-Bit

SSC

Data Sheet 6 V1.1, 2006-12

2.3 Pin Configuration

XC866

General Device Information

MBC

P0.3/SCLK_1/COUT63_1

P0.4/MTSR_1/CC62_1

P0.5/MR ST _1/EXINT 0_0 /COUT62_1

XTAL2

XTAL1

SSC

DDC

P1.6/C CP OS1_1/T12HR_0 /EXINT6

P1.7/CCPOS2_1/T13HR_0

TMS

P0.0/TCK_0/T12HR_1/CC 61_1/CLKOUT/RXDO_1

P0.2/CTRAP_2/TDO_0/TXD_1

P0.1/TDI_0/T13HR_1/RXD_1/EXF2_1/COUT61_1

P2.0/CCPOS0_0/EXINT1/T12HR_2/TCK_1/CC61_3/AN0

P2.1/CCPOS1_0/EXINT2/T13HR_2/TDI_1/CC62_3/AN1

P2.2/CCPOS2_0/CTRAP_1/CC60_3/AN2

DDP

SSP

XC866

RESET

P3.5 /COUT6 2_0

P3.4 /CC62_0

P3.3 /COUT6 1_0

P3.2/CCPOS2_2/CC61_0

P3.1/CCPOS0_2/CC61_2/COUT60_0

P3.0/CCPOS1_2/CC60_0

P3.7/EXINT4/COUT63_0

P3.6 /CTRA P_ 0

P1.5/CCPOS0_1/EXINT5/EXF2_0/RXDO_0

P1.1/EXINT3/TDO_1/TXD_0

P1.0 /RXD_ 0/T 2E X

P2.7 /AN7

AREF

AGND

P2.6 /AN6

P2.5 /AN5

P2.4 /AN4

P2.3 /AN3

Figure 4 XC866 Pin Configuration, PG-TSSOP-38 Package (top view)

Data Sheet 7 V1.1, 2006-12

General Device Information

2.4 Pin Definitions and Functions

Table 3 Pin Definitions and Functions

Symbol Pin

Number

P0 I/O Port 0

P0.0 12 Hi-Z TCK_0 JTAG Clock Input

P0.1 14 Hi-Z TDI_0 JTAG Serial Data Input

P0.2 13 PU CTRAP_2

P0.3 2 Hi-Z SCK_1 SSC Clock Input/Output

P0.4 3 Hi-Z MTSR_1 SSC Master Transmit Output/

P0.5 4 Hi-Z MRST_1 SSC Master Receive Input/

Type Reset

State

Function

Port 0 is a 6-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, and the SSC.

T12HR_1 CCU6 Timer 12 Hardware Run

Input

CC61_1 Input/Output of Capture/Compare

channel 1 CLKOUT Clock Output RXDO_1 UART Transmit Data Output

T13HR_1 CCU6 Timer 13 Hardware Run

Input RXD_1 UART Receive Data Input COUT61_1 Output of Capture/Compare

channel 1 EXF2_1 Timer 2 External Flag Output

CCU6 Trap Input TDO_0 JTAG Serial Data Output TXD_1 UART Transmit Data Output/

Clock Output

COUT63_1 Output of Capture/Compare

channel 3

Slave Receive Input

CC62_1 Input/Output of Capture/Compare

channel 2

Slave Transmit Output EXINT0_0 External Interrupt Input 0 COUT62_1 Output of Capture/Compare

channel 2

XC866

Data Sheet 8 V1.1, 2006-12

General Device Information

Table 3 Pin Definitions and Functions (cont’d)

Symbol Pin

Number

Type Reset

State

Function

P1 I/O Port 1

Port 1 is a 5-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, and the SSC.

P1.0 27 PU RXD_0 UART Receive Data Input

T2EX Timer 2 External Trigger Input

P1.1 28 PU EXINT3 External Interrupt Input 3

TDO_1 JTAG Serial Data Output TXD_0 UART Transmit Data Output/

Clock Output

P1.5 29 PU CCPOS0_1 CCU6 Hall Input 0

EXINT5 External Interrupt Input 5 EXF2_0 TImer 2 External Flag Output RXDO_0 UART Transmit Data Output

P1.6 9 PU CCPOS1_1 CCU6 Hall Input 1

T12HR_0 CCU6 Timer 12 Hardware Run

Input EXINT6 External Interrupt Input 6

P1.7 10 PU CCPOS2_1 CCU6 Hall Input 2

T13HR_0 CCU6 Timer 13 Hardware Run

Input

P1.5 and P1.6 can be used as a software chip select output for the SSC.

XC866

Data Sheet 9 V1.1, 2006-12

General Device Information

Table 3 Pin Definitions and Functions (cont’d)

Symbol Pin

Number

Type Reset

State

Function

P2 I Port 2

Port 2 is an 8-bit general purpose input-only port. It can be used as alternate functions for the digital inputs of the JTAG and CCU6. It is also used as the analog inputs for the ADC.

P2.0 15 Hi-Z CCPOS0_0 CCU6 Hall Input 0

EXINT1 External Interrupt Input 1 T12HR_2 CCU6 Timer 12 Hardware Run

Input TCK_1 JTAG Clock Input CC61_3 Input of Capture/Compare channel 1 AN0 Analog Input 0

P2.1 16 Hi-Z CCPOS1_0 CCU6 Hall Input 1

EXINT2 External Interrupt Input 2 T13HR_2 CCU6 Timer 13 Hardware Run

Input TDI_1 JTAG Serial Data Input CC62_3 Input of Capture/Compare channel 2 AN1 Analog Input 1

P2.2 17 Hi-Z CCPOS2_0 CCU6 Hall Input 2

CTRAP_1

CCU6 Trap Input CC60_3 Input of Capture/Compare channel 0 AN2 Analog Input 2

P2.3 20 Hi-Z AN3 Analog Input 3

P2.4 21 Hi-Z AN4 Analog Input 4

P2.5 22 Hi-Z AN5 Analog Input 5

P2.6 23 Hi-Z AN6 Analog Input 6

P2.7 26 Hi-Z AN7 Analog Input 7

XC866

Data Sheet 10 V1.1, 2006-12

XC866

General Device Information

Table 3 Pin Definitions and Functions (cont’d)

Symbol Pin

Number

P3 I Port 3

P3.0 32 Hi-Z CCPOS1_2 CCU6 Hall Input 1

P3.1 33 Hi-Z CCPOS0_2 CCU6 Hall Input 0

P3.2 34 Hi-Z CCPOS2_2 CCU6 Hall Input 2

P3.3 35 Hi-Z COUT61_0 Output of Capture/Compare

P3.4 36 Hi-Z CC62_0 Input/Output of Capture/Compare

P3.5 37 Hi-Z COUT62_0 Output of Capture/Compare

P3.6 30 PD CTRAP_0

P3.7 31 Hi-Z EXINT4 External Interrupt Input 4

Type Reset

State

Function

Port 3 is a bidirectional general purpose I/O port. It can be used as alternate functions for the CCU6.

CC60_0 Input/Output of Capture/Compare

channel 0

CC61_2 Input/Output of Capture/Compare

channel 1 COUT60_0 Output of Capture/Compare

channel 0

CC61_0 Input/Output of Capture/Compare

channel 1

channel 2

CCU6 Trap Input

COUT63_0 Output of Capture/Compare

channel 3

Data Sheet 11 V1.1, 2006-12

General Device Information

Table 3 Pin Definitions and Functions (cont’d)

Symbol Pin

Number

DDP

SSP

DDC

SSC

AREF

AGND

18 – – I/O Port Supply (3.3 V/5.0 V)

19 – – I/O Port Ground

8––Core Supply Monitor (2.5 V)

7––Core Supply Ground

25 – – ADC Reference Voltage

24 – – ADC Reference Ground

Type Reset

State

Function

XTAL1 6IHi-ZExternal Oscillator Input

(NC if not needed)

XTAL2 5OHi-ZExternal Oscillator Output

(NC if not needed)

TMS 11 I PD Test Mode Select

RESET

38 I PU Reset Input

MBC 1IPUMonitor & BootStrap Loader Control

XC866

Data Sheet 12 V1.1, 2006-12

XC866

Functional Description

3 Functional Description

3.1 Processor Architecture

The XC866 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the XC866 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. Access to the Flash memory, however, requires an additional wait state (one machine cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions.

The XC866 CPU provides a range of debugging features, including basic stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory and SFRs.

Figure 5 shows the CPU functional blocks.

Internal Data

Memory

External SFRs

External Data

Memory

Core SFRs

Regist er Int erfac e

Program Memory

CCLK

Memory Wait

Reset

Legacy Exter nal Interrupts (IEN0, IEN1)

External Interrupts

Non-Maskable Interrupt

16-bit R egis t ers & Memory Interface

Opcode & Imm ediate

Registers

Opcode D ecoder

State Mac hine &

Power Saving

Interrupt

Cont roller

ALU

Mult ipli er / D iv ider

Timer 0 / Timer 1

UART

Figure 5 CPU Block Diagram

Data Sheet 13 V1.1, 2006-12

Functional Description

3.2 Memory Organization

The XC866 CPU operates in the following five address spaces:

• 8 Kbytes of Boot ROM program memory

• 256 bytes of internal RAM data memory

• 512 bytes of XRAM memory (XRAM can be read/written as program memory or external data memory)

• a 128-byte Special Function Register area

• 4/8/16 Kbytes of Flash program memory (Flash devices); or 8/16 Kbytes of ROM program memory, with additional 4 Kbytes of Flash (ROM devices)

Figure 6 illustrates the memory address spaces of the XC866-4FR device.

XC866

FFFF

F200

XRAM

512 bytes

Boot RO M

8 Kby tes

D-Fl ash Bank

4 Kbytes

P-F lash B ank 2

4 Kbytes

P-F lash B ank 1

4 Kbytes

P-F lash B ank 0

4 Kbytes

Progr am Space Ext ernal Data S pace Internal Data S pace

1) For X C866-1FR devic e, physical ly one 4KB yte D-Flas h bank is mapped to both address range 0000H - 0FFFH and A 000H - AFFFH, and the shaded banks are not availabl e.

2) For X C866-2FR devic e, the shaded banks are not av ailable.

F000

E000

C000

B000

A000

3000

2000

1000

0000

XRAM

512 bytes

FFFF

F200

F000

0000

Indirec t

Address

Internal RA M

Direct

Address

Speci al Function

Figure 6 Memory Map of XC866 Flash Devices

Data Sheet 14 V1.1, 2006-12

Functional Description

Figure 7 illustrates the memory address spaces of the XC866-4RR device.

FFFF

XC866

XRAM

512 Bytes

Boot ROM

8 KBytes

Flash (4K-X bytes)

User ROM (X bytes)

Total 4 KByte s

User RO M 4 KB ytes

User RO M

8 KBytes

F200

F000

E000

C000

B000

A000

3000

2000

0000

XRAM

512 Bytes

F200

F000

0000

Indirec t

Addres s

Internal RAM

Code S pace Ex ternal Data Space Internal Data Space

1) For XC866-2RR device, the shaded area is not available and Flash is 4 Kbytes.

2) For XC866-4RR device: ROM = (12+X) KBytes, Flash = (4-X) Kbytes.

Special Function

Internal RAM

Direct

Addr ess

Regis ters

Memory Map User Mode

Figure 7 Memory Map of XC866 ROM Devices

Data Sheet 15 V1.1, 2006-12

XC866

Functional Description

3.2.1 Memory Protection Strategy

The XC866 memory protection strategy includes:

• Read-out protection: The Flash Memory can be enabled for read-out protection and ROM memory is always protected.

• Program and erase protection: The Flash memory in all devices can be enabled for program and erase protection.

Flash memory protection is available in two modes:

• Mode 0: Only the P-Flash is protected; the D-Flash is unprotected

• Mode 1: Both the P-Flash and D-Flash are protected

The selection of each protection mode and the restrictions imposed are summarized in

Table 4.

Table 4 Flash Protection Modes

Mode 01

Activation Program a valid password via BSL mode 6

Selection MSB of password = 0 MSB of password = 1

P-Flash contents can be read by

P-Flash program and erase

D-Flash contents can be read by

D-Flash program Possible Not possible

D-Flash erase Possible, on the condition that bit

Read instructions in the P-Flash

Not possible Not possible

Read instructions in any program memory

DFLASHEN in register MISC_CON is set to 1 prior to each erase operation

Read instructions in the P-Flash or D-Flash

Not possible

BSL mode 6, which is used for enabling Flash protection, can also be used for disabling Flash protection. Here, the programmed password must be provided by the user. A password match triggers an automatic erase of the read-protected Flash contents, see

Table 5 and Table 6, and the programmed password is erased. The Flash protection is

then disabled upon the next reset.

For XC866-2FR and XC866-4FR devices:

The selection of protection type is summarized in Table 5.

Data Sheet 16 V1.1, 2006-12

Functional Description

Table 5 Flash Protection Type for XC866-2FR and XC866-4FR devices

PASSWORD Type of Protection Flash Banks to Erase when

Unprotected

1XXXXXXX 0XXXXXXX

B B

Flash Protection Mode 1 All Banks Flash Protection Mode 0 P-Flash Bank

For XC866-1FR device and ROM devices:

The selection of protection type is summarized in Table 6.

Table 6 Flash Protection Type for XC866-1FR device and ROM devices

XC866

PASSWORD Type of Protection

(Applicable to the

Sectors to Erase when Unprotected

Comments

whole Flash)

1XXXXXXX

Read/Program/Erase All Sectors Compatible to

Protection mode 1 00001XXX 00010XXX 00011XXX 00100XXX 00101XXX 00110XXX 00111XXX 01000XXX 01001XXX 01010XXX

B B B B B B B B B B

Erase Sector 0 Erase Sector 0 and 1 Erase Sector 0 to 2 Erase Sector 0 to 3 Erase Sector 0 to 4 Erase Sector 0 to 5 Erase Sector 0 to 6 Erase Sector 0 to 7 Erase Sector 0 to 8 Erase All Sectors

Others Erase None

Although no protection scheme can be considered infallible, the XC866 memory protection strategy provides a very high level of protection for a general purpose microcontroller.

Data Sheet 17 V1.1, 2006-12

XC866

Functional Description

3.2.2 Special Function Register

The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80

to FFH. All registers, except the program counter, reside in the SFR area. The

SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR range is less than the total number of registers required, address extension mechanisms are required to increase the number of addressable SFRs. The address extension mechanisms include:

• Mapping

• Paging

3.2.2.1 Address Extension by Mapping

Address extension is performed at the system level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80 of addressable SFRs to 256. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit RMAP in the system control register SYSCON0 at address 8F

. To access SFRs in the mapped area, bit RMAP in SFR

SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 8.

SYSCON0 System Control Register 0 Reset Value: 00

765432 10

to FFH, bringing the number

010RMAP

rrwrrw

Field Bits Type Description

RMAP 0rwSpecial Function Register Map Control

0 The access to the standard SFR area is

enabled.

1 The access to the mapped SFR area is

enabled.

1 2rwReserved

Returns the last value if read; should be written with 1.

0 1,[7:3] r Reserved

Returns 0 if read; should be written with 0.

Data Sheet 18 V1.1, 2006-12

XC866

Functional Description

Note: The RMAP bit must be cleared/set by ANL or ORL instructions. The rest bits of

SYSCON0 should not be modified.

As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, before standard/mapped registers are accessed, bit RMAP must be cleared/set, respectively, by software.

SFR Data

(to/from CPU)

SYSCON0.RMAP

Standard Area (R MAP = 0)

Module 1 SFRs

Module 2 SFRs

…...

Module n SFRs

Mapped Area (RMAP = 1)

Module (n+1) SFRs

Module (n+2) SFRs

…...

Module m SFRs

Direct

Internal Data

Memory Address

Figure 8 Address Extension by Mapping

Data Sheet 19 V1.1, 2006-12

XC866

Functional Description

3.2.2.2 Address Extension by Paging

Address extension is further performed at the module level by paging. With the address extension by mapping, the XC866 has a 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit field PAGE in the module page register MOD_PAGE. Hence, the bit field PAGE must be programmed before accessing the SFR of the target module. Each module may contain a different number of pages and a different number of SFRs per page, depending on the specific requirement. Besides setting the correct RMAP bit value to select the SFR area, the user must also ensure that a valid PAGE is selected to target the desired SFR. A page inside the extended address range can be selected as shown in Figure 9.

SFR Address

(from CPU)

MOD_PAGE.PAGE

PAGE 0

SFR0

SFR1

…...

SFRx

PAGE 1

SFR Data

(to/from CPU )

SFR0

SFR1

…...

SFRy

…...

PAGE q

SFR0

SFR1

…...

SFRz

Module

Figure 9 Address Extension by Paging

Data Sheet 20 V1.1, 2006-12

XC866

Functional Description

In order to access a register located in a page different from the actual one, the current page must be left. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access be performed.

If an interrupt routine is initiated between the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the new one programmed and finally, the old page setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore action of the current page setting. By indicating which storage bit field should be used in parallel with the new page value, a single write operation can:

• Save the contents of PAGE in STx before overwriting with the new value

(this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or

• Overwrite the contents of PAGE with the contents of STx, ignoring the value written to

the bit positions of PAGE (this is done at the end of the interrupt routine to restore the previous page setting before the interrupt occurred)

ST3

ST2

ST1

ST0

STNR

value update

from CPU

PAGE

Figure 10 Storage Elements for Paging

With this mechanism, a certain number of interrupt routines (or other routines) can perform page changes without reading and storing the previously used page information. The use of only write operations makes the system simpler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines.

The XC866 supports local address extension for:

• Parallel Ports

• Analog-to-Digital Converter (ADC)

• Capture/Compare Unit 6 (CCU6)

• System Control Registers

Data Sheet 21 V1.1, 2006-12

XC866

Functional Description

The page register has the following definition:

MOD_PAGE Page Register fo r mod ule M OD Reset V alue : 00

765432 10

OP STNR 0 PAGE

wwr rw

Field Bits Type Description

PAGE [2:0] rw Page Bits

When written, the value indicates the new page. When read, the value indicates the currently active page.

STNR [5:4] w Storage Number

This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11 the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored.

00 ST0 is selected. 01 ST1 is selected. 10 ST2 is selected. 11 ST3 is selected.

Data Sheet 22 V1.1, 2006-12

Field Bits Type Description

OP [7:6] w Operation

0X Manual page mode. The value of STNR is

ignored and PAGE is directly written.

10 New page programming with automatic page

saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR.

11 Automatic restore page action. The value

written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR.

0 3r Reserved

Returns 0 if read; should be written with 0.

XC866

Functional Description

Data Sheet 23 V1.1, 2006-12

XC866

Functional Description

3.2.3 Bit Protection Scheme

The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11 bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit field PASS closes access to writing of all protected bits. Note that access is opened for maximum 32 CCLKs if the “close access” password is not written. If “open access” password is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles. The protected bits include NDIV, WDTEN, PD, and SD.

PASSWD Password Register Reset Value: 07

76543210

PASS

wh rh rw

PROTECT

Field Bits Type Description

MODE [1:0] rw Bit Protection Scheme Control bits

00 Scheme Disabled 11 Scheme Enabled (default) Others: Scheme Enabled These two bits cannot be written directly. To change the value between 11B and 00B, the bit field PASS must be written with 11000 MODE[1:0] be registered.

PROTECT_S 2rhBit Protection Signal Status bit

This bit shows the status of the protection. 0 Software is able to write to all protected bits. 1 Software is unable to write to any protected

bits.

PASS [7:3] wh Password bits

The Bit Protection Scheme only recognizes three patterns. 11000BEnables writing of the bit field MODE. 10011BOpens access to writing of all protected bits. 10101BCloses access to writing of all protected bits.

, writing 10011B to the

; only then, will the

MODE

Data Sheet 24 V1.1, 2006-12

XC866

Functional Description

3.2.4 XC866 Register Overview

The SFRs of the XC866 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Table 7 to Table 15, with the addresses of the bitaddressable SFRs appearing in bold typeface.

The CPU SFRs can be accessed in both the standard and mapped memory areas (RMAP = 0 or 1).

Table 7 CPU Register Overview

AddrRegister Name Bit 76543210

RMAP = 0 or 1

SP Reset: 07

Stack Pointer Register

DPL Reset: 00

Data Pointer Register Low

DPH Reset: 00

Data Pointer Register High

PCON Reset: 00

Power Control Register

TCON Reset: 00

Timer Control Register

TMOD Reset: 00

Timer Mode Register

TL0 Reset: 00

Timer 0 Register Low

TL1 Reset: 00

Timer 1 Register Low

TH0 Reset: 00

Timer 0 Register High

TH1 Reset: 00

Timer 1 Register High

SCON Reset: 00

Serial Channel Control Register

SBUF Reset: 00

Serial Data Buffer Register

EO Reset: 00

Extended Operation Register

IEN0 Reset: 00

Interrupt Enable Register 0

IP Reset: 00

Interrupt Priority Register

IPH Reset: 00

Interrupt Priority Register High

PSW Reset: 00

Program Status Word Register

ACC Reset: 00

Accumulator Register

IEN1 Reset: 00

Interrupt Enable Register 1

Bit Field

Type rw

Bit Field DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0

Type rw rw rw rw rw rw rw rw

Bit Field DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0

Type rw rw rw rw rw rw rw rw

Bit Field SMOD 0 GF1 GF0 0 IDLE

Type rw r rw rw r rw

Bit Field TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Type rwh rw rwh rw rwh rw rwh rw

Bit Field GATE1 0 T1M GATE0 0 T0M

Type rw r rw rw r rw

Bit Field VAL

Type rwh

Bit Field VAL

Type rwh

Bit Field VAL

Type rwh

Bit Field VAL

Type rwh

Bit Field

Type rw rw rw rw rw rwh rwh rwh

Bit Field

Type rwh

Bit Field

SM0 SM1 SM2 REN TB8 RB8 TI RI

0 TRAP_

Type r rw r rw

Bit Field EA 0 ET2 ES ET1 EX1 ET0 EX0

Type rw r rwrwrwrwrwrw

Bit Field 0 PT2 PS PT1 PX1 PT0 PX0

Type r rwrwrwrwrwrw

Bit Field

Type r rwrwrwrwrwrw

Bit Field CY AC F0 RS1 RS0 OV F1 P

Type rw rwh rwh rw rw rwh rwh rh

Bit Field ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0

Type rw rw rw rw rw rw rw rw

Bit Field ECCIP3ECCIP2ECCIP1ECCIP0EXM EX2 ESSC EADC

0 PT2H PSH PT1H PX1H PT0H PX0H

Type rw rw rw rw rw rw rw rw

VAL

0 DPSEL

Data Sheet 25 V1.1, 2006-12

XC866

Functional Description

Table 7 CPU Register Overview (cont’d)

AddrRegister Name Bit 76543210

B Reset: 00

B Register

IP1 Reset: 00

Interrupt Priority Register 1

IPH1 Reset: 00

Interrupt Priority Register 1 High

The system control SFRs can be accessed in the standard memory area (RMAP = 0).

Table 8 System Control Register Overview

AddrRegister Name Bit 76543210

RMAP = 0 or 1

SYSCON0 Reset: 00

System Control Register 0

RMAP = 0

SCU_PAGE Reset: 00

Page Register for System Control

RMAP = 0, Page 0

MODPISEL Reset: 00

Peripheral Input Select Register

B4HIRCON0 Reset: 00

Interrupt Request Register 0

IRCON1 Reset: 00

Interrupt Request Register 1

EXICON0 Reset: 00

External Interrupt Control Register 0

EXICON1 Reset: 00

External Interrupt Control Register 1

NMICON Reset: 00

NMI Control Register

BCHNMISR Reset: 00

NMI Status Register

BCON Reset: 00

Baud Rate Control Register

BG Reset: 00

Baud Rate Timer/Reload Register

FDCON Reset: 00

Fractional Divider Control Register

FDSTEP Reset: 00

Fractional Divider Reload Register

FDRES Reset: 00

Fractional Divider Result Register

RMAP = 0, Page 1

Bit Field B7 B6 B5 B4 B3 B2 B1 B0

Type rw rw rw rw rw rw rw rw

Bit Field PCCIP3PCCIP2PCCIP1PCCIP0PXM PX2 PSSC PADC

Type rw rw rw rw rw rw rw rw

Bit Field PCCIP3HPCCIP2HPCCIP1HPCCIP0HPXMH PX2H PSSCH PADC

Type rw rw rw rw rw rw rw rw

Bit Field 0 RMAP

Type r rw

Bit Field OP STNR 0 PAGE

Type w w r rw

Bit Field 0 JTAG

TDIS

JTAG TCKS

0 EXINT

0IS

Type r rw rw r rw rw

Bit Field 0 EXINT6EXINT5EXINT4EXINT3EXINT2EXINT1EXINT

Type r rwh rwh rwh rwh rwh rwh rwh

Bit Field 0 ADCS

RC1

ADCS

RC0

RIR TIR EIR

Type r rwh rwh rwh rwh rwh

Bit Field EXINT3 EXINT2 EXINT1 EXINT0

Type rw rw

Bit Field

Type r rw rw rw

Bit Field

0 EXINT6 EXINT5 EXINT4

0 NMI

ECC

NMI

VDDP

NMI VDD

Type r rw rw rw

Bit Field

0 FNMI

ECC

FNMI

VDDP

FNMI

VDD

Type r rwh rwh rwh

Bit Field BGSEL 0 BREN BRPRE R

Type rw r rw rw rw

Bit Field

Type rw

Bit Field

BGS SYNEN ERRSYNEOFSYNBRK NDOV FDM FDEN

BR_VALUE

Type rw rw rwh rwh

Bit Field STEP

Type rw

Bit Field RESULT

Type rh

rw rw

NMI

FLASH

NMI PLL

OCDS

rw rw rw rw

FNMI

FLASH

FNMI

PLL

OCDS

rwh rwh rwh rwh

rwh rwh rw rw

URRIS

NMI

WDT

FNMI WDT

Data Sheet 26 V1.1, 2006-12

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