Temperature
Storage Temperature
Humidity (Operating)
Dimensions
Table 1-3: ICE-DB-T6 Specifications
2 x DisplayPort
3 x Audio jacks (Line-in, Line-out, Mic)
1 x PS/2 keyboard
1 x PS/2 mouse
ATX/AT p o w e r s upply
-10ºC ~ 60ºC
-20ºC ~ 70ºC
5% ~ 95% (non-condensing)
304.8 mm x 243.8 mm (12” x 9.6”)
Page 9
Type 6 Carrier Board Design Guide
Chapter
2
2 Pin Assignments
Page 10
Type 6 Carrier Board Design Guide
2.1 Chapter Overview
This chapter describes pin assignments and I/O characteristics for COM Express modules.
The carrier board uses two 220-pin 0.5 mm fine pitch board-to-board connectors. There
are seven different pin-out types currently defined by the COM Express Specification. The
preferred choice of the embedded computer industry is the Type 2 pin-out and the latest
pin-outs added in COM Express specification are Type 6 and Type 10. This design guide
focuses on the latest Type 6 pin-out which provides the latest technologies including PCI
Express, Serial ATA and DDI graphics.
Figure 2-1: COM Express Type 6 Module Diagram
Page 11
Type 6 Carrier Board Design Guide
2.2 COM Express Connector Type
The differences among the Module Types are summarized in Table 2-1.
Module Type 1 and 10 supports a single connector with two rows of pins
(220 pins total).
Module Types 2-6 support two connectors with four rows of pins
(440 pins total).
Type Rows PCIe
Lanes
1 AB Up to 6 - - - 4 1 8 / 0 VGA, LVDS
2 AB, CD Up to 22 1/2 32-bit 1 4 1 8 / 0 VGA, LVDS,
3 AB, CD Up to 22 1/2 32-bit - 4 3 8 / 0 VGA, LVDS,
4 AB, CD Up to 32 1/2 - 1 4 1 8 / 0 VGA, LVDS,
5 AB, CD Up to 32 1/2 - - 4 3 8 / 0 VGA, LVDS,
6 AB, CD Up to 24 1/NA - - 4 1 8 / 4 VGA, LVDS,
10 AB Up to 4 -/1 - - 2 1 8 / 0 1 x DDI
PEG/
SDVO
PCI IDE SATA LAN USB
2.0/3.0
Table 2-1: COM Express Connector Type Variations
Display
PEG/SDVO
PEG/SDVO
PEG/SDVO
PEG/SDVO
PEG, 3 x DDI
Page 12
Type 6 Carrier Board Design Guide
2.3 Signal Table Terminology
The following section describes the signals found on the Type 6 connectors. Table 2-2
below describes the terminology used in this section for the Signal Description tables. The
“#” symbol at the end of the signal name indicates that the active or asserted state occurs
when the signal is at a low voltage level. When “#” is not present, the signal is asserted
when at a high voltage level.
Term Description
I/O Bi-directional signal
I Input signal
O Output signal
I/F Interface
GND Ground
PWR Power
OD Open drain output
PD Pull down
PU Pull up
+V12 +12V ±5% Volts Normal Power
+V5SB +5V ±5% Standby Power
+3.3VSB +3.3V ±5% Standby Power
+V3.3 +3.3V ±5% Volts Normal Power
+V5 +5V ±5% Volts Normal Power
# Active-Low Signals
‘+’ and ‘-‘ Differential Pairs
PM Power Management
GBE Gigabit Ethernet
Table 2-2: Conventions and Terminology
Page 13
Type 6 Carrier Board Design Guide
2.4 Connector Pinout Row A and Row B
Pin Signal I/F I/O Pin Signal I/F I/O
A1 GND0 GND - B1 GND15 GND -
A2 GBE0_MDI3- GBE I/O B2 GBE0_ACT# GBE O 3.3V
A3 GBE0_MDI3+ GBE I/O B3 LPC_FRAME# LPC O 3.3V
A4 GBE0_LINK100# GBE O 3.3VB4 LPC_AD0 LPC I/O 3.3V
A5 GBE0_LINK1000# GBE O 3.3VB5 LPC_AD1 LPC I/O 3.3V
A6 GBE0_MDI2- GBE I/O B6 LPC_AD2 LPC I/O 3.3V
A7 GBE0_MDI2+ GBE I/O B7 LPC_AD3 LPC I/O 3.3V
A8 GBE0_LINK# GBE O 3.3VB8 LPC_DRQ0# LPC I 3.3V
A9 GBE0_MDI1- GBE I/O B9 LPC_DRQ1# LPC I 3.3V
A10 GBE0_MDI1+ GBE I/O B10 LPC_CLK LPC O 3.3V
A11 GND1 GND - B11 GND16 GND -
A12 GBE0_MDI0- GBE I/O B12 PWRBTN# PM I
A13 GBE0_MDI0+ GBE I/O B13 SMB_CK SMB -
A14 GBE0_CTREF GBE B14 SMB_DAT SMB -
A15 SUS_S3# PM O B15 SMB_ALERT# SMB I
A16 SATA0_TX+ SATA O B16 SATA1_TX+ SATA O
A17 SATA0_TX- SATA O B17 SATA1_TX- SATA O
A18 SUS_S4# PM O B18 SUS_STAT# PM O
A19 SATA0_RX+ SATA I B19 SATA1_RX+ SATA I
A20 SATA0_RX- SATA I B20 SATA1_RX- SATA I
A21 GND2 GND - B21 GND17 GND -
A22 SATA2_TX+ SATA O B22 SATA3_TX+ SATA O
A23 SATA2_TX- SATA O B23 SATA3_TX- SATA O
A24 SUS_S5# PM O B24 PWR_OK PM I
A25 SATA2_RX+ SATA I B25 SATA3_RX+ SATA I
A26 SATA2_RX- SATA I B26 SATA3_RX- SATA I
A27 BATLOW# PM I B27 WDT - -
A28 ATA_ACT# SATA O 3.3VB28 AC/HD_SDIN2 HDA I 3.3V
A29 AC/HD _SYNC HDA O 3.3VB29 AC/HD_SDIN1 HDA I 3.3V
A30 AC/HD _RST# HDA O 3.3VB30 AC/HD_SDIN0 HDA I 3.3V
A31 GND3 GND - B31 GND18 GND -
A32 AC/HD_BITCLK HDA O 3.3VB32 SPKR - -
A33 AC/HD_SDOUT HDA O 3.3VB33 I2C_CK I2C -
A34 BIOS_DISABLE# - - B34 I2C_DAT I2C -
A35 THRMTRIP# PM O B35 THRM# PM I
A36 USB6- USB I/O B36 USB7- USB I/O
A37 USB6+ USB I/O B37 USB7+ USB I/O
A38 USB_6_7_OC# USB I 3.3V B38 USB_4_5_OC# USB I 3.3V
A39 USB4- USB I/O B39 USB5- USB I/O
A40 USB4+ USB I/O B40 USB5+ USB I/O
A41 GND4 GND - B41 GND19 GND -
A42 USB2- USB I/O B42 USB3- USB I/O
A43 USB2+ USB I/O B43 USB3+ USB I/O
A44 USB_2_3_OC# USB I 3.3V B44 USB_0_1_OC# USB I 3.3V
A45 USB0- USB I/O B45 USB1- USB I/O
Page 14
Type 6 Carrier Board Design Guide
Pin Signal I/F I/O Pin Signal I/F I/O
A46 USB0+ USB I/O B46 USB1+ USB I/O
A47 VCC_RTC PWR -- B47 EXCD1_PERST# PCIE -
A48 EXCD0_PERST# PCIE - B48 EXCD1_CPPE# PCIE -
A49 EXCD0_CPPE# PCIE - B49 SYS_RESET# PM I
A50 LPC_SERIRQ LPC I/O
3.3V
A51 GND5 GND - B51 GND20 GND -
A52 PCIE_TX5+ PCIE O B52 PCIE_RX5+ PCIE I
A53 PCIE_TX5- PCIE O B53 PCIE_RX5- PCIE I
A54 GPI0 GPIO I B54 GPO1 GPIO O
A55 PCIE_TX4+ PCIE O B55 PCIE_RX4+ PCIE I
A56 PCIE_TX4- PCIE O B56 PCIE_RX4- PCIE I
A57 GND6 GND - B57 GPO2 GPIO O
A58 PCIE_TX3+ PCIE O B58 PCIE_RX3+ PCIE I
A59 PCIE_TX3- PCIE O B59 PCIE_RX3- PCIE I
A60 GND7 GND - B60 GND21 GND -
A61 PCIE_TX2+ PCIE O B61 PCIE_RX2+ PCIE I
A62 PCIE_TX2- PCIE O B62 PCIE_RX2- PCIE I
A63 GPI1 GPIO I B63 GPO3 GPIO O
A64 PCIE_TX1+ PCIE O B64 PCIE_RX1+ PCIE I
A65 PCIE_TX1- PCIE O B65 PCIE_RX1- PCIE I
A66 GND8 GND - B66 WAKE0# PCIE I
A67 GPI2 GPIO I B67 WAKE1# PM I
A68 PCIE_TX0+ PCIE O B68 PCIE_RX0+ PCIE I
A69 PCIE_TX0- PCIE O B69 PCIE_RX0- PCIE I
A70 GND9 GND - B70 GND22 GND -
A71 LVD S_A0+ LVD S O B71 LVDS_B0+ LVDS O
A72 LVD S_A0- LVDS O B72 LVDS_B0 - LV D S O
A73 LVD S_A1+ LVD S O B73 LVDS_B1+ LVDS O
A74 LVD S_A1- LVDS O B74 LVDS_B1 - LV D S O
A75 LVD S_A2+ LVD S O B75 LVDS_B2+ LVDS O
A76 LVD S_A2- LVDS O B76 LVDS_B2 - LV D S O
A77 LVDS_VDD_EN LVDS O 3.3VB77 LVDS_B3+ LVDS O
A78 LVD S_A3+ LVD S O B78 LVDS_B3- LVDS O
A79 LVD S_A3- LVDS O B79 LVDS_BKLT_EN LVDS O 3.3V
A80 GND GND - B80 GND GND -
A81 LVD S_A_CK+ LVDS O B81 LV D S _ B _ C K+ LVDS O
A82 LVD S_A_CK- LVDS O B82 LVDS_B_ C K - LV D S O
A83 LVDS_I2C_CK LVDS O 3.3VB83 LVDS_BKLT_CTRL LVDS O 3.3V
A84 LVDS_I2C_DAT LVDS IO 3.3VB84 VCC5SBY1 PWR -
A85 GPI3 GPIO I B85 VCC5SBY2 PWR -
A86 RSVD - - B86 VCC5SBY3 PWR -
A87 RSVD - - B87 VCC5SBY4 PWR -
A88 PCIE0_CK_REF+ PCIE O B88 BIOS_DIS1# - I 3.3V
A89 PCIE0_CK_REF- PCIE O B89 VGA_RED VGA O
A90 GND11 GND - B90 GND 24 GND -
A91 SPI_VCC SPI O 3.3VB91 VGA_GRN VGA O
A92 SPI_MISO SPI IO 3.3VB92 VGA_BLU VGA O
B50 CB_RESET# PM O
Page 15
Pin Signal I/F I/O Pin Signal I/F I/O
A93 GPO0 GPIO O B93 VGA_HSYNC VGA O
A94 SPI_CLK SPI O B94 VGA_VSYNC VGA O
A95 SPI_MOSI SPI IO B95 VGA_I2C_CK VGA I/O
A96 PP_TPM TPM I B96 VGA_I2C_DAT VGA I/O
A97 RSVD - - B97 SPI_CS# SPI O
A98 RS1_TX UART O B98 RSVD - -
A99 RS1_RX UART I B99 RSVD - -
A100 GND13 GND - B100 GND25 GND -
A101 RS2_TX UART O B101 FAN_PWMOUT FAN O
A102 RS2_RX UART I B102 FAN_TACHIN FAN I
A103 LID# - I B103 SLEEP# - I
A104 VCC_12V7 PWR - B104 VCC_12V16 PWR -
A105 VCC_12V8 PWR - B105 VCC_12V17 PWR -
A106 VCC_12V9 PWR - B106 VCC_12V18 PWR -
A107 VCC_12V10 PWR - B107 VCC_12V19 PWR -
A108 VCC_12V11 PWR - B108 VCC_12V20 PWR -
A109 VCC_12V12 PWR - B109 VCC_12V21 PWR -
A110 GND14 GND - B110 GND26 GND -
Type 6 Carrier Board Design Guide
2.5 Connector Pinout Rows C and D
Pin Signal I/F I/O Pin Signal I/F I/O
C1 GND0 GND - D1 GND15 GND -
C2 GND GND - D2 GND GND -
C3 USB_SSRX0- USB 3.0 I D3 USB_SSTX0- USB 3.0 O
C4 USB_SSRX0+ USB 3.0 I D4 USB_SSTX0+ USB 3.0 O
C5 GND GND - D5 GND GND -
C6 USB_SSRX1- USB 3.0 I D6 USB_SSTX1- USB 3.0 O
C7 USB_SSRX1+ USB 3.0 I D7 USB_SSTX1+ USB 3.0 O
C8 GND GND - D8 GND GND -
C9 USB_SSRX2- USB 3.0 I D9 USB_SSTX2- USB 3.0 O
C10 USB_SSRX2+ USB 3.0 I D10 USB_SSTX2+ USB 3.0 O
C11 GND1 GND - D11 GND16 GND -
C12 USB_SSRX3- USB 3.0 I D12 USB_SSTX3- USB 3.0 O
C13 USB_SSRX3+ USB 3.0 I D13 USB_SSTX3+ USB 3.0 O
C14 GND GND - D14 GND GND -
C15 DDI1_PAIR6+ DDI O D15 DDI1_AUX+ DDI O
C16 DDI1_PAIR6- DDI O D16 DDI1_AUX- DDI O
C17 RSVD - - D17 RSVD - -
C18 RSVD - - D18 RSVD - -
C19 PCIE_RX6+ PCIE I D19 PCIE_TX6+ PCIE O
C20 PCIE_RX6- PCIE I D20 PCIE_TX6- PCIE O
C21 GND2 GND - D21 GND17 GND -
C22 RSVD - - D22 RSVD - -
C23 RSVD - - D23 RSVD - -
C24 DDI1_HPD DDI I D24 RSVD - -
C25 DDI1_PAIR4+ DDI O D25 RSVD - -
Page 16
Type 6 Carrier Board Design Guide
Pin Signal I/F I/O Pin Signal I/F I/O
C26 DDI1_PAIR4- DDI O D26 DDI1_PAIR0+ DDI O
C27 RSVD - - D27 DDI1_PAIR0- DDI O
C28 RSVD - - D28 RSVD - -
C29 DDI1_PAIR5+ DDI O D29 DDI1_PAIR1+ DDI O
C30 DDI1_PAIR5- DDI O D30 DDI1_PAIR1- DDI O
C31 GND3 GND - D31 GND18 GND -
C32 DDI2_AUX+ DDI O D32 DDI1_PAIR2+ DDI O
C33 DDI2_AUX- DDI O D33 DDI1_PAIR2- DDI O
C34 DDI2_CTRLCLK DDI O D34 DDI2_CTRLDATA DDI O
C35 RSVD - - D35 RSVD - -
C36 DDI3_AUX+ DDI O D36 DDI1_PAIR3+ DDI O
C37 DDI3_AUX- DDI O D37 DDI1_PAIR3- DDI O
C38 DDI3_CTRLCLK DDI O D38 DDI3_CTRLDATA DDI O
C39 DDI3_PAIR0+ DDI O D39 DDI2_PAIR0+ DDI O
C40 DDI3_PAIR0- DDI O D40 DDI2_PAIR0- DDI O
C41 GND4 GND - D41 GND19 GND -
C42 DDI3_PAIR1+ DDI O D42 DDI2_PAIR1+ DDI O
C43 DDI3_PAIR1- DDI O D43 DDI2_PAIR1- DDI O
C44 DDI3_HPD DDI I D44 DDI2_HPD DDI I
C45 RSVD - - D45 RSVD - -
C46 DDI3_PAIR2+ DDI O D46 DDI2_PAIR2+ DDI O
C47 DDI3_PAIR2- DDI O D47 DDI2_PAIR2- DDI O
C48 RSVD - - D48 RSVD - -
C49 DDI3_PAIR3+ DDI O D49 DDI2_PAIR3+ DDI O
C50 DDI3_PAIR3- DDI O D50 DDI2_PAIR3- DDI O
C51 GND5 GND - D51 GND20 GND -
C52 PEG_RX0+ PEG I D52 PEG_TX0+ PEG O
C53 PEG_RX0- PEG I D53 PEG_TX0- PEG O
C54 RSVD - - D54 PEG_LANE_RV#
C55 PEG_RX1+ PEG I D55 PEG_TX1+ PEG O
C56 PEG_RX1- PEG I D56 PEG_TX1- PEG O
C57 RSVD - - D57 TYPE2#
C58 PEG_RX2+ PEG I D58 PEG_TX2+ PEG O
C59 PEG_RX2- PEG I D59 PEG_TX2- PEG O
C60 GND7 GND - D60 GND21 GND -
C61 PEG_RX3+ PEG I D61 PEG_TX3+ PEG O
C62 PEG_RX3- PEG I D62 PEG_TX3- PEG O
C63 RSVD1 - - D63 RSVD9 - -
C64 RSVD2 - - D64 RSVD10 - -
C65 PEG_RX4+ PEG I D65 PEG_TX4+ PEG O
C66 PEG_RX4- PEG I D66 PEG_TX4- PEG O
C67 RSVD3 - O D67 GND28 GND -
C68 PEG_RX5+ PEG I D68 PEG_TX5+ PEG O
C69 PEG_RX5- PEG I D69 PEG_TX5- PEG O
C70 GND9 GND - D70 GND22 GND -
C71 PEG_RX6+ PEG I D71 PEG_TX6+ PEG O
C72 PEG_RX6- PEG I D72 PEG_TX6- PEG O
C73 DDI1_CTRLDATA DDI O D73 DDI1_CTRLCLK DDI O
Page 17
Pin Signal I/F I/O Pin Signal I/F I/O
C74 PEG_RX7+ PEG I D74 PEG_TX7+ PEG O
C75 PEG_RX7- PEG I D75 PEG_TX7- PEG O
C76 GND8 GND - D76 GND29 GND -
C77 RSVD4 - - D77 RSVD - -
C78 PEG_RX8+ PEG I D78 PEG_TX8+ PEG O
C79 PEG_RX8- PEG I D79 PEG_TX8- PEG O
C80 GND10 GND - D80 GND23 GND -
C81 PEG_RX9+ PEG I D81 PEG_TX9+ PEG O
C82 PEG_RX9- PEG I D82 PEG_TX9- PEG O
C83 RSVD5 - - D83 RSVD8 - -
C84 GND6 GND - D84 GND30 GND -
C85 PEG_RX10+ PEG I D85 PEG_TX10+ PEG O
C86 PEG_RX10- PEG I D86 PEG_TX10- PEG O
C87 GND35 GND - D87 GND31 GND -
C88 PEG_RX11+ PEG I D88 PEG_TX11+ PEG O
C89 PEG_RX11- PEG I D89 PEG_TX11- PEG O
C90 GND27 GND - D90 GND24 GND -
C91 PEG_RX12+ PEG I D91 PEG_TX12+ PEG O
C92 PEG_RX12- PEG I D92 PEG_TX12- PEG O
C93 GND11 GND - D93 GND32 GND -
C94 PEG_RX13+ PEG I D94 PEG_TX13+ PEG O
C95 PEG_RX13- PEG I D95 PEG_TX13- PEG O
C96 GND12 GND - D96 GND33 GND -
C97 RSVD6 - - D97 PEG_ENABLE# PEG I
C98 PEG_RX14+ PEG I D98 PEG_TX14+ PEG O
C99 PEG_RX14- PEG I D99 PEG_TX14- PEG O
C100 GND13 GND - D100 GND25 GND -
C101 PEG_RX15+ PEG I D101 PEG_TX15+ PEG O
C102 PEG_RX15- PEG I D102 PEG_TX15- PEG O
C103 GND GND - D103 GND34 GND -
C104 VCC_12V1 PWR - D104 VCC_12V7 PWR -
C105 VCC_12V2 PWR - D105 VCC_12V8 PWR -
C106 VCC_12V3 PWR - D106 VCC_12V9 PWR -
C107 VCC_12V4 PWR - D107 VCC_12V10 PWR -
C108 VCC_12V5 PWR - D108 VCC_12V11 PWR -
C109 VCC_12V6 PWR - D109 VCC_12V12 PWR -
C110 GND14 GND - D110 GND26 GND -
Type 6 Carrier Board Design Guide
Page 18
Type 6 Carrier Board Design Guide
Chapter
3
3 Signal Description and
Routing Guideline
Page 19
Type 6 Carrier Board Design Guide
3.1 PEG (PCI Express Graphic)
The PEG Port can utilize COM Express PCIe lanes 16 through 32 to drive a PCIe x16 link
for a PCI Express Graphics card. It supports a theoretical bandwidth of up to 4 GB/s. Each
lane of the PEG Port consists of a receiver and transmit differential signal pair. The
corresponding signals can be found on the Module connector rows C and D.