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BUFFER/CLOCK DRIVER MK3807-01
Description
The MK3807-01 is a low skew 3.3 V, 1 to 10 fanout buffer.
The large fanout from a single input line reduces loading on
the input clock. The TTL level outputs reduce noise levels on
the part. Typical applications are clock and signal
distribution.
Block Diagram
Features
• Packaged in 20-pin SSOP
• Available in Pb (lead) free package
• 1 to 10 fanout buffer
• Maximum skew between outputs of same package 0.35
ns
• Maximum skew between outputs of different packages
0.75 ns
• Max propagation delay of 3.8 ns
• Operating voltage of 3.3 V
• Advanced, low power, CMOS process
• Industrial temperature range -40° C to +85° C
• Hysteresis on all inputs
CLK1
CLK2
CLK3
IN
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
IDT™ / ICS™
BUFFER/CLOCK DRIVER 1
MK3807-01 REV D 060407
MK3807-01
BUFFER/CLOCK DRIVER FAN OUT BUFFER
Pin Assignment
1IN
GND CLK10
VDD GND
CLK2
GND
CLK3
VDD
CLK4 CLK6
GND
2
3CLK1
4
5
7
8
9
10
20 pin SOIC, SSOP, TSSOP
Pin Descriptions
Pin
Number
1 IN Input Clock input.
2 GND Power Connect to ground.
3 CLK1 Output Clock output.
4 VDD Power Connect to +3.3 V.
5 CLK2 Output Clock output.
6 GND Power Connect to ground.
7 CLK3 Output Clock output.
8 VDD Power Connect to +3.3 V.
9 CLK4 Output Clock output.
10 GND Power Connect to ground.
11 CLK5 Output Clock output.
12 CLK6 Output Clock output.
13 GND Power Connect to ground.
14 CLK7 Output Clock output.
15 VDD Power Connect to +3.3 V.
16 CLK8 Output Clock output.
17 GND Power Connect to ground.
18 CLK9 Output Clock output.
19 CLK10 Output Clock output.
20 VDD Power Connect to +3.3 V.
Pin
Name
20
19
18 CLK9
17
16
156
14
13
12
11
VDD
CLK8
VDD
CLK7
GND
CLK5
Pin
Type
Pin Description
IDT™ / ICS™
BUFFER/CLOCK DRIVER 2
MK3807-01 REV D 060407
MK3807-01
BUFFER/CLOCK DRIVER FAN OUT BUFFER
External Components
The MK3807-01 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01µF must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitors
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ω resistor in series with the clock
line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20Ω.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitors should be mounted on
the component side of the board as close to the VDD pins
as possible. No vias should be used between the
decoupling capacitors and VDD pins. The PCB trace to VDD
pin should be kept as short as possible, as should the PCB
trace to the ground via.
2) To minimize EMI, the 33Ω series termination resistor, (if
needed) should be placed close to the clock output.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3807-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item Rating
Supply Voltage, VDD 7 V
All Inputs and Outputs -0.5 V to VDD+0.5 V
Ambient Operating Temperature -40 to +85°C
Storage Temperature -65 to +150°C
Junction Temperature 125°C
Soldering Temperature 260°C
Recommended Operation Conditions
Parameter Min. Typ. Max. Units
Ambient Operating Temperature -40 +85 °C
Power Supply Voltage (measured in respect to GND) +3.135 +3.3 +3.465 V
IDT™ / ICS™
BUFFER/CLOCK DRIVER 3
MK3807-01 REV D 060407