Integrated Device Technology Inc IDT7M1024S30GB, IDT7M1024S25GB, IDT7M1024S25G, IDT7M1024S20G Datasheet

Integrated Device Technology, Inc.

4K x 36 BiCMOS
SYNCHRONOUS DUAL-PORT
STATIC RAM MODULE

IDT7M1024

FEATURES:

• High-density 4K x 36 Synchronous Dual-Port SRAM
module

• Architecture based on Dual-Port RAM cells
— Allows full simultaneous access from both ports

• Synchronous operation
— 4ns set-up to clock, 1ns hold on all control, data, and
address inputs
— Data input, address, and control registers
— Fast 20ns clock to data out
— Self-timed write allows fast write cycle

• Clock enable feature

• Single 5V (±10%) power supply

• Multiple GND pins and decoupling capacitors for maxi­mum noise immunity

• Inputs/outputs directly TTL-compatible

DESCRIPTION:

The IDT7M1024 is a 4K x 36 bit high-speed synchronous

Dual-Port Static RAM module constructed on a co-fired ce-

FUNCTIONAL BLOCK DIAGRAM

ramic substrate using four IDT7099 (4K x 9) Dual-Port RAMs.
The IDT7M1024 module is designed to be used as a stand­alone 36-bit Dual-Port Static RAM.

The IDT7M1024 provides a true synchronous Dual-Port
Static RAM interface. Registered inputs provide very short
set-up and hold times on address, data, and all critical control
inputs. All internal registers are clocked on the rising edge of
the clock signal. An asynchronous output enable is provided
to ease asynchronous bus interfacing.

The internal write pulse width is independent of the HIGH
and LOW periods of the clock. This allows the shortest
possible realized cycle times. Clock enable inputs are pro­vided to stall the operation of the address and data input
registers without introducing clock skew for very fast inter­leaved memory applications.

The data inputs are gated to control on-chip noise in bussed
applications. The user must guarantee that the R/W pins are
LOW for at least one clock cycle before any write is attempted.
A HIGH on the CE input for one clock cycle will power down the
internal circuitry to reduce static power consumption.

The IDT7M1024 module is packaged in a 142-lead ceramic

L_

CLKEN

L_

CE

L_

OE

L_A0 – 11

L_I/O0 – 8

L_ R/

W

L_I/O9 – 17

L_ R/

W

L_

CE

L_

OE

L_I/O18 – 26

L_ R/

W

L_

CLKEN

L_I/O27 – 35

R_CLKL_CLK
R_

CLKEN
CE

L

OE

L

W

0

W

1

CE

H

OE

H

W

2

CLKEN

L

H

L
L
L

IDT7099

4K x 9

0

IDT7099

4K x 9

1
H
H

IDT7099

4K x 9

2

H

IDT7099

4K x 9

R_
R_

R_A0 – 11
R_I/O0 – 8

R_ R/

R_I/O9 – 17

R_ R/
R_
R_

R_I/O18 – 26

R_ R/
R_

R_I/O27 – 35

L_ R/

W

3

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

R_ R/

W

3

2809 drw 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES MARCH 1996

1996 Integrated Device Technology, Inc. DSC-2809/6

7.4 1

IDT7M1024
4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES

PGA (Pin Grid Array).

All IDT military modules are constructed with semiconduc­tor components manufactured in compliance with the latest
revision of MIL-STD-883, Class B making them ideally suited
to applications demanding the highest level of performance
and reliability.

PIN CONFIGURATION

12345678910111213

A GND L_I/O3 L_I/O2 GND L_I/O1 L_I/O0 GND R_I/O0 R_I/O1 GND R_I/O2 R_I/O3 GND

B L_I/O4 L_I/O5 L_I/O6 L_A2 L_A1 L_A0 L_CLK R_A0 R_A1 R_A2 R_I/O6 R_I/O5 R_I/O4

C L_I/O8 VCC L_I/O7 GND

D L_I/O9 L_I/O10 L_I/O11 L_A3

E L_I/O12 L_CE LL_CE H L_A4 R_A5 R_CE HR_CE L R_I/O12

F L_I/O13 L_OE LL_OE H L_A5 R_A6 R_OE HR_OE L R_I/O13

G GND L_R/W0 L_R/W1 GND GND R_R/W1 R_R/W0 GND

H L_I/O14 L_R/W2 L_R/W3 L_A6 R_A7 R_R/W3 R_R/W2 R_I/O14

J L_I/O15 L_I/O16 L_I/O17 L_A7 R_A8 R_I/O17 R_I/O16 R_I/O15

K L_I/O20 L_I/O19 L_I/O18 G N D L_A10 L_A11 GND R_A11 R_A10 GND R_I/O18 R_I/O19 R_I/O20

L L_I/O21 VCC L_I/O22 L_A8 L_A9 L_I/O31 R_I/O35 R_I/O34 R_I/O30 R_A9 R_I/O22 VCC R_I/O21

M L_I/O23 L_I/O24 L_I/O25 L_I/O29 L_I/O30 L_I/O32 L_I/O35 R_I/O33 R_I/O31 R_I/O29 R_I/O25 R_I/O24 R_I/O23

N GND L_I/O26 L_I/O27 L_I/O28 GND L_I/O33 L_I/O34 R_I/O32

L_

CLKEN

GND

LL_

CLKEN

R_CLK

H

R_

CLKEN

GND

HR_

CLKEN

R_A3 R_A4 R_I/O11 R_I/O10 R_I/O9

GND

GND R_I/O7 VCC R_I/O8

L

R_I/O28 R_I/O27 R_I/O26 G N D

2809 drw 02

PIN NAMES

Left Port Right Port Names

L_R/W 0-3 R_R/W 0-3 Byte Read/Write Enables

L_OE L, H R_OE L, H Word Output Enables

L_CE L, H R_CE L, H Word Chip Enables

L_

CLKEN

L, H R_
L_CLK R_CLK Clock Inputs
L_A 0-11 R_A 0-11 Address Inputs
L_I/O 0-35 R_I/O 0-35 Data Input/Outputs

VCC Power

GND Ground

CLKEN

L, H Word Clock Enables

2809 tbl 01

7.4 2

IDT7M1024
4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

V

TERM

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V

with Respect to

GND

(3)

VTERM

T

Terminal Voltage –0.5 to VCC –0.5 to VCC V

A Operating 0 to +70 –55 to +125 °C

Temperature

BIAS Temperature –55 to +125 –65 to +135 °C

T

Under Bias

STG Storage –55 to +125 –65 to +150 °C

T

Temperature

OUT DC Output Current 50 50 mA

I

NOTES: 2809 tbl 02

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

2. Inputs and Vcc terminals only.

CAPACITANCE (TA = +25°C, F = 1.0MHZ)

Symbol Parameter

CIN Input Capacitance VIN = 0V 50 pF

OUT Output Capacitance VOUT = 0V 15 pF

C

(1)

Condition Max. Unit

2809 tbl 05

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND VCC

Military –55°C to +125°C 0V 5.0V ± 10%

Commercial 0°C to +70°C 0V 5.0V ± 10%

2809 tbl 03

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
VIH Input HIGH Voltage 2.2 — 6.0 V

IL Input LOW Voltage –0.5

V

NOTE: 2809 tbl 04

1. VIL = -3.0V for pulse width less than 20ns.

(1)

— 0.8 V

TRUTH TABLES

TRUTH TABLE I: READ/WRITE CONTROL

Inputs

Synchronous Asynchronous Outputs

Clk

u
u
u
u
u

CE

CE

R/

W

W

OE

OE

h h X High-Z Deselected, Power Down, Data I/O Disabled
h l X DATAIN Deselected, Power Down, Data Input Enabled

l l X DATAIN Write
l h L DATAOUT Read
l h H High-Z Data I/O Disabled

(1)

I/O0-35 Mode

2809 tbl 06

TRUTH TABLE II:
CLOCK ENABLE FUNCTION TABLE

Inputs Register Inputs Register Outputs

Operating Mode Clk

Load “1”
Load “0”

Hold (do nothing)

NOTE: 2809 tbl 07

1. H = HIGH voltage level steady state, h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, L =LOW voltage level steady state
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition, X = Don't care, N/C = No change

u
u
u

X H X X N/C N/C

(1)

CLKEN

CLKEN

ADDR DATAIN ADDR DATAOUT

lhhHH
lllLL

h X X N/C N/C

7.4 3