Integrated Device Technology Inc IDT7133SA20F, IDT7133SA20G, IDT7133SA20J, IDT7133SA20PF, IDT7133SA25F Datasheet

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Integrated Device Technology, Inc.
HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS
IDT7133SA/LA IDT7143SA/LA
• High-speed access — Military: 25/35/45/55/70/90ns (max.) — Commercial: 20/25/35/45/55/70/90ns (max.)
• Low-power operation — IDT7133/43SA
Active: 500 mW (typ.) Standby: 5mW (typ.)
— IDT7133/43LA
Active: 500mW (typ.) Standby: 1mW (typ.)
• Versatile control for write: separate write control for lower and upper byte of each port
• MASTER IDT7133 easily expands data bus width to 32 bits or more using SLAVE IDT7143
• On-chip port arbitration logic (IDT7133 only)
BUSY
output flag on IDT7133;
• Fully asynchronous operation from either port
• Battery backup operation–2V data retention
• TTL-compatible; single 5V (±10%) power supply
• Available in 68-pin ceramic PGA, 68-pin Flatpack, 68-pin PLCC, and 100-pin TQFP
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (–40°C to +85°C) is avail­able, tested to military electrical specifications
BUSY
input on IDT7143
DESCRIPTION:
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs. The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM together with the IDT7143 “SLAVE” Dual-Port in 32-bit-or­more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.
Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asyn­chronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technol­ogy, these devices typically operate on only 500mW of power. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200µW for a 2V battery.
The IDT7133/7143 devices have identical pinouts. Each is packaged in a 68-pin ceramic PGA, a 68-pin flatpack, a 68-pin PLCC, and a 100-pin TQFP. Military grade product is manu­factured in compliance with the latest revision of MIL-STD­883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
(2)
R/
W
LUB
CE
L
(2)
R/
W
LLB
OE
L
I/O8L - I/O15L
I/O0L - I/O7L
(1)
BUSY
L
A10L
A0L
NOTES:
1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor of 270. IDT7143 (SLAVE): BUSY is input.
2. "LB" designates "Lower Byte" and "UB" designates "Upper Byte" for the R/W signals.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ADDRESS
DECODER
CE
L
CONTROL
11
I/O
ARBITRATION
(IDT7133 ONLY)
MEMORY
ARRAY
LOGIC
I/O
CONTROL
ADDRESS DECODER
11
CE
OE
I/O8R - I/O15R I/O0R - I/O7R
A
A0R
R
MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996
©1996 Integrated Device Technology, Inc. DSC-2746/6
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.14 1
R/
CE
R/
R
BUSY
10R
2746 drw 01
(2)
W
RUB
R
(2)
W
RLB
(1)
R
IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
I/O I/O I/O I/O I/O
I/O
(1,2)
INDEX
I/O
9L
10L 11L 12L 13L 14L
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
LUB
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
I/O
1L
I/O
0L
I/O
CC
V
W
R/
LLB
W
R/
L
OE
10L
A
A9LA
98765432168 67 66 65 64 63 62 61
10 11 12 13 14 15 16 17 18 19 20
IDT7133/43
J68-1
&
F68-1
PLCC/FLATPACK
TOP VIEW
(3)
21 22 23 24 25 26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
I/O
GND
RUB
W
R/
RLB
W
R/
R
OE
10R
A
9R
A
8R
A
8L
7L
A
A
6L
60
A
5L
59 58
A
4L
57
A
3L
56
A
2L
A
1L
55 54
A
0L
53
BUSY
L
52
CE
L
51
CE
R
50
BUSY
R
49
A
0R
48
A
1R
47
A
2R
46
A
3R
45
A
4R
44
A
5R
7R
6R
A
A
2746 drw 02
INDEX
N/C N/C N/C N/C
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
GND I/O I/O I/O
V I/O I/O I/O I/O
N/C N/C N/C N/C
LUB
LLB
9L
8L
7L
6L
5L
4L
3L
I/O
I/O
I/O
I/O
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1 2 3 4 5 6 7 8
9 10 11 12
CC
13
0R
14
1R
15
2R
16
CC
17
3R
18
4R
19
5R
20
6R
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
7R
8R
9R
10R
I/O
I/O
I/O
I/O
I/O
11R
I/O
I/O
12R
I/O
I/O
13R
I/O
2L
I/O
14R
I/O
GND
GND
1L
I/O
15R
I/O
L
0L
CC
OE
V
I/O
IDT7133/43
PN100-1
100-PIN
TQFP
TOP VIEW
R
RLB
OE
GND
W
R/
W
R/
N/C
(3)
N/C
R
CE
L
CE
RUB
W
R/
/W
R
N/C
N/C
N/C
N/C
N/C
N/C
10R
A
10L
A
9R
A
9L
8L
7L
6L
A
A
A
A
N/C
75 74
N/C
73
N/C
72
N/C
71
5L
A
70
A
4L
69
A
3L
68
A
2L
67
A
1L
66
A
0L
65
N/C
64
BUSY
GND N/C
BUSY
N/C
0R
A A
1R
A
2R
A
3R
A
4R
N/C N/C N/C N/C
L
R
63 62 61 60 59 58 57 56 55 54 53 52 51
8R
7R
5R
6R
A
A
A
A
2746 drw 03
NOTES:
1. Both V
CC pins must be connected to the supply to ensure reliable operation.
2. Both GND pins must be connected to the supply to ensure reliable operation.
3. This text does not indicate orientation of the actual part-marking.
6.14 2
IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D)
11
10
09
08
07
06
05
04
51
52 49 47 45 43 41 39 37 3553 34
A
8L
5455
A
10L
5657
R/
W
LLB
5859
V
CC
R/
6061
I/O
1L
6263
I/O
3L
6465
I/O
5L
50 48 46 44 42 40 38 36
A
7L
9L
LUB
0L
2L
4L
5L
A
4L
L
A
A
A
OE
W
I/O
I/O
I/O
6L
(1,2)
A
3L
A
1L
A
2L
A
0L
TOP VIEW
L
BUSY
CE
L
IDT7133/43
GU68-1
PGA
CE
BUSY
(3)
R
A
R
A
2R
A
3R
4R
A
5R
32 33
A
8R
30 31
A
10R
28 29
R/
W
RLB
26 27
GND
24 25
I/O
14R
22 23
I/O
12R
A
6R
A
7R
A
9R
OE
R
R/
W
RUB
I/O
15R
I/O
13R
0R
A
A
1R
6667
I/O
7L
I/O
168
2
I/O
I/O
10L
6L
3
9L
4
I/O
I/O
11L
12L
5
6
I/O
I/O
13L
14L
7
8
I/O
9
15L
GND
10
V
CC
I/O
0R
03
02
01
INDEX
I/O
8L
ABCDEFGHJKL
NOTES:
1. Both V
CC pins must be connected to the supply to ensure reliable operation.
2. Both GND pins must be connected to the supply to ensure reliable operation.
3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left Port Right Port Names
L
CE
LUB R/WRUB Upper Byte Read/Write Enable
R/
W
LLB R/WRLB Lower Byte Read/Write Enable
R/
W
L
OE
A
0L – A10L A0R – A10R Address
0L – I/O15L I/O0R – I/O15R Data Input/Output
I/O
BUSY
L
CC Power
V GND Ground
CE
R Chip Enable
OE
R Output Enable
BUSY
R Busy Flag
2746 tbl 01
20 21
I/O
7R
11R
19
I/O
9R
2746 drw 04
I/O
10R
11
12
I/O
I/O
13
1R
14
2R
I/O
I/O
15
3R
16
4R
I/O
I/O
18
5R
I/O
8R
17
I/O
6R
6.14 3
IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Military Unit
(2)
V
TERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V with Respect to GND
A Operating 0 to +70 –55 to +125 °C
T
Temperature
T
BIAS Temperature –55 to +125 –65 to +135 °C
Under Bias
STG Storage –55 to +125 –65 to +150 °C
T
Temperature
(3)
P
T
Power 2.0 2.0 W Dissipation
I
OUT DC Output 50 50 mA
Current
NOTES: 2746 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect reliability.
2. V
TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to + 0.5V.
< 20mA for the period of VTERM > Vcc
CAPACITANCE
(1)
(TA = +25°C, f = 1.0MHZ) TQFP ONLY
Symbol Parameter Conditions
C
IN Input Capacitance VIN = 3dV 9 pF
C
OUT Input/Output VOUT = 3dV 10 pF
Capacitance
NOTES: 2746 tbl 03
1. This parameter is determined by device characterization but is not production tested.
2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
(2)
Max. Unit
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Grade Temperature GND V
CC
Military –55°C to +125°C 0V 5.0V ± 10% Commercial 0°C to +70°C 0V 5.0V ± 10%
2746 tbl 04
RECOMMENDED DC OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
V
CC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V V
IH Input High Voltage 2.2 6.0 V IL Input Low Voltage –0.5
V
NOTES: 2746 tbl 05
1. VIL (min.) = -1.5V for pulse width less than 10ns.
2. V
TERM must not exceed Vcc + 0.5V.
(1)
0.8 V
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
LI| Input Leakage Current
|I
LO| Output Leakage Current
|I V
OL Output Low Voltage (I/O0-I/O15)IOL = 4mA 0.4 0.4 V OL Open Drain Output Low Voltage IOL = 16mA 0.5 0.5 V
V
(
BUSY
)
V
OH Output High Voltage IOH = -4mA 2.4 2.4 V
NOTE: 2746 tbl 06
1. At Vcc < 2.0V, input leakages are undefined.
(1)
VCC = 5.5V, VIN = 0V to VCC —10—5µA
CE
= VIH, VOUT = 0V to VCC —10—5µA
6.14 4
(Either port, VCC = 5.0V ± 10%)
IDT7133SA IDT7133LA IDT7143SA IDT7143LA
IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(3)
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
IDT7133X20
Test IDT7143X20
(2)
Symbol Parameter Condition Version Typ.
I
CC Dynamic Operating
CE
= VIL MIL. S 250 330 240 325 mA
Current Outputs Open L 230 300 220 295 (Both Ports Active) f = f
MAX
COM’L. S 250 310 250 300 240 295
(4)
L 230 280 230 270 210 250
SB1 Standby Current
I
(Both Ports — TTL f = f
CE
L and CER = VIH MIL. S 25 90 25 75 mA
(4)
MAX
L– – 2580 2565
Level Inputs) COM’L. S 25 80 25 80 25 70
L2570 2570 2560
I
SB2 Standby Current
(One Port — TTL Level Inputs) f = f
CE
"A" = VIL and MIL. S 140 230 120 200 mA
CE
"
(5)
B" = VIH MAX
, L 100 190 100 180
(4)
, Active COM’L. S 140 200 140 200 120 180
Port Outputs Open L 120 180 100 170 100 160
SB3 Full Standby Current Both Ports CEL & MIL. S 1 30 1 30 mA
I
(Both Ports — CMOS Level Inputs) V
I
SB4 Full Standby Current
(One Port — All
CE
R > VCC - 0.2V L 0.2 10 0.2 10
IN > VCC - 0.2V or COM’L. S 1 15 1 15 1 15 IN < 0.2V, f = 0
V
CE
"A" < 0.2V and MIL. S 140 220 120 190 mA
CE
"B" > VCC - 0.2V
(5)
L 0.2 5 0.2 4 0.2 4
(6)
CMOS Level Inputs) VIN > VCC - 0.2V or L 120 200 100 170
V
IN < 0.2V COM’L. S 140 190 140 190 120 170
Active Port Outputs Open, f = f
NOTES: 2746 tbl 07
1. Commercial only, 0°C to +70°C temperature range.
2. V
CC = 5V, TA = +25°C for Typ., and are not production tested. ICCDC = 180mA (Typ.)
3. "X" in part numbers indicates power rating (SA or LA).
4. At f = f
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”
of input levels of GND to 3V.
MAX
(4)
L 120 170 120 170 100 150
Max. Typ.
(VCC = 5.0V ± 10%)
(1)
(1)
IDT7133X25 IDT7133X35 IDT7143X25 IDT7143X35
(2)
Max. Typ.
(2)
Max. Unit
6.14 5
IDT7133SA/LA, IDT7143SA/LA HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(3)
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
IDT7133X45 IDT7133X55 IDT7133X70/90
Test IDT7143X45 IDT7143X55 IDT7143X70/90
Symbol Parameter Condition Version Typ.
CC Dynamic Operating
I
CE
= VIL MIL. S 230 320 230 315 230 310 mA
Current Outputs Open L 210 290 210 285 210 280 (Both Ports Active) f = f
MAX
COM’L. S 230 290 230 285 230 280
(4)
L 210 260 210 255 210 250
I
SB1 Standby Current
(Both Ports — TTL f = f
CE
L and CER = VIH MIL. S 25 80 25 80 25 75 mA
(4)
MAX
L2570 2570 2565
Level Inputs) COM’L. S 25 75 25 70 25 70
L2565 2560 2560
I
SB2 Standby Current
(One Port — TTL Level Inputs) f = f
CE
"A" = VIL and MIL. S 120 210 120 210 120 200 mA
CE
"
(5)
B" = VIH MAX
, L 100 190 100 190 100 180
(4)
, Active COM’L. S 120 190 120 180 120 180
Port Outputs Open L 100 170 100 160 100 160
I
SB3 Full Standby Current Both Ports CEL & MIL. S 1 30 1 30 1 30 mA
(Both Ports — CMOS Level Inputs) V
I
SB4 Full Standby Current
(One Port — All
R > VCC - 0.2V L 0.2 10 0.2 10 0.2 10
CE
IN > VCC - 0.2V or COM’L. S 1 15 1 15 1 15
V
IN < 0.2V, f = 0
CE
"A" < 0.2V and MIL. S 120 200 120 200 120 190 mA "B" > VCC - 0.2V
CE
(5)
L 0.2 4 0.2 4 0.2 4
(6)
CMOS Level Inputs) VIN > VCC - 0.2V or L 100 180 100 180 100 170
V
IN < 0.2V COM’L. S 120 180 120 170 120 170
Active Port Outputs Open, f = f
MAX
(4)
L 100 160 100 150 100 150
(2)
Max. Typ.
(VCC = 5.0V ± 10%)
(2)
Max. Typ.
(2)
Max. Unit
NOTES: 2746 tbl 07
1. Commercial only, 0°C to +70°C temperature range.
2. V
CC = 5V, TA = +25°C for Typ., and are not production tested. ICCDC = 180mA (Typ.)
3. "X" in part numbers indicates power rating (SA or LA).
4. At f = f
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions”
of input levels of GND to 3V.
6.14 6
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