Integrated Device Technology Inc IDT7132LA35FB, IDT7132LA35J, IDT7132LA35JB, IDT7132LA35L48B, IDT7132LA35P Datasheet

Integrated Device Technology, Inc.

I/O

Control

Address
Decoder

MEMORY

ARRAY

ARBITRATION

LOGIC

Address
Decoder

I/O

Control

R/

W

L

CE

L

OE

L

BUSY

L

A

10L

A

0L

2692 drw 01

I/O0L- I/O

7L

CE

L

BUSY

R

I/O0R-I/O

7R

A

10R

A

0R

CE

R

(1,2) (1,2)

R/

W

R

CE

R

OE

R

11

11

HIGH-SPEED
2K x 8 DUAL-PORT
STATIC RAM

IDT7132SA/LA
IDT7142SA/LA

FEATURES:

• High-speed access
— Military: 25/35/55/100ns (max.)
— Commercial: 25/35/55/100ns (max.)
— Commercial: 20ns only in PLCC for 7132

• Low-power operation
— IDT7132/42SA

Active: 550mW (typ.)
Standby: 5mW (typ.)

— IDT7132/42LA

Active: 550mW (typ.)
Standby: 1mW (typ.)

• Fully asynchronous operation from either port

• MASTER IDT7132 easily expands data bus width to 16-or-

more bits using SLAVE IDT7142

• On-chip port arbitration logic (IDT7132 only)

•

BUSY

output flag on IDT7132;

• Battery backup operation —2V data retention

• TTL-compatible, single 5V ±10% power supply

• Available in popular hermetic and plastic packages

• Military product compliant to MIL-STD, Class B

• Standard Military Drawing # 5962-87002

• Industrial temperature range (–40°C to +85°C) is available,

tested to miliary electrical specifications

BUSY

input on IDT7142

DESCRIPTION:

The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port
Static RAMs. The IDT7132 is designed to be used as a stand­alone 8-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM
together with the IDT7142 “SLAVE” Dual-Port in 16-bit-or­more word width systems. Using the IDT MASTER/SLAVE
Dual-Port RAM approach in 16-or-more-bit memory system
applications results in full-speed, error-free operation without
the need for additional discrete logic.

Both devices provide two independent ports with separate
control, address, and l/O pins that permit independent, asyn­chronous access for reads or writes to any location in memory.
An automatic power down feature, controlled by CE permits
the on-chip circuitry of each port to enter a very low standby
power mode.

Fabricated using IDT’s CMOS high-performance technol­ogy, these devices typically operate on only 550mW of power.
Low-power (LA) versions offer battery backup data retention
capability, with each Dual-Port typically consuming 200µW
from a 2V battery.

The IDT7132/7142 devices are packaged in a 48-pin
sidebraze or plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and
48-lead flatpacks. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

NOTES:

1. IDT7132 (MASTER):
drain output and requires pullup
resistor of 270Ω.
IDT7142 (SLAVE):

2. Open drain output: requires pullup
resistor of 270Ω.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-2692/8

BUSY

BUSY

is open

is input.

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.02 1

IDT7132SA/LA AND IDT7142SA/LA

IDT7132/42

L48-1

&

F48-1

48-PIN LCC/ FLATPACK

TOP VIEW

(3)

INDEX

65432148 47 46 45 44 43

19 20 21 22 23 25 26 27 28 29 3024

42
41
40
39
38
37
36
35
34
33
32
31

7
8
9
10
11
12
13
14
15
16
17
18

2692 drw 03

GND

CE

R

CE

L

OE

L

A

0L

OE

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

I/O

7R

I/O

3L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

I/O

2L

BUSY

L

R/

W

L

R/

W

R

BUSY

R

V

CC

I/O

6R

I/O

5R

I/O

4R

I/O

3R

I/O

2R

I/O

1R

I/O

0R

I/O

7L

I/O

6L

I/O

5L

I/O

4L

A

10L

A

10R

IDT7132/42

J52-1

52-PIN PLCC

TOP VIEW

(3)

INDEX

N/C

GND

OE

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

N/C
I/O

7R

46
45
44
43
42
41
40
39
38
37
36
35
34

I/O

3L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

I/O

2L

8
9
10
11
12
13
14
15
16
17
18
19
20

474849505152

1

234567

33323130292827262524232221

2692 drw 04

A

10L

V

CC

A

10R

I/O

6R

A

0L

OE

L

N/C

CE

L

CE

R

N/C

BUSY

L

R/

W

L

R/

W

R

BUSY

R

I/O

5R

I/O

4R

I/O

3R

I/O

2R

I/O

1R

I/O

0R

I/O

7L

I/O

6L

I/O

5L

I/O

4L

HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

CE

L

R/

BUSY

A

OE

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

148

W

L

2

L

3

10L

4

L

5

A

0L

6

A

1L

7

A

2L

8

A

3L

9

A

4L

10

A

5L

11

A

6L

12

A

7L

13

A

8L

14

A

9L

15

0L

16

1L

17

2L

18

3L

19

4L

20

5L

21

6L

22

7L

23
24

(1,2)

IDT7132/

7142

P48-1

&

C48-2

DIP

TOP

(3)

VIEW

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

V

CC

CE

R

R/

W

R

BUSY

R

A

10R

OE

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

I/O

7R

I/O

6R

I/O

5R

I/O

4R

I/O

3R

I/O

2R

I/O

1R

I/O

0R

2692 drw 02

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

TERM

V

Terminal Voltage -0.5 to +7.0 -0.5 to +7.0 V
with Respect to
GND

T

A Operating 0 to +70 -55 to +125 °C

Temperature

T

BIAS Temperature -55 to +125 -65 to +135 °C

Under Bias

T

STG Storage -55 to +125 -65 to +150 °C

Temperature

I

OUT DC Output 50 50 mA

Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

2. V

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or

10ns maximum, and is limited to

0.5V.

Grade Temperature GND V

Military -55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%

Ambient

< 20mA for the period of VTERM > Vcc +

CC

2692 tbl 01

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

RECOMMENDED
DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V

V

IH Input High Voltage 2.2 — 6.0

V

IL Input Low Voltage -0.5 — 0.8 V

NOTES:

1. V

IL (min.) = -1.5V for pulse width less than 10ns.
TERM must not exceed Vcc + 0.5V.

2692 tbl 02

2. V

6.02 2

(1)

(2)

V

2692 tbl 03

IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

7132X20

(2)

7132X25
7142X25

(1,6)

(VCC = 5.0V ± 10%)

(3)

7132X35 7132X55 7132X100

(3)

7142X35 7142X55 7142X100

Symbol Parameter Test Conditions Version Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit

I

CC Dynamic Operating

CE

L and CER = VIL, MIL. SA — — 110 280 80 230 65 190 65 190 mA

Current (Both Ports Outputs open, LA — — 110 220 80 170 65 140 65 140
Active) f = f

MAX

(4)

COM'L. SA 110 250 110 220 80 165 65 155 65 155

LA 110 200 110 170 80 120 65 110 65 110

SB1 Standby Current

I

(Both Ports - TTL f = f

CE

L and CER = VIH, MIL. SA — — 30 80 25 80 20 65 20 65 mA

(4)

MAX

LA — — 30 60 25 60 20 45 20 45

Level Inputs) COM'L. SA 30 65 30 65 25 65 20 65 20 55

LA 30 45 30 45 25 45 20 35 20 35

I

SB2 Standby Current

(One Port - TTL

CE

"A" = VIL and MIL. SA — — 65 160 50 150 40 125 40 125 mA

CE

"B" = VIH

(7)

LA — — 65 125 50 115 40 90 40 90

Level Inputs) Active Port Outputs COM'L. SA 65 165 65 150 50 125 40 110 40 110

MAX

(4)

(5)

(7)

LA 65 125 65 115 50 90 40 75 40 75

LA 0.2 5 0.2 5 0.2 4 0.2 4 0.2 4

LA — — 60 115 45 105 40 85 40 80

SB3 Full Standby Current

I

(Both Ports - All
CMOS Level Inputs V

I

SB4 Full Standby Current

(One Port - All
CMOS Level Inputs) V

Open, f = f

CE

L and MIL. SA — — 1.0 30 1.0 30 1.0 30 1.0 30 mA

CE

R > VCC -0.2V, LA — — 0.2 10 0.2 10 0.2 10 0.2 10

IN > VCC -0.2V or COM'L. SA 1.0 15 1.0 15 1.0 15 1.0 15 1.0 15

V

IN < 0.2V,f = 0

CE

"A" < 0.2V and MIL. SA — — 60 155 45 145 40 110 40 110 mA

CE

"B" > VCC -0.2V

IN > VCC -0.2V or COM'L. SA 60 155 60 145 45 110 40 100 40 95

V

IN < 0.2V, LA 60 115 60 105 45 85 40 70 40 70

Active Port Outputs
Open, f = f

NOTES: 2689 tbl 04

1. 'X' in part numbers indicates power rating (SA or LA).

2. Com'l Only, 0°C to +70°C temperature range. PLCC package only.

3. Not available in DIP packages.

4. At f = f

5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

6. Vcc = 5V, T

7. Port "A" may be either left or right port. Port "B" is opposite from port "A".

Max, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS”

of input levels of GND to 3V.

A=+25°C for Typ. and is not production tested. Vcc DC = 100mA (Typ.)

MAX

(4)

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)

7132SA 7132LA
7142SA 7142LA

Symbol Parameter Test Conditions Min. Max. Max. Max. Unit

Ll| Input Leakage VCC = 5.5V, — 10 — 5 µA

|l

|lLO| Output Leakage VCC = 5.5V, — 10 — 5 µA

V

OL Output Low Voltage lOL = 4mA — 0.4 — 0.4 V

V

OL Open Drain Output lOL = 16mA — 0.5 — 0.5 V

V

OH Output High Voltage lOH = -4mA 2.4 — 2.4 — V

NOTE: 2689 tbl 05

1. At Vcc < 2.0V leakages are undefined.

(1)

Current

(1)

Current

(l/O0-l/O

Low Voltage (

7) lOL= 16mA

BUSY, INT

)

Supply Current V

VIN = 0V to VCCIN = GND to VCC

CE

= VIH, VOUT = 0V to VCC

IN > VCC -0.2V or < 0.2V

C

6.02 3

IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS (LA Version Only)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

DR VCC for Data Retention 2.0 — — V

I

CCDR Data Retention Current VCC = 2.0V,

IN ≥ VCC -0.2V or VIN ≤ 0.2V Com’l. — 100 1500 µA

V

(3)

t

CDR Chip Deselect to Data 0 — — ns

CE

≥ VCC -0.2V Mil. — 100 4000 µA

Retention Time

(3)

t

R Operation Recovery tRC ——ns

Time

NOTES:

CC = 2V, TA = +25°C, and is not production tested.

1. V

RC = Read Cycle Time

2. t

3. This parameter is guaranteed but not production tested.

lDT7132LA/IDT7142LA

(2)

2692 tbl 06

DATA RETENTION WAVEFORM

DATA RETENTION MODE

V

CC

CE

4.5V 4.5V
t

CDR

V

IH

DATA

V

DR

V

OUT

775Ω

≥

DR

2.0V
t

R

V

IH

2692 drw 05

5V

1250Ω

30pF*

100pF for 55 and 100ns versions

AC TEST CONDITIONS

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

DATA

OUT

775Ω

GND TO 3.0V

5ns

1.5V

1.5V

Figures 1, 2, and 3

2692 tbl 07

5V

1250Ω

5pF*

BUSY

Figure 1. AC Output Test Load

5V

270Ω

or

INT

30pF*

100pF for 55 and 100ns versions

Figure 3.

AC Output Test Load

BUSYBUSY

BUSY

BUSYBUSY

and

INTINT

INT

INTINT

2692 drw 06

Figure 2. Output Test Load

HZ, tLZ, tWZ, and tOW)

(for t

* Including scope and jig

6.02 4