Integrated Device Technology Inc IDT7130LA100C, IDT7130LA100CB, IDT7130LA100F, IDT7130LA20P, IDT7130LA20PB Datasheet

Integrated Device Technology, Inc.

HIGH-SPEED
1K x 8 DUAL-PORT
STATIC RAM

IDT7130SA/LA
IDT7140SA/LA

FEATURES

• High-speed access
—Military: 25/35/55/100ns (max.)
—Commercial: 25/35/55/100ns (max.)
—Commercial: 20ns 7130 in PLCC and TQFP

• Low-power operation
—IDT7130/IDT7140SA

—Active: 550mW (typ.)
—Standby: 5mW (typ.)

—IDT7130/IDT7140LA

—Active: 550mW (typ.)
—Standby: 1mW (typ.)

• MASTER IDT7130 easily expands data bus width to
16-or-more-bits using SLAVE IDT7140

• On-chip port arbitration logic (IDT7130 Only)

•

BUSY

output flag on IDT7130;

BUSY

input on IDT7140

• Interrupt flags for port-to-port communication

• Fully asynchronous operation from either port

• Battery backup operation–2V data retention (LA only)

• TTL-compatible, single 5V ±10% power supply

• Military product compliant to MIL-STD-883, Class B

• Standard Military Drawing #5962-86875

• Industrial temperature range (–40°C to +85°C) is avail­able, tested to military electrical specifications

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

DESCRIPTION

The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port
Static RAMs. The IDT7130 is designed to be used as a
stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual­Port RAM together with the IDT7140 "SLAVE" Dual-Port in
16-bit-or-more word width systems. Using the IDT MAS­TER/SLAVE Dual-Port RAM approach in 16-or-more-bit
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.

Both devices provide two independent ports with sepa­rate control, address, and I/O pins that permit independent
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by

CE

, permits the on chip circuitry of each port to enter a very

low standby power mode.

Fabricated using IDT's CMOS high-performance tech­nology, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consum­ing 200µW from a 2V battery.

The IDT7130/IDT7140 devices are packaged in 48-pin
sidebraze or plastic DIPs, LCCs, or flatpacks, 52-pin PLCC,
and 64-pin TQFP and STQFP. Military grade product is
manufactured in compliance with the latest revision of MIL­STD-883, Class B, making it ideally suited to military tem­perature applications demanding the highest level of per­formance and reliability.

FUNCTIONAL BLOCK DIAGRAM

6.01 1

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-2689/7

I/O

Control

Address
Decoder

MEMORY

ARRAY

ARBITRATION

and

INTERRUPT

LOGIC

Address
Decoder

I/O

Control

R/

W

L

CE

L

OE

L

BUSY

L

A9L

A0L

2689 drw 01

I/O0L- I/O7L

CE

L

OE

L

R/

W

L

INT

L

BUSY

R

I/O0R-I/O7R

A9R
A0R

INT

R

CE

R

OE

R

(2)

(1,2) (1,2)

(2)

R/

W

R

CE

R

OE

R

R/

W

R

10

10

NOTES:

1. IDT7130 (MASTER):

BUSY

is open
drain output and requires pullup
resistor of 270Ω.
IDT7140 (SLAVE):

BUSY

is input.

2. Open drain output: requires pullup
resistor of 270Ω.

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01 2

PIN CONFIGURATIONS

(1,2)

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

INDEX

IDT7130/40

PP64-1 & PN64-1

64-PIN STQFP

64-PIN TQFP
TOP VIEW

(3)

8

9
10
11
12
13
14
15
16

1

2

3

4

5

6

7

46
45
44
43
42
41
40
39
38
37
36
35
34

47

48

33

I/O

6R

N/C

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

I/O

7R

OE

R

N/C
N/C

I/O

2L

A

0L

OE

L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

N/C

N/C

2689 drw 05

17

18

19

20

32

31

30

29

28

27

26

25

24

23

22

21

49

50

51

52

63

62

61

605958

57

56

55

54

53

64

N/C

N/C

BUSY

R

INT

R

N/C

N/C

N/C

N/C

GND

N/C

N/C

GND

N/C

CE

L

R/

W

R

CE

R

V

CC

V

CC

R/

W

L

BUSY

L

INT

L

I/O

3L

I/O

4L

I/O

5L

I/O

6L

I/O

7L

I/O

0R

I/O

1R

I/O

2R

I/O

3R

I/O

4R

I/O

5R

IDT7130/40

L48-1

&

F48-1

48-PIN LCC/ FLATPACK

TOP VIEW

(3)

INDEX

65432148 47 46 45 44 43

19 20 21 22 23 25 26 27 28 29 3024

42
41
40
39
38
37
36
35
34
33
32
31

7
8
9
10
11
12
13
14
15
16
17
18

2689 drw 03

GND

CE

R

CE

L

OE

L

A0L

OE

R

A0R

A1R
A2R

A3R

A4R
A5R

A6R
A7R
A8R

A9R

I/O7R

I/O3L

A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L

A9L
I/O0L
I/O1L
I/O2L

INT

L

BUSY

L

R/

W

L

R/

W

R

BUSY

R

INT

R

VCC

I/O6R

I/O5R

I/O4R

I/O3R

I/O2R

I/O1R

I/O0R

I/O7L

I/O6L

I/O5L

I/O4L

IDT7130/40

J52-1

52-PIN PLCC
TOP VIEW

(3)

INDEX

N/C

GND

N/C

N/C

CE

R

CE

L

OE

L

A

0L

OE

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

N/C
I/O

7R

46
45
44
43
42
41
40
39
38
37
36
35
34

I/O

3L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

I/O

2L

8
9
10
11
12
13
14
15
16
17
18
19
20

474849505152

1

234567

33323130292827262524232221

2689 drw 04

INTLBUSY

L

R/

W

L

R/

W

R

BUSYRINT

R

I/O

6R

V

CC

I/O

5R

I/O

4R

I/O

3R

I/O

2R

I/O

1R

I/O

0R

I/O

7L

I/O

6L

I/O

5L

I/O

4L

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

148

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

IDT7130/
IDT7140

P48-1

&

C48-2

DIP

TOP

VIEW

(3)

2689 drw 02

GND

I/O

6R

I/O

5R

I/O

4R

I/O

3R

I/O

2R

I/O

1R

I/O

0R

I/O

7L

I/O

6L

I/O

5L

I/O

4L

CE

R

CE

L

OE

L

A

0L

INT

L

BUSY

L

R/

W

L

R/

W

R

BUSY

R

INT

R

V

CC

OE

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

I/O

7R

I/O

3L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

I/O

2L

6.01 3

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

7130SA 7130LA
7140SA 7140LA

Symbol Parameter Test Conditions Min. Max. Max. Max. Unit

|l

Ll| Input Leakage VCC = 5.5V, — 10 — 5 µA

Current

(1)

VIN = 0V to VCCIN = GND to VCC

|lLO| Output Leakage VCC = 5.5V, — 10 — 5 µA

Current

(1)

CE

= VIH, VOUT = 0V to VCC

C

V

OL Output Low Voltage lOL = 4mA — 0.4 — 0.4 V

(l/O0-l/O

7) lOL= 16mA

V

OL Open Drain Output lOL = 16mA — 0.5 — 0.5 V

Low Voltage (

BUSY, INT

)

V

OH Output High Voltage lOH = -4mA 2.4 — 2.4 — V

Symbol Parameter Conditions

(2)

Max. Unit

C

IN Input Capacitance VIN = 3dV 9 pF

C

OUT Output Capacitance VIN = 3dV 10 pF

2689 tbl 02

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

V

TERM

(2)

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND

T

A Operating 0 to +70 –55 to +125 °C

Temperature

T

BIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

T

STG Storage –55 to +125 –65 to +150 °C

Temperature

I

OUT DC Output 50 50 mA

Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time
or 10ns maximum, and is limited to

< 20mA for the period of VTERM > Vcc

+ 0.5V.

2689 tbl 01

RECOMMENDED
DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V
V

IH Input High Voltage 2.2 — 6.0

(2)

V

V

IL Input Low Voltage –0.5 — 0.8 V

NOTES:

1. V

IL (min.) > -1.5V for pulse width less than 10ns.

2. V

TERM must not exceed Vcc + 0.5V.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND V

CC

Military –55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%

2689 tbl 03

(1)

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(VCC = 5.0V ± 10%)

NOTES:

1. This parameter is determined by device characterization but is not
production tested.

2. 3dv references the interpolated capacitance when the input and

output signals switch from 0V to 3V or from 3V to 0V.

3. 11pF max. for other packages.

2689 tbl 05

CAPACITANCE

(1)

(TA = +25°C, f = 1.0MHz) TQFP ONLY

(3)

NOTE: 2689 tbl 04

1. At Vcc < 2.0V leakages are undefined.

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01 4

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(1,6)

(VCC = 5.0V ± 10%)

7130X20

(2)

7130X25

(3)

7130X35 7130X55 7130X100

7140X25

(3)

7140X35 7140X55 7140X100

Symbol Parameter Test Conditions Version Typ. Max. Typ. Max. Typ. Max. Typ.Max. Typ. Max. Unit

I

CC Dynamic Operating

CE

L and CER = VIL, MIL. SA — — 110 280 110 230 110 190 110 190 mA

Current (Both Ports Outputs open, LA — — 110 220 110 170 110 140 110 140
Active) f = f

MAX

(4)

COM'L. SA 110 250 110 220 110 165 110 155 110 155

LA 110 200 110 170 110 120 110 110 110 110

I

SB1 Standby Current

CE

L and CER = VIH, MIL. SA — — 30 80 25 80 20 65 20 65 mA

(Both Ports - TTL f = f

MAX

(4)

LA — — 30 60 25 60 20 45 20 45

Level Inputs) COM'L. SA 30 65 30 65 25 65 20 65 20 55

LA 30 45 30 45 25 45 20 35 20 35

I

SB2 Standby Current

CE

"A" = VIL and MIL. SA — — 65 160 50 150 40 125 40 125 mA

(One Port - TTL

CE

"B" = VIH

(7)

LA — — 65 125 50 115 40 90 40 90

Level Inputs) Active Port Outputs COM'L. SA 65 165 65 150 50 125 40 110 40 110

Open, f = f

MAX

(4)

LA 65 125 65 115 50 90 40 75 40 75

I

SB3 Full Standby Current

CE

L and MIL. SA — — 1.0 30 1.0 30 1.0 30 1.0 30 mA

(Both Ports - All

CE

R > VCC -0.2V, LA — — 0.2 10 0.2 10 0.2 10 0.2 10

CMOS Level Inputs V

IN > VCC -0.2V or COM'L. SA 1.0 15 1.0 15 1.0 15 1.0 15 1.0 15

V

IN < 0.2V,f = 0

(5)

LA 0.2 5 0.2 5 0.2 4 0.2 4 0.2 4

I

SB4 Full Standby Current

CE

"A" < 0.2V and MIL. SA — — 60 155 45 145 40 110 40 110 mA

(One Port - All

CE

"B" > VCC -0.2V

(7)

LA — — 60 115 45 105 40 85 40 80

CMOS Level Inputs) V

IN > VCC -0.2V or COM'L. SA 60 155 60 145 45 110 40 100 40 95

V

IN < 0.2V, LA 60 115 60 105 45 85 40 70 40 70

Active Port Outputs
Open, f = f

MAX

(4)

NOTES: 2689 tbl 06

1. 'X' in part numbers indicates power rating (SA or LA).

2. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP packages.

3. Not available in DIP packages.

4. At f = f

Max, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS”

of input levels of GND to 3V.

5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

6. Vcc = 5V, T

A=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ.)

7. Port "A" may be either left or right port. Port "B" is opposite from port "A".

Symbol Parameter Min. Typ.

(1)

Max. Unit

V

DR VCC for Data Retention 2.0 — — V

I

CCDR Data Retention Current — 100 4000 µA

— 100 1500 µA

t

CDR Chip Deselect to Data 0 — — ns

Retention Time

t

R Operation Recovery tRC ——ns

Time

DATA RETENTION CHARACTERISTICS (LA Version Only)

lDT7130LA/IDT7140LA

Mil.
Com’l.

VCC = 2.0V,

CE

> VCC -0.2V

V

IN > VCC -0.2V or VIN < 0.2V

(3)

(3)

Test Conditions

2689 tbl 07

(2)

NOTES:

1. V

CC = 2V, TA = +25°C, and is not production tested.

2. t

RC = Read Cycle Time

3. This parameter is guaranteed but not production tested.

6.01 5

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

5V

1250Ω

(*100pF for 55 and
100ns versions)

30pF*

775Ω

DATA

OUT

5V

1250Ω

775Ω

5pF*

DATA

OUT

2689 drw 07

5V

270Ω

30pF*

BUSY

or

INT

*

100pF for 55 and 100ns versions

DATA RETENTION WAVEFORM

AC TEST CONDITIONS

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V

5ns

1.5V

1.5V

Figures 1, 2, and 3

2689 tbl 08

V

CC

CE

4.5V 4.5V

DATA RETENTION MODE

t

CDR

t

R

V

IH

V

IH

V

DR

V

DR

2.0V

2692 drw 06

≥

Figure 3.

BUSYBUSY

BUSYBUSY

BUSY

and

INTINT

INTINT

INT

AC Output Test Load

Figure 1. Output Test Load

Figure 2. Output Test Load

(for t

HZ, tLZ, tWZ, and tOW)

* including scope and jig