IDT IDT7130SA, IDT7130LA, IDT7140SA, IDT7140LA User Manual

查询IDT7130LA100C供应商

HIGH-SPEED
1K x 8 DUAL-PORT
STATIC RAM

Integrated Device Technology, Inc.

FEATURES

• High-speed access
—Military: 25/35/55/100ns (max.)
—Commercial: 25/35/55/100ns (max.)
—Commercial: 20ns 7130 in PLCC and TQFP

• Low-power operation
—IDT7130/IDT7140SA

—Active: 550mW (typ.)
—Standby: 5mW (typ.)

—IDT7130/IDT7140LA

—Active: 550mW (typ.)
—Standby: 1mW (typ.)

• MASTER IDT7130 easily expands data bus width to
16-or-more-bits using SLAVE IDT7140

• On-chip port arbitration logic (IDT7130 Only)

•

BUSY

output flag on IDT7130;

• Interrupt flags for port-to-port communication

• Fully asynchronous operation from either port

• Battery backup operation–2V data retention (LA only)

• TTL-compatible, single 5V ±10% power supply

• Military product compliant to MIL-STD-883, Class B

• Standard Military Drawing #5962-86875

• Industrial temperature range (–40°C to +85°C) is avail­able, tested to military electrical specifications

BUSY

input on IDT7140

IDT7130SA/LA
IDT7140SA/LA

DESCRIPTION

The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port
Static RAMs. The IDT7130 is designed to be used as a
stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual­Port RAM together with the IDT7140 "SLAVE" Dual-Port in
16-bit-or-more word width systems. Using the IDT MAS­TER/SLAVE Dual-Port RAM approach in 16-or-more-bit
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.

Both devices provide two independent ports with sepa­rate control, address, and I/O pins that permit independent
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by

CE

, permits the on chip circuitry of each port to enter a very

low standby power mode.

Fabricated using IDT's CMOS high-performance tech­nology, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consum­ing 200µW from a 2V battery.

The IDT7130/IDT7140 devices are packaged in 48-pin
sidebraze or plastic DIPs, LCCs, or flatpacks, 52-pin PLCC,
and 64-pin TQFP and STQFP. Military grade product is
manufactured in compliance with the latest revision of MIL­STD-883, Class B, making it ideally suited to military tem­perature applications demanding the highest level of per­formance and reliability.

FUNCTIONAL BLOCK DIAGRAM

OE

CE

R/

I/O0R-I/O7R

BUSY

INT

2689 drw 01

W

A9R
A0R

R

R

R

R

(2)

R

OE

L

CE

L

R/

W

L

I/O0L- I/O7L

(1,2) (1,2)

BUSY

L

A9L

A0L

NOTES:

1. IDT7130 (MASTER):
drain output and requires pullup
resistor of 270Ω.
IDT7140 (SLAVE):

2. Open drain output: requires pullup
resistor of 270Ω.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

BUSY

BUSY

is open

is input.

INT

(2)

L

Address
Decoder

R/

CE
OE

L
L

W

L

10

I/O

Control

MEMORY

ARRAY

ARBITRATION

and

INTERRUPT

LOGIC

I/O

Control

Address
Decoder

10

CE

R

OE

R

R/

W

R

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-2689/7

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.01 1

IDT7130SA/LA AND IDT7140SA/LA

INDEX

IDT7130/40

PP64-1 & PN64-1

64-PIN STQFP

64-PIN TQFP
TOP VIEW

(3)

8

9
10
11
12
13
14
15
16

1

2

3

4

5

6

7

46
45
44
43
42
41
40
39
38
37
36
35
34

47

48

33

I/O

6R

N/C

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

I/O

7R

OE

R

N/C
N/C

I/O

2L

A

0L

OE

L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

N/C

N/C

2689 drw 05

17

18

19

20

32

31

30

29

28

27

26

25

24

23

22

21

49

50

51

52

63

62

61

605958

57

56

55

54

53

64

N/C

N/C

BUSY

R

INT

R

N/C

N/C

N/C

N/C

GND

N/C

N/C

GND

N/C

CE

L

R/

W

R

CE

R

V

CC

V

CC

R/

W

L

BUSY

L

INT

L

I/O

3L

I/O

4L

I/O

5L

I/O

6L

I/O

7L

I/O

0R

I/O

1R

I/O

2R

I/O

3R

I/O

4R

I/O

5R

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

CE

L

R/

BUSY

INT

OE

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND

148

W

L

2

L

3

L

4

L

5

A

0L

6

A

1L

7

A

2L

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

IDT7130/

IDT7140

P48-1

&

C48-2

DIP

TOP

VIEW

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L
0L
1L
2L
3L
4L
5L
6L
7L

24

(1,2)

(3)

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

V

CC

CE

R

R/

W

R

BUSY

R

INT

R

OE

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

I/O

7R
6R

I/O
I/O

5R

I/O

4R

I/O

3R

I/O

2R

I/O

1R

I/O

0R

2689 drw 02

INDEX

I/O
I/O
I/O
I/O

L

L

0L

A

OE

N/C

8

A

1L

9

A

2L

10

A

3L

11

A

4L

12

A

5L

13

A

6L

14

A

7L

15

A

8L

16

A

9L

17

0L

18

1L

19

2L

20

3L

6L

5L

4L

I/O

I/O

I/O

L

W

INTLBUSY

R/

234567

1

IDT7130/40

J52-1

52-PIN PLCC
TOP VIEW

7L

N/C

I/O

GND

L

CE

0R

I/O

CC

V

(3)

1R

I/O

R

CE

2R

I/O

R

W

R/

3R

I/O

R

BUSYRINT

5R

4R

I/O

I/O

N/C

474849505152

46

OE

45
44
43
42
41
40
39
38
37
36
35
34

33323130292827262524232221

6R

I/O

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

N/C
I/O

7R

2689 drw 04

L

INDEX

L

A0L

OE

INT

W

BUSY

R/

L

CE

L

L

VCC

R

CE

R

W

R/

65432148 47 46 45 44 43

7

A1L
A2L

8

A3L

9
A4L
A5L
A6L
A7L
A8L
A9L

I/O0L
I/O1L
I/O2L

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

10

11

12

13

14

15

16

17

18

19 20 21 22 23 25 26 27 28 29 3024

I/O3L

48-PIN LCC/ FLATPACK

I/O5L

I/O4L

IDT7130/40

L48-1

&

F48-1

TOP VIEW

I/O7L

I/O6L

GND

I/O0R

(3)

I/O1R

I/O2R

R

R

BUSY

INT

I/O4R

I/O3R

R

OE

42
41
40
39
38
37
36
35
34
33
32
31

I/O5R

A0R

A1R
A2R

A3R

A4R
A5R

A6R
A7R
A8R

A9R

I/O7R

I/O6R

2689 drw 03

6.01 2

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

V

TERM

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND

A Operating 0 to +70 –55 to +125 °C

T

Temperature

BIAS Temperature –55 to +125 –65 to +135 °C

T

Under Bias

STG Storage –55 to +125 –65 to +150 °C

T

Temperature

I

OUT DC Output 50 50 mA

RECOMMENDED
DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V
V

IH Input High Voltage 2.2 — 6.0

V

IL Input Low Voltage –0.5 — 0.8 V

NOTES:

1. V

IL (min.) > -1.5V for pulse width less than 10ns.

2. V

TERM must not exceed Vcc + 0.5V.

(1)

(2)

2689 tbl 02

V

Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time
or 10ns maximum, and is limited to
+ 0.5V.

< 20mA for the period of VTERM > Vcc

2689 tbl 01

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND V

Military –55 °C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%

CC

2689 tbl 03

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Test Conditions Min. Max. Max. Max. Unit

Ll| Input Leakage VCC = 5.5V, — 10 — 5 µA

|l

|lLO| Output Leakage VCC = 5.5V, — 10 — 5 µA

OL Output Low Voltage lOL = 4mA — 0.4 — 0.4 V

V

OL Open Drain Output lOL = 16mA — 0.5 — 0.5 V

V

OH Output High Voltage lOH = -4mA 2.4 — 2.4 — V

V

NOTE: 2689 tbl 04

1. At Vcc < 2.0V leakages are undefined.

(1)

Current

(1)

Current

(l/O0-l/O

7) lOL= 16mA

Low Voltage (

BUSY, INT

VIN = 0V to VCCIN = GND to VCC

CE

= VIH, VOUT = 0V to VCC

)

C

(VCC = 5.0V ± 10%)

7130SA 7130LA
7140SA 7140LA

CAPACITANCE

(TA = +25°C, f = 1.0MHz) TQFP ONLY

Symbol Parameter Conditions

C

IN Input Capacitance VIN = 3dV 9 pF
OUT Output Capacitance VIN = 3dV 10 pF

C

NOTES:

1. This parameter is determined by device characterization but is not
production tested.

2. 3dv references the interpolated capacitance when the input and

output signals switch from 0V to 3V or from 3V to 0V.

3. 11pF max. for other packages.

(1)

(3)

(2)

Max. Unit

2689 tbl 05

6.01 3

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

7130X20

(2)

7130X25
7140X25

(1,6)

(VCC = 5.0V ± 10%)

(3)

7130X35 7130X55 7130X100

(3)

7140X35 7140X55 7140X100

Symbol Parameter Test Conditions Version Typ. Max. Typ. Max. Typ. Max. Typ.Max. Typ. Max. Unit

CC Dynamic Operating

I

CE

L and CER = VIL, MIL. SA — — 110 280 110 230 110 190 110 190 mA

Current (Both Ports Outputs open, LA — — 110 220 110 170 110 140 110 140
Active) f = f

MAX

COM'L. SA 110 250 110 220 110 165 110 155 110 155

(4)

LA 110 200 110 170 110 120 110 110 110 110

SB1 Standby Current

I

(Both Ports - TTL f = f

CE

L and CER = VIH, MIL. SA — — 30 80 25 80 20 65 20 65 mA

(4)

MAX

LA — — 30 60 25 60 20 45 20 45

Level Inputs) COM'L. SA 30 65 30 65 25 65 20 65 20 55

LA 30 45 30 45 25 45 20 35 20 35

I

SB2 Standby Current

(One Port - TTL

CE

"A" = VIL and MIL. SA — — 65 160 50 150 40 125 40 125 mA

"B" = VIH

CE

(7)

LA — — 65 125 50 115 40 90 40 90

Level Inputs) Active Port Outputs COM'L. SA 65 165 65 150 50 125 40 110 40 110

(4)

Open, f = f

I

SB3 Full Standby Current

(Both Ports - All
CMOS Level Inputs V

SB4 Full Standby Current

I

(One Port - All
CMOS Level Inputs) V

CE

L and MIL. SA — — 1.0 30 1.0 30 1.0 30 1.0 30 mA

CE

R > VCC -0.2V, LA — — 0.2 10 0.2 10 0.2 10 0.2 10

IN > VCC -0.2V or COM'L. SA 1.0 15 1.0 15 1.0 15 1.0 15 1.0 15

V

IN < 0.2V,f = 0

CE

"A" < 0.2V and MIL. SA — — 60 155 45 145 40 110 40 110 mA
"B" > VCC -0.2V

CE

IN > VCC -0.2V or COM'L. SA 60 155 60 145 45 110 40 100 40 95
IN < 0.2V, LA 60 115 60 105 45 85 40 70 40 70

V
Active Port Outputs
Open, f = f

NOTES: 2689 tbl 06

1. 'X' in part numbers indicates power rating (SA or LA).

2. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP packages.

3. Not available in DIP packages.

4. At f = f

5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

6. Vcc = 5V, T

7. Port "A" may be either left or right port. Port "B" is opposite from port "A".

Max, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS”

of input levels of GND to 3V.

A=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ.)

MAX

MAX

(5)

(7)

(4)

LA 65 125 65 115 50 90 40 75 40 75

LA 0.2 5 0.2 5 0.2 4 0.2 4 0.2 4

LA — — 60 115 45 105 40 85 40 80

DATA RETENTION CHARACTERISTICS (LA Version Only)

Symbol Parameter Min. Typ.

DR VCC for Data Retention 2.0 — — V

V
I

CCDR Data Retention Current — 100 4000 µA

VCC = 2.0V,

(3)

CDR Chip Deselect to Data 0 — — ns

t

Retention Time

(3)

R Operation Recovery tRC ——ns

t

V

IN > VCC -0.2V or VIN < 0.2V

Test Conditions

CE

> VCC -0.2V

Mil.
Com’l.

lDT7130LA/IDT7140LA

— 100 1500 µA

(2)

Time

NOTES:

1. V

CC = 2V, TA = +25°C, and is not production tested.

2. t

RC = Read Cycle Time

3. This parameter is guaranteed but not production tested.

6.01 4

(1)

Max. Unit

2689 tbl 07

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION WAVEFORM

DATA RETENTION MODE

V

CC

CE

4.5V 4.5V

t

CDR

V

IH

V

DR

≥

2.0V
t

R

V

DR

V

IH

2692 drw 06

AC TEST CONDITIONS

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V

5ns

1.5V

1.5V

Figures 1, 2, and 3

DATA

BUSY

OUT

775Ω

or

5V

1250Ω

30pF*

Figure 1. Output Test Load

5V

270Ω

INT

2689 tbl 08

(*100pF for 55 and
100ns versions)

DATA

5V

OUT

775Ω

Figure 2. Output Test Load

(for t

HZ, tLZ, tWZ, and tOW)

* including scope and jig

1250Ω

5pF*

30pF*

Figure 3.

AC Output Test Load

BUSYBUSY

BUSY

BUSYBUSY

and

*

100pF for 55 and 100ns versions

INTINT

INT

INTINT

6.01 5

2689 drw 07