Integrated Device Technology Inc IDT71215S10PF, IDT71215S12PF, IDT71215S8PF, IDT71215S9PF Datasheet

Integrated Device Technology, Inc.

BiCMOS StaticRAM
240K (16K x 15-BIT)
CACHE-TAG RAM



For the Pentium

Processor

IDT71215

FEATURES:

• 16K x 15 Configuration
– 12 TAG Bits
– 3 Separate I/O Status Bits (Valid, Dirty, Write Through)

• Match output uses Valid bit to qualify MATCH output

• High-Speed Address-to-Match comparison times
– 8/9/10/12ns over commercial temperature range

•

BRDY

circuitry included inside the Cache-Tag for highest

speed operation

• Asynchronous Read/Match operation with Synchronous
Write and Reset operation

• Separate WE for the TAG bits and the Status bits

• Separate OE for the TAG bits, the Status bits, and

• Synchronous

RESET

pin for invalidation of all Tag entries

BRDY

• Dual Chip selects for easy depth expansion with no
performance degredation

• I/O pins both 5V TTL and 3.3V LVTTL compatible with
V

CCQ pins

•

PWRDN

pin to place device in low-power mode

• Packaged in a 80-pin Thin Plastic Quad Flat Pack
(TQFP)

DESCRIPTION:

The IDT71215 is a 245,760-bit Cache Tag StaticRAM,
organized 16K x 15 and designed to support the Pentium and
other Intel processors at bus speeds up to 66MHz. There are
twelve common I/O TAG bits, with the remaining three bits
used as status bits. A 12-bit comparator is on-chip to allow fast
comparison of the twelve stored TAG bits and the current Tag
input data. An active HIGH MATCH output is generated when
these two groups of data are the same for a given address.

This high-speed MATCH signal, with t

ADM as fast as 8ns,

provides the fastest possible enabling of secondary cache
accesses.

The three separate I/O status bits (VLD, DTY, and WT) can
be configured for either dedicated or generic functionality,
depending on the SFUNC input pin. With SFUNC LOW, the
status bits are defined and used internally by the device,
allowing easier determination of the validity and use of the
given Tag data. SFUNC HIGH releases the defined internal
status bit usage and control, allowing the user to configure the
status bit information to fit his system needs. A synchronous

RESET

pin, when held LOW at a rising clock edge, will reset
all status bits in the array for easy invalidation of all Tag
addresses.

The IDT71215 also provides the option for Burst Ready

(

BRDY

) generation within the cache tag itself, based upon
MATCH, VLD bit, WT bit, and external inputs provided by the
user. This can significantly simplify cache controller logic and
minimize cache decision time. Match and Read operations
are both asynchronous in order to provide the fastest access
times possible, while Write operations are synchronous for
ease of system timing.

The IDT71215 uses a 5V power supply on Vcc with sepa-

rate V

CCQ pins provided for the outputs to offer compliance

with both 5.0V TTL and 3.3V LVTTL Logic levels. The

PWRDN

pin offers a low-power standby mode to reduce power con­sumption by 90%, providing significant system power sav­ings.

The IDT71215 is fabricated using IDT's high-performance,
high-reliability BiCMOS technology and is offered in a space­saving 80-pin Thin Plastic Quad Flat Pack (TQFP) package.

PIN DESCRIPTIONS

A0 – A13 Address Inputs Input

CS1

, CS2 Chip Selects Input

WET
WES
OET
OES
RESET
PWRDN

SFUNC Status Bit Function Control Pin Input
W/

R

VLD

IN / S1IN Valid Bit / S1 Bit Input Input

DTY

IN / S2IN Dirty Bit / S2 Bit Input Input

WT

IN / S3IN Write Through Bit / S3 Bit Input Input

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Pentium is a trademark of Intel Corporation

Write Enable - Tag Bits Input
Write Enable - Status Bits Input
Output Enable - Tag Bits Input
Output Enable - Status Bits Input
Status Bit Reset Input
Powerdown Mode Control Pin Input

Write/Read Input from Processor Input

COMMERCIAL TEMPERATURE RANGE AUGUST 1996

1996 Integrated Device Technology, Inc. DSC-3075/3

CLK System Clock Input
BRDYH

BRDYOE BRDY
BRDYIN
BRDY

TAG

0 – TAG11 Tag Data Input/Outputs I/O

VLD

OUT / S1OUT Valid Bit / S1 Bit Output Output

DTY

OUT / S2OUT Dirty Bit / S2 Bit Output Output

WT

OUT / S3OUT Write Through Bit / S3 Bit Output Output

MATCH Match Output
V

CC +5V Power Pwr

V

CCQ Output Buffer Power QPwr

V

SS Ground Gnd

14.3

BRDY

Force High Input

Output Enable Input
Additional
Burst Ready Output

BRDY

Input Input

3075 tbl 01

1

IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION

IN

/ S1

IN

VLD

CC

V

SS

V

CS2

PWRDN

CS1

WET

WES

CC

V

SS

V

CLK

RESET

OES

OET

TAG11

BRDYOE

SS

V

CCQ

V

TAG10

TAG9

DTYIN / S2

IN

/ S3

WT

SS
SS
SS
SS

80

1

IN
IN

V
V
V
V

A0
A1
A2

V

CC

V

SS

PN80-1

A3
A4
A5
A6
A7

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

TAG8
TAG7
TAG6
VLD

OUT

V

CCQ
SS

V
BRDY
MATCH
V

SS

V

CCQ

OUT

WT
TAG5
TAG4
NC
V

SS

V

SS

V

SS

/ S1

/ S3

OUT

OUT

A8

SS

V

SFUNC

SS

V

CC

V

W/R

BRDYH

BRDYIN

A10

A9

TQFP

TOP VIEW

A11

A12

A13

OUT

/ S2

OUT

DTY

SS

V

TAG0

TAG1

CCQ

V

TAG2

TAG3

3075 drw 01

14.3 2

IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE

FUNCTIONAL BLOCK DIAGRAM

ADDR (0:13)

CS1

CS2

TAG (0:11)

OET

WET

WRITE

(pos) PULSE

GENERATOR

Reg

Reg

Reg

0

16K x 12

1

MEMORY

TAG BITS

Data in

Register

SA

16K x 3
MEMORY

STATUS BITS

Data in

Register

SA

VLD/S1IN
DTY/S2IN
WT/S3IN

VLD/S1

OUT

DTY/S2OUT
WT/S3OUT

WES

CLK

RESET

PWRDN

SFUNC

W/

BRDYH

BRDYIN

RESET

OES

(neg) PULSE

GENERATOR

COMPARE

MATCH

R

BRDY

Reg

BRDYOE

14.3 3

IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE

TRUTH TABLES

CHIP SELECT, RESET, AND POWER-DOWN FUNCTIONS

CS1

CS2

CS1

RESET

RESET

PWRDN

PWRDN

CLK

WET

WET

WES

WES

BRDYOE

BRDYOE

TAG VLDOUT DTYOUT WTOUT MATCH

(1, 2)

BRDY

OPERATION POWER

BRDY

CHIP SELECT FUNCTION

H X X H X X X X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Deselected Active
X L X H X X X X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Deselected Active

L H X H X X X X – – – – – – Selected Active

RESET FUNCTION

LH L H ↑ H H L Hi-Z L
LH L H ↑ H H H Hi-Z L

(3)

(3)

HX L H ↑ H H X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Reset Status Active
XL L H ↑ H H X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Reset Status Active
XX L H ↑ L X X – – – – – – Not Allowed –
XX L H ↑ X L X – – – – – – Not Allowed –

(3)

L

(3)

L

(3)

L

(3)

L

(3)

L

(3)

L

H Reset Status Active

Hi-Z Reset Status Active

POWER-DOWN FUNCTION

X X X L X H H X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Power-down Standby

NOTES:

1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.

2.

OET, OES

3.

OES

, W/R, BRDYH,

is LOW.

BRDYIN

and SFUNC are "X" for this table.

3075 tbl 02

READ AND WRITE FUNCTIONS

OET

OES

WET

WES

OET

OES

WET

WES

CLK W/

(1, 2)

RRTAG VLDIN DTYIN WTIN VLDOUT DTYOUT WTOUT MATCH OPERATION

READ FUNCTION

LXHX XXD
XLXX XX – – – –D
H X X X X X Hi-Z – – – – – – D
X H X X X X – – – – Hi-Z Hi-Z Hi-Z D

OUT ––––––DOUT Read TAG I/O

OUT DOUT D OUT DOUT Read Status Bits

OUT TAG I/O Disable
OUT Status Disabled

WRITE FUNCTION

HXLX ↑XD
LXLX ↑X – – – – – – – – Not Allowed
XLXL ↑X–D
XHXL ↑X–D

NOTES:

1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.

2. This table applies when

3. D

OUT in this case is the same as DIN; that is, the input data is written through to the outputs during the write operation.

CS1

is LOW and CS2,

IN –––DOUT DOUT DOUT L Write TAG I/O

RESET

IN DIN DIN DOUT
IN DIN DIN Hi-Z Hi-Z Hi-Z L Write Status Bits

, and

PWRDN

are HIGH.

BRDYOE

(3)

, BRDYH,

DOUT

(3)

BRDYIN

(3)

DOUT

and SFUNC are "X" for this table.

L Write Status Bits

3075 tbl 03

14.3 4

IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE

TRUTH TABLES (CONT.)

OET

OET

(1, 2, 3)

WET

WET

WES

WES

TAG VLD

(4)

DTY

(4)

(4)

WT

MATCH OPERATION

MATCH FUNCTION

CS1

CS2 SFUNC

CS1

H X X X X X Hi-Z – – – Hi-Z Deselected
X L X X X X Hi-Z – – – Hi-Z Deselected
LHXXXX ––––D
LH X L HX D
LH X H LX D
LH X X XL – D
L H L H H H TAG
L H L H H H TAG
L H H H H H TAG

NOTES: 3075 tbl 04

1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.

2. M = HIGH if TAG

3.

PWRDN

4. This column represents the stored memory cell data for the given Status bit at the selected address.

and

IN equals the memory contents at that address; M = LOW if TAGIN does not equal the memory contents at that address.

RESET

are HIGH for this table. W/R, BRDYH,

OUT – – – L Read Tag I/O

IN – – – L Write Tag I/O

IN DIN DIN L Write Status Bits
IN L – – L Invalid Data - Dedicated Status Bits
IN H – – M Match - Dedicated Status Bits
IN X – – M Match - Generic Status Bits

BRDYOE, BRDYIN, OES

OUT Selected

, and CLK are "X".

(6)

OET

OET

(1, 2, 3, 5)

WET

WET

WES

WES

BRDYH W/

RR SFUNC VLD

(4)

DTY

(4)WT(4)

TAG MATCH

BRDY

BRDY

OPERATION

BRDY

Disabled

BRDY

Input

(7)

BRDY

BRDY

BRDYOE

BRDYOE

FUNCTION

BRDYIN

BRDYIN

H X X X X X X X X – X – – Hi-Z
L L X X X X X X X – X – X L Ext
LHLXXXXXX–XDOUT L H Read TAG
LHXLXXXXX–XD
LHXXLXXXD

IN DIN DIN – L H Write Status

L H X X X H X X X – X – X H Force

IN L H Write TAG

BRDY

HIGH
L H X X X X X L L – X – L H Invalid TAG
L H X X X X H L X – H – X H Write Through
L H H H H L X L H – L TAG
L H H H H L L L H – X TAG
L H H H H L X L H – X TAG
L H H H H L X H X – X TAG

NOTES: 3075 tbl 05

1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.

2. M = HIGH if TAG

3.

PWRDN

4. This column represents the stored memory cell data for the given Status bit at the selected address.

5.

6.

7.

and

CS1

is LOW, CS2 is HIGH for this table.

BRDYIN

is a synchronous input; thus the inputs noted in the table must be applied during a rising CLK edge.

BRDYIN

will be a factor in determining the

be LOW(Valid).

IN equals the memory contents at that address; M = LOW if TAGIN does not equal the memory contents at that address.

RESET

are HIGH for this table. CLK and

BRDY

OES

are "X".

output in all cases except when BRDYH is HIGH and there is a valid MATCH. In that case,

IN M
IN M
IN M
IN M

M

M

M

M

Compare
Compare
Compare
Compare

BRDY

will

14.3 5