IDT IDT70V3379S User Manual
查询IDT70V3379S供应商
HIGH-SPEED 3.3V 32K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5/6ns (max)
◆
Pipelined output mode
◆
Counter enable and reset features
◆
Dual chip enables allow for depth expansion without
additional logic
◆
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
Functional Block Diagram
L
UB
IDT70V3379S
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆
Separate byte controls for multiplexed bus and bus
matching compatibility
◆
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
◆
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
◆
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
◆
Available in a 128-pin Thin Quad Plastic Flatpack (TQFP)
and 208-pin fine pitch Ball Grid Array, and 256-pin
Ball Grid Array
R
UB
R
CE
CE
OE
LB
R
W
R/
0R
1R
R
L
LB
L
W
R/
0L
CE
1L
CE
L
OE
B
B
W
W
0
1
L
L
Dout0-8_L
Dout9-17_L
B
B
W
W
1
0
R
R
Dout0-8_R
Dout9-17_R
32K x 18
MEMORY
ARRAY
,
.
17R
R
CLK
R
R
R
CLK
I/O0L-I/O
L
A
14L
A
CNTRST
ADS
CNTEN
17L
0L
L
L
L
Counter/
Address
Reg.
Din_L
ADDR_L
Din_R
ADDR_R
Counter/
Address
Reg.
I/O0R-I/O
A
14R
A
0R
CNTRST
ADS
CNTEN
4833 tbl 01
©2001 Integrated Device Technology, Inc.
APRIL 2001
1
DSC 4833/8
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
Description:
The IDT70V3379 is a high-speed32K x 18 bit synchronous Dual-Port
RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on control,
data, and address inputs provide minimal setup and hold times. The timing
latitude provided by this approach allows systems to be designed with very
short cycle times. With an input data register, the IDT70V3379 has been
optimized for applications having unidirectional or bidirectional data flow
in bursts. An automatic power down feature, controlled by CE0 and CE1,
permits the on-chip circuitry of each port to enter a very low standby power
mode.
The 70V3379 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controllable by the OPT pins. The power supply for
the core of the device (V
DD) remains at 3.3V.
Pin Configuration
21
I/O
9L
NC
SS
V
NC
V
NC
SS
I/O9RV
V
SS
NC
11R
I/O
SS
V
NC
V
DD
V
SS
14LVDDQR
DDQRVDD
I/O
10L
DDQR
V
NC V
12L
V
DDQR
V
SS
I/O
13R
DDQL
V
NC
11L
I/O
DDQL
V
NC I/O
V
DD
V
DDQL
I/O
14R
NC I/O
(1,2,3,4)
9876543
A
NC
NC OPT
NC
V
SS
NC
NC
NC
A
I/O
NC
10R
SS
12L
A
9L
13L
A
A
14L
10L
A
11L
7L
A
UB
A
NC
LB
NC
8L
CE
0L
L
1L
CE
DD
V
L
NC
I/O
12R
70V3379BF
BF-208
SS
V
208-Pin fpBGA
Top View
I/O
SS
V
13L
10
(5)
V
V
V
OE
(6)
11
DD
L
L
CNTEN
CLK
SS
ADS
L
5L
A
SS
R/
L
CNTRST
6L
A
L
W
3L
A
L
1412 13
15
A
4L
A
V
SS
1L
A
DD
V
2L
A
NC
DD
V
I/O
SS
V
NC
DD
V
V
SS
I/O
NC
L
0L
V
DDQR
8R
I/O
DDQL
V
6L
6R
I/O
V
DDQL
NC
V
DD
3R
V
DDQL
3L
I/O
I/O
I/O
I/O
I/O
NC
NC
V
NC
V
V
V
1716
V
SS
A
NC
8L
7L
SS
5L
SS
SS
4R
SS
V
V
V
I/O
NCNC
I/O
V
I/O
SS
DDQR
NC
DDQR
SS
B
C
7R
D
E
F
G
5R
H
J
K
4L
L
DDQL
I/O
V
NC
16R
SS
V
NC
SS
V
I/O
I/O
NC
V
NC
NC
I/O
15R
V
SS
SS
16L
V
I/O
17L
V
NC
DDQR
DDQL
V
15L
I/O
8R
A
12R
NC
NC
NC
NC
V
NC
NC
SS
NC
NC
17R
DD
13R
A
14RA10R
A
11R
A
A
9R
A
7R
A
UB
NC
DD
V
0R
CE
NC
R
R
LB
CE
V
SS
1R
SS
V
DD
V
OE
R
CLK
ADS
W
R/
CNTRST
R
CNTEN
R
R
A
5R
6R
A
R
3R
R
A
SS
NC
V
DDQL
V
1R
I/O
1L
I/O
NC
A
4R
V
DDQL
V
SS
A
1R
SS
NC
V
2R
A
DD
V
0R
A
OPT
R
NOTES:
DD pins must be connected to 3.3V power supply.
1. All V
DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
2. All V
3. All V
IL (0V).
set to V
SS pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
I/O
V
I/O
NC
V
NC
2R
DDQR
V
M
2L
I/O
N
NC
SS
0R
SS
DDQR
V
NC
0L
I/O
4833 tbl 02
P
R
T
U
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3,4)
(con't.)
A2
A1
NC
B1
NC
C1
NC
D1
NC
E1
I/O
10R
F1
I/O
11L
G1
NC
H1
NCH2I/O
J1
I/O
13L
K1
NC
L1
I/O
15L
M1
I/O
16R
N1NCN2
P1
NCP2I/O
R1NCR2NCR3NCR4
T1
NC
NC
B2
NC
C2
I/O
9L
D2
I/O
9R
E2
I/O
10L
F2
NCF3I/O
G2
NC
12R
J2
I/O
14R
K2
NC
L2
NC
M2
I/O
16L
17R
I/O
17L
T2NCT3
A3
NC
B3
NC
C3
V
SS
D3
NC
E3
NCE4V
11R
G3
12L
I/O
H3NCH4
J3
I/O
13R
K3
14L
I/O
L3
I/O
15R
M3
NCM4V
N3
NC
P3
NCP4NC
NC
A4
B4
C4
D4
F4
V
G4
V
V
J4
V
K4
V
L4
V
N4
T4
NC
NC
NC
V
DD
DDQL
DDQL
DDQR
DDQR
DDQL
DDQL
DDQR
DDQR
DD
V
NC
NC
A5
B5
C5
D5
V
E5
F5
G5
H5
J5
K5
L5
M5
N5
V
P5
R5
T5
A
14L
NC
A
DDQL
V
V
V
V
V
V
V
V
DDQR
A
13R
NC
A
13L
DD
DD
SS
SS
SS
SS
DD
DD
14R
A6
A
B6
C6
D6
V
E6
F6
G6
H6
J6
K6
L6
M6
N6
V
P6
R6
T6
11L
A
A
DDQL
V
V
V
V
V
V
V
V
DDQR
A
A
12R
A
12L
10L
DD
SS
SS
SS
SS
SS
SS
DD
10R
11R
70V3379BC
BC-256
256-Pin BGA
Top View
A8
A7
B7
C7
D7
V
E7
F7
G7
H7
J7
K7
L7
M7
N7
V
P7
R7
T7
A
8L
A
9L
A
7L
DDQR
V
SS
V
SS
SS
V
V
SS
V
SS
V
SS
V
SS
V
SS
DDQL
A
7R
A
9R
8R
A
B8
C8
D8
V
E8
F8
G8
H8
J8
K8
L8
M8
N8
V
P8
R8
T8
NC
UB
NC
DDQR
V
V
V
SS
V
SS
V
V
V
V
DDQL
NC
UB
NC
SS
SS
SS
SS
SS
SS
(5)
(6)
A14
A10
B10
R/
C10
CLK
D10
V
E10
F10
G10
H10
J10
K10
L10
M10
N10
V
P10
CLK
R10
R/
T10
OE
W
DDQL
V
SS
V
SS
SS
V
V
SS
V
SS
V
SS
V
SS
V
SS
DDQR
W
OE
L
L
L
R
R
R
A11
CNTEN
B11
CNTRST
C11
ADS
D11
V
DDQR
E11
V
DD
F11
V
SS
G11
SS
V
H11
V
SS
J11
V
SS
K11
V
SS
L11
V
SS
M11
V
DD
N11
DDQL
V
P11
ADS
R11
CNTRST
T11
CNTEN
L
L
L
R
R
R
A9
CE
1L
B9
CE
0L
L
C9
LB
L
D9
V
DDQL
E9
V
SS
F9
V
SS
G9
V
SS
H9
V
SS
J9
V
SS
K9
V
SS
L9
V
SS
M9
V
SS
N9
DDQR
V
P9
LB
R
R9
CE
R
0R
T9
1R
CE
A12
B12
C12
D12
V
E12
F12
G12
H12
J12
K12
L12
M12
N12
V
P12
R12
T12
A
A
A
DDQR
V
V
DD
SS
V
V
SS
V
SS
V
SS
V
DD
V
DD
DDQL
A
A
A
DD
6R
4R
5R
A13
A
A
5L
B13
4L
C13
6L
D13
V
E13
V
DDQR
F13
V
DDQR
G13
V
H13
V
DDQL
J13
V
DDQR
K13
V
L13
V
M13
V
N13
V
P13
A
R13
A
T13
A
2L
A
1L
A
3L
DD
DDQL
DDQR
DDQL
DDQL
DD
3R
1R
2R
B14
V
C14
OPT
D14
NC
E14
F14
I/O
G14
I/O
H14
NC
J14
I/O
K14
NC
L14
I/O
M14
I/O
N14
NC
P14
R14
OPT
T14
A
0L
DD
L
NC
6R
5L
4R
2L
1R
NC
R
0R
A16
A15
NC
B16
B15
NC
C16
C15
NC
D16
D15
NC
E15
I/O
7L
F15
F16
NC
G16
G15
NC
H16
H15
NC
J16
J15
I/O
3R
K16
K15
NC
L15
L16
NC
M16
M15
I/O
1L
N16
N15
0R
I/O
P15
P16
NC
R16
R15
NC
T15NCT16
I/O
I/O
E16
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
I/O
NC
NC
I/O
NC
NC
8L
8R
7R
6L
5R
4L
3L
2R
0L
,
NOTES:
DD pins must be connected to 3.3V power supply.
1. All V
DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
2. All V
3. All V
IL (0V).
set to V
SS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
4833drw 02c
,
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
V
V
V
V
A
IO
IO
DDQL
V
IO
IO
DDQR
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
DDQL
IO
IO
DDQR
V
IO
IO
A
(1,2,3,4)
14L
NC
V
SS
NC
9L
9R
SS
10L
10R
V
SS
11L
11R
12L
12R
V
DD
V
DD
V
SS
V
SS
13R
13L
14R
14L
15R
15L
V
SS
16R
16L
SS
17R
17L
NC
NC
NC
14R
(con't.)
L
L
3
2
1
1
A
A
8
7
2
2
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
9
0
38
3
4
L
L
T
S
N
L
E
L
L
L
0
L
L
1
1
A
6
2
1
L
1
9
8
7
A
A
A
A
5
4
3
2
2
2
2
2
1
1
1
1
L
L
1
0
D
L
B
E
E
D
B
U
L
C
C
V
1
0
9
8
2
1
7
2
1
1
1
1
1
1
1
L
L
K
D
S
S
E
L
D
S
S
V
6
1
1
O
V
V
C
5
4
3
2
1
1
1
1
1
1
1
1
70V3379PRF
PK-128
(5)
128-Pin TQFP
Top View
1
4
2
3
5
6
7
8
4
4
4
4
4
9
4
4
4
4
(6)
0
1
4
2
3
5
5
5
5
5
R
L
T
T
S
L
L
L
L
W
N
N
/
R
1
1
1
5
5
6
D
A
C
C
A
0
9
8
7
1
0
0
0
1
1
1
1
6
7
8
9
5
5
5
5
L
5
4
3
2
A
A
A
A
6
5
4
3
0
0
0
0
102
1
1
1
1
101
100
85
82
78
76
74
0
1
2
3
6
4
6
6
6
6
A
1L
A
0L
OPT
L
SS
DDQL
7L
7R
SS
DDQR
DD
DD
SS
SS
SS
DDQL
SS
DDQR
OPT
0R
1R
(7)
8L
8R
(7)
6L
6R
5L
5R
4R
4L
3R
3L
2R
2L
1R
1L
0R
0L
R
99
NC (VSS)
IO
98
97
IO
NC (VSS)
96
V
95
V
94
IO
93
IO
92
91
V
90
V
89
IO
88
IO
87
IO
86
IO
V
V
84
V
83
V
81
IO
80
IO
79
IO
IO
77
IO
IO
75
V
V
73
IO
72
IO
71
V
70
V
69
IO
68
IO
67
66
A
65
A
Pin Configuration
.
S
R
R
R
R
R
3
1
A
R
2
1
0
9
1
1
1
A
A
A
A
R
R
R
R
8
7
A
A
R
1
0
B
B
E
E
L
U
C
C
NOTES:
DD pins must be connected to 3.3V power supply.
1. All V
DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
2. All V
3. All V
IL (0V).
set to V
SS pins must be connected to ground supply.
4. Package body is approximately 14mm x 20mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
7. In the 70V3379 (32K x 18) and 70V3389 (64K x 18), pins 96 and 99 are NC. The upgrade devices 70V3399 (128K x 18) and 70V3319 (256K x 18) assign
these pins as Vss. Customers who plan to take advantage of the upgrade path should treat these pins as VSS on the 70V3379 and 70V3389. If no upgrade is
needed, the pins can be treated as NC.
S
R
R
R
R
R
D
D
S
S
D
D
V
V
E
K
V
V
L
O
C
R
R
R
R
R
R
6
5
4
T
S
N
W
/
S
E
D
R
T
R
A
T
N
N
C
C
3
A
A
A
A
2
A
4833 drw 02a
6.42
4
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
Pin Names
Left Port Right Port Names
0L
CE
CE
,
L
W
R/
L
OE
0L
- A
A
I/O0L - I/O
L
CLK
L
ADS
CNTEN
CNTRST
L
- LB
UB
V
14L
L
L
L
DDQL
OPT
1L
17L
L
CE
R/
OE
A0R - A
I/O0R - I/O
CLK
ADS
CNTEN
CNTRST
UBR - LB
DD
V
SS
V
0R
1R
CE
,
R
W
R
14R
17R
R
R
R
R
R
DDQR
V
OPT
Chip Enables
Read/ Write Enab le
Output Enable
Address
Data In pu t/O utp ut
Clock
Address Strobe Enable
Co unte r En ab l e
Coun te r Re se t
Byte Enables (9-bit bytes)
Po we r (I/O Bus ) (3.3V or 2.5V )
R
Op tio n fo r se l e ct ing V
Po we r (3.3V )
Ground (0V)
NOTES:
DD, OPTX, and VDDQX must be set to appropriate operating levels prior to
1. V
applying inputs on the I/Os and controls for that port.
(1)
(1,2)
DDQX
(1)
X selects the operating voltage levels for the I/Os and controls on that port.
2. OPT
X is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
If OPT
levels and V
port's I/Os and controls will operate at 2.5V levels and V
DDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
DDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
48 33 tb l 01
with the other at 2.5V.
Truth Table IRead/Write and Enable Control
OE
CLK
X
X
X
X
H
↑
↑
↑
↑
L
↑
L
↑
L
↑
↑
0
CE
L H H H X High-Z High-Z All By tes Des ele c ted
LHHL LHigh-Z D
LHLHL DINHigh-Z Write to Upper Byte Only
LHLLL D
LHHLHHigh-Z D
LHLHH D
LHLLHD
L H L L X H ig h-Z Hig h-Z Outp uts Dis ab le d
CE
1
NOTES:
1. "H" = V
2. ADS, CNTEN, CNTRST = V
IH, "L" = VIL, "X" = Don't Care.
IH.
3. OE is an asynchronous input signal.
UB LB
R/
W
Upper Byte
I/O
9-18
IN
OUT
OUT
Lower Byte
0-8
I/O
IN
IN
D
OUT
Hig h-Z Read Upp e r By te Onl y
OUT
D
(1,2,3)
MODE
Write to Lower Byte Only
Wri te to B o th B y te s
Read Lo wer By te Only
Read Both Bytes
4833 t bl 02
6.42
5
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
Truth Table IIAddress Counter Control
Address
Address
XX0↑XX L
An X An
An Ap Ap
XApAp + 1↑H L
NOTES:
Previous
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE
Addr
Used CLK
(6)
ADS CNTEN CNTRST
(4)
L
↑
↑
XHD
HH H D
(5)
(4)
HD
(1,2)
(3)
I/O
I/O
D
(0) Counter Reset to Address 0
I/O
(n) External Address Used
I/O
(p) External Address Blocked—Counter disabled (Ap reused)
I/O
(p+1) Counter Enable d —Internal Address generation
0, CE1, BEn and OE.
MODE
4833 tbl 03
3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other memory control signals including CE
5. The address counter advances if CNTEN = V
IL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
0, CE1 and BEn
Recommended Operating
DD
(1,2)
4833 tbl 04
Unit
o
C
o
C
48 33 tb l 06
Temperature and Supply Voltage
Ambient
Grade
Commercial 0OC to +7 0OC0V3.3V + 150mV
Industrial -40OC to +8 5OC0V3.3V + 150mV
NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter T
Absolute Maximum Ratings
Symbol Rat ing Commercial
(2)
TERM
V
BIAS
T
STG
T
OUT
I
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
TERM must not exceed VDD + 150mV for more than 25% of the cycle time or
2. V
4ns maximum, and is limited to
Terminal Voltage
with Res pe c t to
GND
Tempe rature
Under Bias
Storage
Tempe rature
DC Output Curre nt 50 mA
Temperature GND V
A. This is the "instant on" case tempereature.
(1)
& Industrial
-0.5 to +4.6 V
-55 to +125
-65 to +150
< 20mA for the period of VTERM > VDD + 150mV.
Recommended DC Operating
Conditions with V
Symbol Parameter Min. Typ. Max. Unit
DD
Core S upp ly Vo ltage 3.15 3.3 3.45 V
V
DDQ
I/O Supply Voltage
V
SS
V
Ground 0 0 0 V
Input High Vo ltage
IH
V
(Ad d re ss & Contro l Inputs )
IH
V
Input High Vo ltage - I/O
IL
Input Lo w Vol tage -0. 3
V
NOTES:
IL > -1.5V for pulse width less than 10 ns.
1. V
TERM must not exceed VDDQ + 125mV.
2. V
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to V
supplied as indicated above.
(3)
DDQ at 2.5V
(3)
2.375 2.5 2.625 V
____
1.7
(3)
____
1.7
(1)
____
IL (0V), and VDDQX for that port must be
V
V
DDQ
DDQ
+ 125m V
+ 125m V
(2)
(2)
0.7 V
4833 tbl 05a
V
V
Recommended DC Operating
Conditions with V
Symbol Parameter Min. Typ. Max. Unit
Core S upp l y Voltag e 3.15 3.3 3.45 V
V
DD
V
I/O Supply Voltage
DDQ
Ground 0 0 0 V
V
SS
Inp ut Hi g h Vo l tag e
V
IH
(Ad d re ss & Contro l Inputs )
V
Inp u t Hig h Vo l tag e - I/O
IH
Input Lo w Vo ltag e -0.3
V
IL
NOTES:
IL > -1.5V for pulse width less than 10 ns.
1. V
TERM must not exceed VDDQ + 150mV.
2. V
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to V
supplied as indicated above.
(3)
DDQ at 3.3V
3.15 3.3 3.45 V
____
2.0
(3)
(3)
2.0
(1)
IH (3.3V), and VDDQX for that port must be
V
+ 150mV
DDQ
____
V
+ 150mV
DDQ
____
0.8 V
(2)
(2)
4833 t b l 0 5 b
V
V
6.42
6
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