Integrated Device Technology Inc IDT7024S15PF, IDT7024S17F, IDT7024S17G, IDT7024S17J, IDT7024S17PF Datasheet

Integrated Device Technology, Inc.

HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM

IDT7024S/L

FEATURES:

• True Dual-Ported memory cells which allow simulta­neous access of the same memory location

• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial: 15/17/20/25/35/55ns (max.)

• Low-power operation
— IDT7024S

Active: 750mW (typ.)
Standby: 5mW (typ.)

— IDT7024L

Active: 750mW (typ.)
Standby: 1mW (typ.)

• Separate upper-byte and lower-byte control for
multiplexed bus compatibility

• IDT7024 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading

FUNCTIONAL BLOCK DIAGRAM

W

L

R/

UB

L

more than one device

•M/S = H for
M/S = L for

BUSY

output flag on Master

BUSY

input on Slave

• Busy and Interrupt Flags

• On-chip port arbitration logic

• Full on-chip hardware support of semaphore signaling
between ports

• Devices are capable of withstanding greater than 2001V

electrostatic discharge.

• Fully asynchronous operation from either port

• Battery backup operation—2V data retention

• TTL-compatible, single 5V (±10%) power supply

• Available in 84-pin PGA, 84-pin quad flatpack, 84-pin
PLCC, and 100-pin Thin Quad Plastic Flatpack

• Industrial temperature range (–40°C to +85°C) is avail­able, tested to military electrical specifications

W

R

R/

UB

R

NOTES:

1. (MASTER):

BUSY

is output;
(SLAVE):
is input.

2.

BUSY

outputs

and

INT

outputs
are non-tri-stated
push-pull.

BUSY

I/O8L-I/O

I/O0L-I/O

BUSY

LB
CE
OE

A

A

SEM
INT

15L

(1,2)
L

11L

L
L
L

I/O

12

Control

MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

M/

S

7L

Address

0L

L

(2)

L

Decoder

CE
OE

R/

W

L
L
L

I/O

Control

Address
Decoder

12

CE

R

OE

R

R/

W

R

LB

R

CE

R

OE

R

I/O8R-I/O

I/O0R-I/O

BUSY

A

11R

A

0R

SEM

R
(2)

INT

R

2740 drw 01

R

15R

7R

(1,2)

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-2740/6

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.15

1

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DESCRIPTION:

The IDT7024 is a high-speed 4K x 16 Dual-Port Static
RAM. The IDT7024 is designed to be used as a stand-alone
64K-bit Dual-Port RAM or as a combination MASTER/SLAVE
Dual-Port RAM for 32-bit or more word systems. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or
wider memory system applications results in full-speed, error­free operation without the need for additional discrete logic.

This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by chip
enable ( CE ) permits the on-chip circuitry of each port to enter

PIN CONFIGURATIONS

6L

3L

5L

INDEX

I/O

I/O
I/O
I/O
I/O
I/O

GND
I/O
I/O

V

GND

I/O
I/O
I/O

V
I/O
I/O
I/O
I/O
I/O
I/O

7L

I/O

I/O

11109876543218483

8L

12

9L

13

10L

14

11L

15

12L

16

13L

17
18

14L

19

15L

20

CC

21
22

0R

23

1R

24

2R

25

CC

26

3R

27

4R

28

5R

29

6R

30

7R

31

8R

32

33 34 35 36 37 38 39 40 41 42 43 44 45

9R

11R

10R

I/O

I/O

I/O

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

I/O

12R

I/O

4L

I/O

13R

I/O

I/O

14R

I/O

2L

I/O

GND

GND

15R

I/O

(1,2)

L

1L

0L

CC

I/O

OE

V

I/O

IDT7024

J84-1
F84-2

84-PIN PLCC /

FLATPACK

TOP VIEW

R

R

W

OE

GND

R/

L

L

L

L

SEM

CE

UB

L

N/C

LB

W

R/

82 81 80 79 78 77 76 75

(3)

46 47 48 49 50 51 52 53

R

R

R

R

SEM

CE

UB

11R

N/C

LB

A

10R

A

11L

A

10L

9L

8L

A

A

A

A

7L

74

A

6L

73

A

5L

72

A

4L

71

A

3L

70

A

2L

69

A

1L

68

A

0L

67

INT

L

66

BUSY

65

GND

64
63

M/

S

62

BUSY

61

INT

R

60

A

0R

59

A

1R

58

A

2R

57

A

3R

56

A

4R

A

5R

55

A

6R

54

2740 drw 02

9R

7R

8R

A

A

A

a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technol
ogy, these devices typically operate on only 750mW of power.
Low-power (L) versions offer battery backup data retention
capability with typical power consumption of 500µW from a 2V
battery.

The IDT7024 is packaged in a ceramic 84-pin PGA, an 84­pin quad flatpack, an 84-pin PLCC, and a 100-pin TQFP.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited
to military temperature applications demanding the highest
level of performance and reliability.

L

R

Index

I/O
I/O
I/O
I/O

GND
I/O
I/O

GND

I/O
I/O
I/O

I/O
I/O
I/O
I/O

9L

8L

7L

6L

5L

I/O

I/O

I/O

I/O

I/O

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

N/C

1

N/C

2

N/C

3

N/C

4

10L

5

11L

6

12L

7

13L

8
9

14L

10

15L

11

V

CC

12
13

0R

14

1R

15

2R

16

V

CC

17

3R

18

4R

19

5R

20

6R

21

N/C

22

N/C

23

N/C

24

N/C

25

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

7R

8R

9R

10R

11R

I/O

I/O

I/O

I/O

I/O

4L

I/O

12R

I/O

3L

I/O

13R

I/O

2L

I/O

14R

I/O

1L

I/O

GND

TOP VIEW

15R

GND

I/O

L

0L

I/O

OE

IDT7024
PN100-1

100-PIN

TQFP

R

R

W

OE

R/

CC

V

GND

L

W

R/

(3)

R

SEM

L

SEM

R

CE

L

CE

R

UB

L

UB

R

LB

L

LB

N/C

N/C

11R

A

11L

A

10R

A

10L

A

9R

A

9L

8L

7L

6L

A

A

A

A

75
74

73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

2740 drw 03

6R

5R

8R

7R

A

A

A

A

N/C
N/C
N/C
N/C
A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

INT

BUSY

GND
M/

S

BUSY

INT

A

0R

A

1R

A

2R

A

3R

A

4R

N/C
N/C
N/C
N/C

L

L

R

R

6.15 2

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS (CONT'D)

63 61 60 58 55 54 51 48 46 45

11

66

10

I/O

67

09

I/O

69

08

I/O

72

07

I/O

75

06

76

05

79

04

81

03

82

02

84346915131618

01

I/O

I/O

7L

5L

I/O4LI/O2LI/O

64

62

10L

I/O8LI/O6LI/O3LI/O

65

11L

I/O

9L

68

13L

I/O

12L

71

73

15L

I/O

14L

V

70

74

GND

I/O

I/O

I/O

11R

GND

78

V

2R

4R

7R

9R

I/O

I/O

I/O

0R

77

I/O

1R

80

I/O

3R

83

I/O

5R

125

I/O6RI/O

I/O8RI/O

CC

CC

(1,2)

A

0L

59 56 49 50 40

1L

57 53 52

GND

IDT7024

84-PIN PGA

TOP VIEW

7

81110

10R

I/O

13R

I/O

15R

12R

I/O

14R

OERLB

SEM

OE

L

UB

L

V

CC

G84-3

(3)

12

SEM

GNDGND

14 17 20

R

R/

W

R

R/

UB

CE

CE

L

L

W

L

R

R

R

LB

47 44

N/C

A

N/C

L

11R

11L

A

9L

33 35

BUSY

L

32 31

GND

28 29

A

0R

A

8R

A

10R

A

10L

43

A

8L

41

A

6L

38

A

3L

A

0L

M/

S

INT

R

26

A

2R

23

A

5R

22 24

A

6R

19 21

A

9R

42

A

7L

A

5L

39

A

4L

37

A

2L

34

INT

36

A

1L

30

BUSY

27

A

1R

25

A

3R

A

4R

A

7R

L

R

ABCDEFGHJ KL

Index

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

PIN NAMES

Left Port Right Port Names

CE

L

R/

W

L R/WR Read/Write Enable

OE

L

A

0L – A11L A0R – A11R Address

I/O

0L – I/O15L I/O0R – I/O15R Data Input/Output

SEM

L

UB

L

LB

L

INT

L

BUSY

L

CE

R Chip Enable

OE

R Output Enable

SEM

R Semaphore Enable

UB

R Upper Byte Select

LB

R Lower Byte Select

INT

R Interrupt Flag

BUSY

R Busy Flag

M/

S

V

CC Power

Master or Slave Select

GND Ground

2740 tbl 1

2740 drw 04

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND V

Military –55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%

CC

2740 tbl 02

6.15 3

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL

(1)

Inputs

CECE

CE

CECE

R/

WW

W

WW

OEOE

OE

OEOE

UBUB

UB

UBUB

LBLB

LB

LBLB

SEMSEM

SEM

SEMSEM

H X X X X H High-Z High-Z Deselected: Power-Down
X X X H H H High-Z High-Z Both Bytes Deselected

L L X L H H DATA
L L X H L H High-Z DATA
L L X L L H DATA
L H L L H H D ATA
L H L H L H High-Z DATA
L H L L L H DATA

X X H X X X High-Z High-Z Outputs Disabled

NOTE: 2740 tbl 03

1. A0L — A11L are not equal to A0R — A11R.

TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL

Inputs Outputs

CECE

CE

CECE

H H L X X L DATA
X H L H H L DATA
H
X

L X X L X L — — Not Allowed
L X X X L L — — Not Allowed

NOTE:

1. There are eight semaphore flags written to via I/O

R/

WW

W

WW

u
u

OEOE

OE

OEOE

UBUB

UB

UBUB

LBLB

LB

LBLB

SEMSEM

SEM

SEMSEM

X X X L DATA
X H H L DATA

0 and read from all of the I/O's (I/O0 - I/O15). These eight semaphores are addressed by A0 - A2.

Outputs

8-15 I/O0-7 Mode

I/O

IN High-Z Write to Upper Byte Only

IN Write to Lower Byte Only

IN DATAIN Write to Both Bytes

OUT High-Z Read Upper Byte Only

OUT Read Lower Byte Only

OUT DATAOUT Read Both Bytes

(1)

8-15 I/O0-7 Mode

I/O

OUT DATAOUT Read Semaphore Flag Data Out
OUT DATAOUT Read Semaphore Flag Data Out

IN DATAIN Write I/O0 into Semaphore Flag
IN DATAIN Write I/O0 into Semaphore Flag

2740 tbl 04

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

V

TERM

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND

T

A Operating 0 to +70 –55 to +125 °C

Temperature

T

BIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

STG Storage –55 to +125 –65 to +150 °C

T

Temperature

I

OUT DC Output 50 50 mA

Current

NOTES: 2740 tbl 05

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. V

TERM must not exceed Vcc +0.5V for more than 25% of the cycle time or

10ns maximum, and is limited to

.

+ 0.5V

< 20ma for the period over VTERM > Vcc

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CC Supply Voltage 4.5 5.0 5.5 V

V
GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.2 — 6.0

V
V

IL Input Low Voltage –0.5

NOTES: 2740 tbl 06

1. VIL > -1.5V for pulse width less than 10ns.

TERM must not exceed Vcc + 0.5V.

2. V

CAPACITANCE

(1)

(1)

— 0.8 V

(TA = +25°C, F = 1.0MHZ) TQFP ONLY

Symbol Parameter Condition

IN Input Capacitance VIN = 3dV 9 pF

C

OUT Output Capacitance VOUT = 3dV 10 pF

C

NOTES: 2740 tbl 07

1. This parameter are determined by device characterization, but is not
production tested.

2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.

(2)

(2)

Max. Unit

V

6.15 4

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

LI| Input Leakage Current

|I

LO| Output Leakage Current

|I

OL Output Low Voltage IOL = 4mA — 0.4 — 0.4 V

V

OH Output High Voltage IOH = -4mA 2.4 — 2.4 — V

V

NOTE:

1. At Vcc

< 2.0V input leakages are undefined.

(1)

VCC = 5.5V, VIN = 0V to VCC —10—5µA

CE

= VIH, VOUT = 0V to VCC —10—5µA

(VCC = 5.0V ± 10%)

IDT7024S IDT7024L

2740 tbl 08

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

7024X15 7024X17 7024X20 7024X25

Test Com'l. Only Com'l. Only

Symbol Parameter Condition Version Typ.

CC Dynamic Operating

I
Current

(Both Ports Active) f = f

CE

"A"=VIL, Outputs Open MIL S — — — — 160 370 155 340 mA

SEM

= V

IH L — — — — 160 320 155 280

(3)

MAX

COM S 170 310 170 310 160 290 155 265

L 170 260 170 260 160 240 155 220

I

SB1 Standby Current CER = CEL = VIH MIL S — — — — 20 90 16 80 mA

(Both Ports — TTL
Level Inputs) f = f

SEM

R =

MAX

SEM

L = VIH L————20701665

(3)

COMS2060206020601660

L2050205020501650

I

SB2 Standby Current

CE

"A"=VIL and CE"B"=VIL

(5)

MIL S — — — — 95 240 90 215 mA

(One Port — TTL Active Port Outputs Open L — — — — 95 210 90 180

(3)

Level Inputs) f = f

I

SB3 Full Standby Current Both Ports CEL and MIL S — — — — 1.0 30 1.0 30 mA

(Both Ports — All
CMOS Level Inputs) V

MAX

SEM

R =

SEM

L = VIH L 105 160 105 160 95 150 90 140

CE

R >VCC - 0.2V L — — — — 0.2 10 0.2 10

IN > VCC - 0.2V or COM S 1.0 15 1.0 15 1.0 15 1.0 15

V

IN < 0.2V, f = 0

SEM

R

=

SEM

(4)

L> VCC - 0.2V

COM S 105 190 105 190 95 180 90 170

L 0.2 5 0.2 5 0.2 5 0.2 5

(2)

Max. Typ.

(1)

(VCC = 5.0V ± 10%)

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Unit

I

SB4 Full Standby CurrentCE"A" < 0.2 and MIL S — — — — 90 225 85 200 mA

(One Port — All
CMOS Level Inputs)
V
V

CE

"B" > VCC - 0.2V

R =

SEM

SEM

IN > VCC - 0.2V or COM S 100 170 100 170 90 155 85 145
IN < 0.2V, Active Port L 100 140 100 140 90 130 85 120

(5)

L> VCC - 0.2V

L — — — — 90 200 85 170

Outputs Open,

(3)

f = f

NOTES: 2740 tbl 09

1. "X" in part numbers indicates power rating (S or L).

2. V

CC = 5V, TA = +25°C, and are not production tested. ICC DC = 120mA (typ.)

3. At f = f

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

MAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input levels of GND to 3V.

MAX

6.15 5

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Test Mil. Only

Symbol Parameter Condition Version Typ.

CC Dynamic Operating

I

Current
(Both Ports Active) f = f

SB1 Standby Current

I

(Both Ports — TTL
Level Inputs) f = f

SB2 Standby Current

I

(One Port — TTL Active Port Outputs Open L 85 160 85 160 80 160
Level Inputs) f = f

I

SB3 Full Standby Current Both Ports CEL and MIL. S 1.0 30 1.0 30 1.0 30 mA

(Both Ports — All
CMOS Level Inputs) V

SB4 Full Standby Current

I

(One Port — All
CMOS Level Inputs)

NOTES: 2740 tbl 10

1. "X" in part numbers indicates power rating (S or L).

CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (typ.)

2. V

3. At f = f

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

MAX, address and I/O'S are cycling at the maximum frequency read cycleof 1/tRC, and using “AC Test Conditions”of input levels of GND to 3V.

CE

= VIL, Outputs Open MIL. S 150 300 150 300 140 300 mA

SEM

= V

IH L 150 250 150 250 140 250

(3)

MAX

COM’L. S 150 250 150 250 — —

L 150 210 150 210 — —

CE

L = CER = VIH MIL. S 13 80 13 80 10 80 mA

SEM

R =

SEM

L = VIH L13 65 13651065

(3)

MAX

COM’L. S 13 60 13 60 — —

L13 50 13 50 — —

(4)

(5)

(5)

MIL. S 85 190 85 190 80 190 mA

COM’L. S 85 155 85 155 — —

L 0.2 5 0.2 5 — —

L 80 150 80 150 75 150

CE

"A"=VIL and CE"B"=VIH

(3)

MAX

R =

SEM

SEM

CE

R > VCC - 0.2V L 0.2 10 0.2 10 0.2 10

IN > VCC - 0.2V or COM’L. S 1.0 15 1.0 15 — —

V

IN < 0.2V, f = 0

SEM

R =

CE

"A" < 0.2 and MIL. S 80 175 80 175 75 175 mA

CE

"B" > VCC - 0.2V

R =

SEM

V

IN > VCC - 0.2V or COM’L. S 80 135 80 135 — —
IN < 0.2V, L 80 110 80 110 — —

V

L = VIH L 85 130 85 130 — —

SEM

L > VCC - 0.2V

SEM

L > VCC - 0.2V

Active Port Outputs Open,

(3)

f = f

MAX

(1)

(Cont.) (VCC = 5.0V ± 10%)

7024X35 7024X55 7024X70

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Unit

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)

(VLC = 0.2V, VHC = VCC - 0.2V)

Symbol Parameter Test Condition Min. Typ.

DR VCC for Data Retention VCC = 2V 2.0 — — V

V

CCDR Data Retention Current

I

(3)

CDR

t

(3)

R

t

NOTES: 2740 tbl 11

1. TA = +25°C, VCC = 2V, and are by characterization but are not production tested.

2. t

RC = Read Cycle Time

3. This parameter is guaranteed by device characterization but are not production tested.

. At Vcc < 2.0V, input leakages are not defined.

4

Chip Deselect to Data Retention Time
Operation Recovery Time tRC

(4)

(1)

Max. Unit

CE

> VHC MIL. — 100 4000 µA

IN > VHC or < VLC COM’L. — 100 1500

V

SEM

> VHC 0——ns

(2)

——ns

DATA RETENTION WAVEFORM

DATA RETENTION MODE

≥

V

V

CC

CE

V

t

CDR

IH

4.5V

DR

2V

V

DR

6.15 6

4.5V
t

R

V

IH

2740 drw 05