Integrated Device Technology Inc IDT7024S15PF, IDT7024S17F, IDT7024S17G, IDT7024S17J, IDT7024S17PF Datasheet

Integrated Device Technology, Inc.

HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM

IDT7024S/L

FEATURES:

• True Dual-Ported memory cells which allow simulta­neous access of the same memory location

• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial: 15/17/20/25/35/55ns (max.)

• Low-power operation
— IDT7024S

Active: 750mW (typ.)
Standby: 5mW (typ.)

— IDT7024L

Active: 750mW (typ.)
Standby: 1mW (typ.)

• Separate upper-byte and lower-byte control for
multiplexed bus compatibility

• IDT7024 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading

FUNCTIONAL BLOCK DIAGRAM

W

L

R/

UB

L

more than one device

•M/S = H for
M/S = L for

BUSY

output flag on Master

BUSY

input on Slave

• Busy and Interrupt Flags

• On-chip port arbitration logic

• Full on-chip hardware support of semaphore signaling
between ports

• Devices are capable of withstanding greater than 2001V

electrostatic discharge.

• Fully asynchronous operation from either port

• Battery backup operation—2V data retention

• TTL-compatible, single 5V (±10%) power supply

• Available in 84-pin PGA, 84-pin quad flatpack, 84-pin
PLCC, and 100-pin Thin Quad Plastic Flatpack

• Industrial temperature range (–40°C to +85°C) is avail­able, tested to military electrical specifications

W

R

R/

UB

R

NOTES:

1. (MASTER):

BUSY

is output;
(SLAVE):
is input.

2.

BUSY

outputs

and

INT

outputs
are non-tri-stated
push-pull.

BUSY

I/O8L-I/O

I/O0L-I/O

BUSY

LB
CE
OE

A

A

SEM
INT

15L

(1,2)
L

11L

L
L
L

I/O

12

Control

MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

M/

S

7L

Address

0L

L

(2)

L

Decoder

CE
OE

R/

W

L
L
L

I/O

Control

Address
Decoder

12

CE

R

OE

R

R/

W

R

LB

R

CE

R

OE

R

I/O8R-I/O

I/O0R-I/O

BUSY

A

11R

A

0R

SEM

R
(2)

INT

R

2740 drw 01

R

15R

7R

(1,2)

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-2740/6

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.15

1

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DESCRIPTION:

The IDT7024 is a high-speed 4K x 16 Dual-Port Static
RAM. The IDT7024 is designed to be used as a stand-alone
64K-bit Dual-Port RAM or as a combination MASTER/SLAVE
Dual-Port RAM for 32-bit or more word systems. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or
wider memory system applications results in full-speed, error­free operation without the need for additional discrete logic.

This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by chip
enable ( CE ) permits the on-chip circuitry of each port to enter

PIN CONFIGURATIONS

6L

3L

5L

INDEX

I/O

I/O
I/O
I/O
I/O
I/O

GND
I/O
I/O

V

GND

I/O
I/O
I/O

V
I/O
I/O
I/O
I/O
I/O
I/O

7L

I/O

I/O

11109876543218483

8L

12

9L

13

10L

14

11L

15

12L

16

13L

17
18

14L

19

15L

20

CC

21
22

0R

23

1R

24

2R

25

CC

26

3R

27

4R

28

5R

29

6R

30

7R

31

8R

32

33 34 35 36 37 38 39 40 41 42 43 44 45

9R

11R

10R

I/O

I/O

I/O

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

I/O

12R

I/O

4L

I/O

13R

I/O

I/O

14R

I/O

2L

I/O

GND

GND

15R

I/O

(1,2)

L

1L

0L

CC

I/O

OE

V

I/O

IDT7024

J84-1
F84-2

84-PIN PLCC /

FLATPACK

TOP VIEW

R

R

W

OE

GND

R/

L

L

L

L

SEM

CE

UB

L

N/C

LB

W

R/

82 81 80 79 78 77 76 75

(3)

46 47 48 49 50 51 52 53

R

R

R

R

SEM

CE

UB

11R

N/C

LB

A

10R

A

11L

A

10L

9L

8L

A

A

A

A

7L

74

A

6L

73

A

5L

72

A

4L

71

A

3L

70

A

2L

69

A

1L

68

A

0L

67

INT

L

66

BUSY

65

GND

64
63

M/

S

62

BUSY

61

INT

R

60

A

0R

59

A

1R

58

A

2R

57

A

3R

56

A

4R

A

5R

55

A

6R

54

2740 drw 02

9R

7R

8R

A

A

A

a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technol
ogy, these devices typically operate on only 750mW of power.
Low-power (L) versions offer battery backup data retention
capability with typical power consumption of 500µW from a 2V
battery.

The IDT7024 is packaged in a ceramic 84-pin PGA, an 84­pin quad flatpack, an 84-pin PLCC, and a 100-pin TQFP.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited
to military temperature applications demanding the highest
level of performance and reliability.

L

R

Index

I/O
I/O
I/O
I/O

GND
I/O
I/O

GND

I/O
I/O
I/O

I/O
I/O
I/O
I/O

9L

8L

7L

6L

5L

I/O

I/O

I/O

I/O

I/O

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

N/C

1

N/C

2

N/C

3

N/C

4

10L

5

11L

6

12L

7

13L

8
9

14L

10

15L

11

V

CC

12
13

0R

14

1R

15

2R

16

V

CC

17

3R

18

4R

19

5R

20

6R

21

N/C

22

N/C

23

N/C

24

N/C

25

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

7R

8R

9R

10R

11R

I/O

I/O

I/O

I/O

I/O

4L

I/O

12R

I/O

3L

I/O

13R

I/O

2L

I/O

14R

I/O

1L

I/O

GND

TOP VIEW

15R

GND

I/O

L

0L

I/O

OE

IDT7024
PN100-1

100-PIN

TQFP

R

R

W

OE

R/

CC

V

GND

L

W

R/

(3)

R

SEM

L

SEM

R

CE

L

CE

R

UB

L

UB

R

LB

L

LB

N/C

N/C

11R

A

11L

A

10R

A

10L

A

9R

A

9L

8L

7L

6L

A

A

A

A

75
74

73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

2740 drw 03

6R

5R

8R

7R

A

A

A

A

N/C
N/C
N/C
N/C
A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

INT

BUSY

GND
M/

S

BUSY

INT

A

0R

A

1R

A

2R

A

3R

A

4R

N/C
N/C
N/C
N/C

L

L

R

R

6.15 2

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS (CONT'D)

63 61 60 58 55 54 51 48 46 45

11

66

10

I/O

67

09

I/O

69

08

I/O

72

07

I/O

75

06

76

05

79

04

81

03

82

02

84346915131618

01

I/O

I/O

7L

5L

I/O4LI/O2LI/O

64

62

10L

I/O8LI/O6LI/O3LI/O

65

11L

I/O

9L

68

13L

I/O

12L

71

73

15L

I/O

14L

V

70

74

GND

I/O

I/O

I/O

11R

GND

78

V

2R

4R

7R

9R

I/O

I/O

I/O

0R

77

I/O

1R

80

I/O

3R

83

I/O

5R

125

I/O6RI/O

I/O8RI/O

CC

CC

(1,2)

A

0L

59 56 49 50 40

1L

57 53 52

GND

IDT7024

84-PIN PGA

TOP VIEW

7

81110

10R

I/O

13R

I/O

15R

12R

I/O

14R

OERLB

SEM

OE

L

UB

L

V

CC

G84-3

(3)

12

SEM

GNDGND

14 17 20

R

R/

W

R

R/

UB

CE

CE

L

L

W

L

R

R

R

LB

47 44

N/C

A

N/C

L

11R

11L

A

9L

33 35

BUSY

L

32 31

GND

28 29

A

0R

A

8R

A

10R

A

10L

43

A

8L

41

A

6L

38

A

3L

A

0L

M/

S

INT

R

26

A

2R

23

A

5R

22 24

A

6R

19 21

A

9R

42

A

7L

A

5L

39

A

4L

37

A

2L

34

INT

36

A

1L

30

BUSY

27

A

1R

25

A

3R

A

4R

A

7R

L

R

ABCDEFGHJ KL

Index

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

PIN NAMES

Left Port Right Port Names

CE

L

R/

W

L R/WR Read/Write Enable

OE

L

A

0L – A11L A0R – A11R Address

I/O

0L – I/O15L I/O0R – I/O15R Data Input/Output

SEM

L

UB

L

LB

L

INT

L

BUSY

L

CE

R Chip Enable

OE

R Output Enable

SEM

R Semaphore Enable

UB

R Upper Byte Select

LB

R Lower Byte Select

INT

R Interrupt Flag

BUSY

R Busy Flag

M/

S

V

CC Power

Master or Slave Select

GND Ground

2740 tbl 1

2740 drw 04

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND V

Military –55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%

CC

2740 tbl 02

6.15 3

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL

(1)

Inputs

CECE

CE

CECE

R/

WW

W

WW

OEOE

OE

OEOE

UBUB

UB

UBUB

LBLB

LB

LBLB

SEMSEM

SEM

SEMSEM

H X X X X H High-Z High-Z Deselected: Power-Down
X X X H H H High-Z High-Z Both Bytes Deselected

L L X L H H DATA
L L X H L H High-Z DATA
L L X L L H DATA
L H L L H H D ATA
L H L H L H High-Z DATA
L H L L L H DATA

X X H X X X High-Z High-Z Outputs Disabled

NOTE: 2740 tbl 03

1. A0L — A11L are not equal to A0R — A11R.

TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL

Inputs Outputs

CECE

CE

CECE

H H L X X L DATA
X H L H H L DATA
H
X

L X X L X L — — Not Allowed
L X X X L L — — Not Allowed

NOTE:

1. There are eight semaphore flags written to via I/O

R/

WW

W

WW

u
u

OEOE

OE

OEOE

UBUB

UB

UBUB

LBLB

LB

LBLB

SEMSEM

SEM

SEMSEM

X X X L DATA
X H H L DATA

0 and read from all of the I/O's (I/O0 - I/O15). These eight semaphores are addressed by A0 - A2.

Outputs

8-15 I/O0-7 Mode

I/O

IN High-Z Write to Upper Byte Only

IN Write to Lower Byte Only

IN DATAIN Write to Both Bytes

OUT High-Z Read Upper Byte Only

OUT Read Lower Byte Only

OUT DATAOUT Read Both Bytes

(1)

8-15 I/O0-7 Mode

I/O

OUT DATAOUT Read Semaphore Flag Data Out
OUT DATAOUT Read Semaphore Flag Data Out

IN DATAIN Write I/O0 into Semaphore Flag
IN DATAIN Write I/O0 into Semaphore Flag

2740 tbl 04

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

V

TERM

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND

T

A Operating 0 to +70 –55 to +125 °C

Temperature

T

BIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

STG Storage –55 to +125 –65 to +150 °C

T

Temperature

I

OUT DC Output 50 50 mA

Current

NOTES: 2740 tbl 05

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. V

TERM must not exceed Vcc +0.5V for more than 25% of the cycle time or

10ns maximum, and is limited to

.

+ 0.5V

< 20ma for the period over VTERM > Vcc

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CC Supply Voltage 4.5 5.0 5.5 V

V
GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.2 — 6.0

V
V

IL Input Low Voltage –0.5

NOTES: 2740 tbl 06

1. VIL > -1.5V for pulse width less than 10ns.

TERM must not exceed Vcc + 0.5V.

2. V

CAPACITANCE

(1)

(1)

— 0.8 V

(TA = +25°C, F = 1.0MHZ) TQFP ONLY

Symbol Parameter Condition

IN Input Capacitance VIN = 3dV 9 pF

C

OUT Output Capacitance VOUT = 3dV 10 pF

C

NOTES: 2740 tbl 07

1. This parameter are determined by device characterization, but is not
production tested.

2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.

(2)

(2)

Max. Unit

V

6.15 4

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

LI| Input Leakage Current

|I

LO| Output Leakage Current

|I

OL Output Low Voltage IOL = 4mA — 0.4 — 0.4 V

V

OH Output High Voltage IOH = -4mA 2.4 — 2.4 — V

V

NOTE:

1. At Vcc

< 2.0V input leakages are undefined.

(1)

VCC = 5.5V, VIN = 0V to VCC —10—5µA

CE

= VIH, VOUT = 0V to VCC —10—5µA

(VCC = 5.0V ± 10%)

IDT7024S IDT7024L

2740 tbl 08

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

7024X15 7024X17 7024X20 7024X25

Test Com'l. Only Com'l. Only

Symbol Parameter Condition Version Typ.

CC Dynamic Operating

I
Current

(Both Ports Active) f = f

CE

"A"=VIL, Outputs Open MIL S — — — — 160 370 155 340 mA

SEM

= V

IH L — — — — 160 320 155 280

(3)

MAX

COM S 170 310 170 310 160 290 155 265

L 170 260 170 260 160 240 155 220

I

SB1 Standby Current CER = CEL = VIH MIL S — — — — 20 90 16 80 mA

(Both Ports — TTL
Level Inputs) f = f

SEM

R =

MAX

SEM

L = VIH L————20701665

(3)

COMS2060206020601660

L2050205020501650

I

SB2 Standby Current

CE

"A"=VIL and CE"B"=VIL

(5)

MIL S — — — — 95 240 90 215 mA

(One Port — TTL Active Port Outputs Open L — — — — 95 210 90 180

(3)

Level Inputs) f = f

I

SB3 Full Standby Current Both Ports CEL and MIL S — — — — 1.0 30 1.0 30 mA

(Both Ports — All
CMOS Level Inputs) V

MAX

SEM

R =

SEM

L = VIH L 105 160 105 160 95 150 90 140

CE

R >VCC - 0.2V L — — — — 0.2 10 0.2 10

IN > VCC - 0.2V or COM S 1.0 15 1.0 15 1.0 15 1.0 15

V

IN < 0.2V, f = 0

SEM

R

=

SEM

(4)

L> VCC - 0.2V

COM S 105 190 105 190 95 180 90 170

L 0.2 5 0.2 5 0.2 5 0.2 5

(2)

Max. Typ.

(1)

(VCC = 5.0V ± 10%)

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Unit

I

SB4 Full Standby CurrentCE"A" < 0.2 and MIL S — — — — 90 225 85 200 mA

(One Port — All
CMOS Level Inputs)
V
V

CE

"B" > VCC - 0.2V

R =

SEM

SEM

IN > VCC - 0.2V or COM S 100 170 100 170 90 155 85 145
IN < 0.2V, Active Port L 100 140 100 140 90 130 85 120

(5)

L> VCC - 0.2V

L — — — — 90 200 85 170

Outputs Open,

(3)

f = f

NOTES: 2740 tbl 09

1. "X" in part numbers indicates power rating (S or L).

2. V

CC = 5V, TA = +25°C, and are not production tested. ICC DC = 120mA (typ.)

3. At f = f

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

MAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input levels of GND to 3V.

MAX

6.15 5

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Test Mil. Only

Symbol Parameter Condition Version Typ.

CC Dynamic Operating

I

Current
(Both Ports Active) f = f

SB1 Standby Current

I

(Both Ports — TTL
Level Inputs) f = f

SB2 Standby Current

I

(One Port — TTL Active Port Outputs Open L 85 160 85 160 80 160
Level Inputs) f = f

I

SB3 Full Standby Current Both Ports CEL and MIL. S 1.0 30 1.0 30 1.0 30 mA

(Both Ports — All
CMOS Level Inputs) V

SB4 Full Standby Current

I

(One Port — All
CMOS Level Inputs)

NOTES: 2740 tbl 10

1. "X" in part numbers indicates power rating (S or L).

CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (typ.)

2. V

3. At f = f

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

MAX, address and I/O'S are cycling at the maximum frequency read cycleof 1/tRC, and using “AC Test Conditions”of input levels of GND to 3V.

CE

= VIL, Outputs Open MIL. S 150 300 150 300 140 300 mA

SEM

= V

IH L 150 250 150 250 140 250

(3)

MAX

COM’L. S 150 250 150 250 — —

L 150 210 150 210 — —

CE

L = CER = VIH MIL. S 13 80 13 80 10 80 mA

SEM

R =

SEM

L = VIH L13 65 13651065

(3)

MAX

COM’L. S 13 60 13 60 — —

L13 50 13 50 — —

(4)

(5)

(5)

MIL. S 85 190 85 190 80 190 mA

COM’L. S 85 155 85 155 — —

L 0.2 5 0.2 5 — —

L 80 150 80 150 75 150

CE

"A"=VIL and CE"B"=VIH

(3)

MAX

R =

SEM

SEM

CE

R > VCC - 0.2V L 0.2 10 0.2 10 0.2 10

IN > VCC - 0.2V or COM’L. S 1.0 15 1.0 15 — —

V

IN < 0.2V, f = 0

SEM

R =

CE

"A" < 0.2 and MIL. S 80 175 80 175 75 175 mA

CE

"B" > VCC - 0.2V

R =

SEM

V

IN > VCC - 0.2V or COM’L. S 80 135 80 135 — —
IN < 0.2V, L 80 110 80 110 — —

V

L = VIH L 85 130 85 130 — —

SEM

L > VCC - 0.2V

SEM

L > VCC - 0.2V

Active Port Outputs Open,

(3)

f = f

MAX

(1)

(Cont.) (VCC = 5.0V ± 10%)

7024X35 7024X55 7024X70

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Unit

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)

(VLC = 0.2V, VHC = VCC - 0.2V)

Symbol Parameter Test Condition Min. Typ.

DR VCC for Data Retention VCC = 2V 2.0 — — V

V

CCDR Data Retention Current

I

(3)

CDR

t

(3)

R

t

NOTES: 2740 tbl 11

1. TA = +25°C, VCC = 2V, and are by characterization but are not production tested.

2. t

RC = Read Cycle Time

3. This parameter is guaranteed by device characterization but are not production tested.

. At Vcc < 2.0V, input leakages are not defined.

4

Chip Deselect to Data Retention Time
Operation Recovery Time tRC

(4)

(1)

Max. Unit

CE

> VHC MIL. — 100 4000 µA

IN > VHC or < VLC COM’L. — 100 1500

V

SEM

> VHC 0——ns

(2)

——ns

DATA RETENTION WAVEFORM

DATA RETENTION MODE

≥

V

V

CC

CE

V

t

CDR

IH

4.5V

DR

2V

V

DR

6.15 6

4.5V
t

R

V

IH

2740 drw 05

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns Max.
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load Figures 1 and 2

2740 tbl 12

DATA

BUSY

OUT

INT

5V

1250Ω

30pF775Ω

DATA

5V

1250Ω

OUT

5pF775Ω

Figure 1. AC Output Test Load Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

Including scope and Jig

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

IDT7024X15 IDT7024X17 IDT7024X20 IDT7024X25
Com'l. Only Com'l. Only

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE

RC Read Cycle Time 15 — 17 — 20 — 25 — ns

t

AA Address Access Time — 15 — 17 — 20 — 25 ns

t

(1, 2)

(1, 2)

(3)
(3)

(3)

(1,2)

OE

— 15 — 17 — 20 — 25 ns
— 15 — 17 — 20 — 25 ns

3 — 3 — 3 — 3 — ns

— 10 — 10 — 12 — 15 ns

0 — 0 — 0 — 0 — ns

(1,2)

— 15 — 17 — 20 — 25 ns

or

SEM

) 10 — 10 — 10 — 10 — ns

— 15 — 17 — 20 — 25 ns

ACE Chip Enable Access Time

t

ABE Byte Enable Access Time

t

AOE Output Enable Access Time — 10 — 10 — 12 — 13 ns

t

OH Output Hold from Address Change 3 — 3 — 3 — 3 — ns

t

LZ Output Low-Z Time

t
t

HZ Output High-Z Time
PU Chip Enable to Power Up Time

t
t

PD Chip Disable to Power Down Time

t

SOP Semaphore Flag Update Pulse (
SAA Semaphore Address Access

t

(4)

2740 drw 06

IDT7024X35 IDT7024X55 IDT7024X70

Mil. Only

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
READ CYCLE

RC Read Cycle Time 35 — 55 — 70 — ns

t

AA Address Access Time — 35 — 55 — 70 ns

t

(1, 2)

(1, 2)

= VIL, and

(3)
(3)

(1,2)

(1,2)

OE

or

SEM

) 15—15—15—ns

(3)

SEM

=VIH. To access semaphore, CE = VIH or UB &

6.15 7

—35—55—70ns
—35—55—70ns

3—3—3—ns

—15—25—30ns

0—0—0—ns

—35—50—50ns

—35—55—70ns

LB

= VIH, and

SEM

=VIL.

ACE Chip Enable Access Time

t
t

ABE Byte Enable Access Time
AOE Output Enable Access Time — 20 — 30 — 35 ns

t
t

OH Output Hold from Address Change 3 — 3 — 3 — ns

t

LZ Output Low-Z Time
HZ Output High-Z Time

t
t

PU Chip Enable to Power Up Time

t

PD Chip Disable to Power Down Time
SOP Semaphore Flag Update Pulse (

t
t

SAA Semaphore Address Access

NOTES: 2740 tbl 13

1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V

4. "X" in part numbers indicates power rating (S or L).

IL,

UB

or

LB

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

WAVEFORM OF READ CYCLES

ADDR

t
t

t

t

UB, LB

DATA

BUSY

OE

R/

OUT

OUT

CE

W

(5)

AA
ACE

AOE

t

ABE

LZ

(4)

(1)

(4)

(4)

(4)

t

RC

t

OH

(4)

(2)

t

HZ

2740 drw 07

t

BDD

VALID DATA

(3, 4)

NOTES:

1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.

2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.

BDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations

3. t

BUSY

4. Start of valid data depends on which timing becomes effective last

5.

has no relation to valid output data.

= V

IH.

SEM

tABE, tAOE, tACE, tAA or tBDD.

TIMING OF POWER-UP POWER-DOWN

CE

t

I

CC

I

SB

PU

50% 50%

t

PD

2740 drw 08

6.15 8

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

IDT7024X15 IDT7024X17 IDT7024X20 IDT7024X25

Com'l. Only Com'l. Only

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE

WC Write Cycle Time 15 — 17 — 20 — 25 — ns

t

EW Chip Enable to End-of-Write

t

AW Address Valid to End-of-Write 12 — 12 — 15 — 20 — ns

t

AS Address Set-up Time

t

WP Write Pulse Width 12 — 12 — 15 — 20 — ns

t

WR Write Recovery Time 0 — 0 — 0 — 0 — ns

t

DW Data Valid to End-of-Write 10 — 10 — 15 — 15 — ns

t

HZ Output High-Z Time

t

DH Data Hold Time

t

WZ Write Enable to Output in High-Z

t

OW Output Active from End-of-Write

t

SWRD

t

SPS

t

SEM

Flag Write to Read Time 5 — 5 — 5 — 5 — ns

SEM

Flag Contention Window 5 — 5 — 5 — 5 — ns

(1, 2)

(4)

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE

WC Write Cycle Time 35 — 55 — 70 — ns

t

EW Chip Enable to End-of-Write

t

AW Address Valid to End-of-Write 30 — 45 — 50 — ns

t

AS Address Set-up Time

t

WP Write Pulse Width 25 — 40 — 50 — ns

t

WR Write Recovery Time 0 — 0 — 0 — ns

t

DW Data Valid to End-of-Write 15 — 30 — 40 — ns

t

(4)

UB

or LB = VIL,

(1, 2)

t

HZ Output High-Z Time

t

DH Data Hold Time
WZ Write Enable to Output in High-Z

t
t

OW Output Active from End-of-Write

t

SWRD
SPS

t

NOTES: 2740 tbl 14

1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V
for the entire t

4. The specification for t
over voltage and temperature, the actual t

5. "X" in part numbers indicates power rating (S or L).

SEM

Flag Write to Read Time 5 — 5 — 5 — ns

SEM

Flag Contention Window 5 — 5 — 5 — ns

EW time.

IL,

DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary

(3)

(3)

12 — 12 — 15 — 20 — ns

0 — 0—0—0—ns

— 10 — 10 — 12 — 15 ns

0 — 0—0—0—ns

(1, 2)

(1, 2, 4)

(3)

(3)

(1, 2)

(1, 2, 4)

SEM

= VIH. To access semaphore, CE = VIH or UB & LB = VIH, and

DH will always be smaller than the actual tOW.

— 10 — 10 — 12 — 15 ns

0 — 0—0—0—ns

(5)

IDT7024X35 IDT7024X55 IDT7024X70

Mil. Only

30 — 45 — 50 — ns

0—0—0—ns

—15—25—30ns

0—0—0—ns

—15—25—30ns

0—0—0—ns

SEM

= VIL. Either condition must be valid

6.15 9

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/

t

WC

ADDRESS

OE

t

AW

(2)

t

WP

(7)

t

WZ

CE

UB

DATA

or

SEM

or

R/

DATA

LB

W

OUT

(9)

(9)

(6)

t

AS

(4) (4)

IN

WW

W

CONTROLLED TIMING

WW

(3)

t

WR

t

OW

t

DW

t

DH

(1,5,8)

t

HZ

(7)

2740 drw 09

TIMING WAVEFORM OF WRITE CYCLE NO. 2,

t

WC

CECE

CE

CECE

,

UBUB

UB

UBUB

LBLB

,

LB

CONTROLLED TIMING

LBLB

(1,5)

ADDRESS

t

AW

SEM

LB

R/

IN

(9)

t

WR

(3)

(9)

(6)

t

AS

t

EW

(2)

W

t

DW

EW or tWP) of a Low

CE

or R/W (or

SEM

Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.

DW. If

WP .

UB

or LB and a Low CE and a Low R/W for memory array writing cycle.

SEM

or R/W) going High to the end-of-write cycle.

UB,

or LB.

OE

is High during an R/W controlled write cycle, this requirement does not apply and the write pulse

SEM

= VIH. To access Semaphore, CE = VIH or UB & LB = VIH, and

WP for (tWZ + tDW) to allow the I/O drivers to turn off and data

t

DH

SEM

2740 drw 10

= VIL. tEW must be

CE

or

UB

or

DATA

NOTES:

1. R/W or CE or UB & LB must be High during all address transitions.

2. A write occurs during the overlap (t

WR is measured from the earlier of

3. t

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or

6. Timing depends on which enable signal is asserted last, CE, R/W,

7. This parameter is guaranted by device characterization, but is not production tested. Transition is measured +/- 500mV steady state with the Output Test
Load (Figure 2).

8. If OE is Low during R/W controlled write cycle, the write pulse width must be the larger of t

to be placed on the bus for the required t
can be as short as the specified t

9. To access RAM, CE = VIL, UB or LB = VIL, and

met for either condition.

6.15 10

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE

t

t

SAA

A0-A

SEM

I/O

R/

2

0

W

VALID ADDRESS

t

AW

t

EW

DATA

VALID

t

AS

t

WP

t

t

WR

DW

VALID ADDRESS

t

ACE

t

SOP

IN

t

DH

t

SWRD

t

OE

Read CycleWrite Cycle

NOTES:

1.CE = V

2. "DATA

IH or

UB

OUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.

& LB = VIH for the duration of the above timing (both write and read cycle).

TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION

DATA

AOE

(1,3,4)

OUT

VALID

OH

(2)

2740 drw 11

(1)

A

0"A"-A2"A"

(2)

SIDE

SIDE

NOTES:

1. D

0R = D0L = VIL, CER = CEL = VIH, or both

2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/

SPS is not satisfied, there is no guarantee which side will be granted the Semaphore flag.

4. If t

(2)

“A”

“B”

R/

SEM

A

0"B"-A2"B"

R/

SEM

W

W

W

A or

"A"

"A"

"B"

"B"

UB

SEM

MATCH

t

SPS

MATCH

2740 drw 12

& LB = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.

A going High to R/WB or

SEM

B going High.

6.15 11

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

IDT7024X15 IDT7024X17 IDT7024X20 IDT7024X25

Com'l Only Com'l Only

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

BUSY TIMING (M/

BAA

t

BDA

t

BAC

t

BDC

t

APS Arbitration Priority Set-up Time

t

BDD

t

WH Write Hold After

t

BUSY TIMING (M/

WB

t

WH Write Hold After

t

PORT-TO-PORT DELAY TIMING

t

WDD Write Pulse to Data Delay
DDD Write Data Valid to Read Data Delay

t

SS

S

= V

IH)

SS

BUSY

Access Time from Address Match — 15 — 17 — 20 — 20 ns

BUSY

Disable Time from Address Not Matched — 15 — 17 — 20 — 20 ns

BUSY

Access Time from Chip Enable Low — 15 — 17 — 20 — 20 ns

BUSY

Disable Time from Chip Enable High — 15 — 17 — 17 — 17 ns

BUSY

Disable to Valid Data

SS

S

= V

IL)

SS

BUSY

Input to Write

BUSY

(4)

BUSY

(2)

(3)

(5)

(5)

(1)

(1)

5 —5—5—5—ns

—18—18—30—30ns

12 — 13 — 15 — 17 — ns

0—0—0—0—ns

12 — 13 — 15 — 17 — ns

—30—30—45—50ns
—25—25—35—35ns

(6)

IDT7024X35 IDT7024X55 IDT7024X70

Mil. Only

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

SS

BUSY TIMING (M/

BAA

t

BDA

t

BAC

t

BDC

t

APS Arbitration Priority Set-up Time

t
t

BDD

t

WH Write Hold After

BUSY
BUSY
BUSY
BUSY

BUSY

BUSY TIMING (M/

WB

t

WH Write Hold After

t

BUSY

IH)

S

= V

SS

Access Time from Address Match — 20 — 45 — 45 ns
Disable Time from Address Not Matched — 20 — 40 — 40 ns
Access Time from Chip Enable Low — 20 — 40 — 40 ns
Disable Time from Chip Enable High — 20 — 35 — 35 ns

Disable to Valid Data

(5)

BUSY

SS

IL)

S

= V

SS

Input to Write

(4)

BUSY

(5)

(2)

(3)

5—5—5—ns
—35—40—45ns
25 — 25 — 25 — ns

0—0—0—ns
25 — 25 — 25 — ns

PORT-TO-PORT DELAY TIMING

WDD Write Pulse to Data Delay

t

DDD Write Data Valid to Read Data Delay

t

NOTES: 2740 tbl 15

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With
of Write With Port-To-Port Delay (M/S = V

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0ns, t

4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".

5. To ensure that a write cycle is completed on port "B" after contention with port "A".

6. "X" in part numbers indicates power rating (S or L).

(1)

IL)".

—60—80—95ns

(1)

WDD – tWP (actual), or tDDD – tDW (actual).

—45—65—80ns

BUSY

(M/S = VIH)" or "Timing Waveform

6.15 12

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

(2,4,5)

t

DH

t

WDD

VALID

BUSY BUSY

BUSY (M/

BUSY BUSY

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND

t

WC

t

BAA

MATCH

t

WP

t

DW

MATCH

ADDR

DATA

ADDR

DATA

R/

W

IN "A"

BUSY

OUT "B"

"A"

"A"

"B"

"B"

t

APS

(1)

t

NOTES:

1. To ensure that the earlier of the two ports wins. t

L = CER = VIL.

2.

CE

3.OE = V

4. If M/S = V

5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".

IL for the reading port.

IL (slave),

BUSY

is an input. Then for this example

APS is ignored for M/

BUSY

S

= VIL (slave).

"A" = VIH and

BUSY

"B" input is shown above.

DDD

(3)

SS

S

= VIH)

SS

t

BDA

t

BDD

VALID

2740 drw 13

TIMING WAVEFORM OF WRITE WITH

R/

W

"A"

(3)

t

WB

BUSY

"B"

"B"

R/

W

NOTES:

WH must be met for both

1. t

2. Busy is asserted on port "B" Blocking R/W"B", until

WB is only for the Slave Version.

3. t

BUSY

input (slave) and output (master).

BUSY

BUSYBUSY

BUSY

BUSYBUSY

t

WP

(2)

"B" goes High.

t

WH

(1)

2740 drw 14

6.15 13

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

WAVEFORM OF BUSY ARBITRATION CONTROLLED BY

ADDR

and

CE

CE

BUSY

"A"
"B"

"A"

"B"

"B"

t

APS

(2)

ADDRESSES MATCH

t

BAC

CECE

CE

TIMING (M/

CECE

t

BDC

SS

S

= VIH)

SS

(1)

2740 drw 14

WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING

"A"

"B"

IH)

(1)

t

APS

ADDRESS "N"

(2)

MATCHING ADDRESS "N"

t

BAA

t

BDA

(M/

SS

S

= V

SS

ADDR

ADDR

BUSY

"B"

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If t

APS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.

2740 drw 16

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

IDT7024X15 IDT7024X17 IDT7024X20 IDT7024X25

Com'l. Only Com'l. Only

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
INTERRUPT TIMING

t

AS Address Set-up Time 0 — 0 — 0 — 0 — ns
WR Write Recovery Time 0 — 0 — 0 — 0 — ns

t

INS Interrupt Set Time — 15 — 15 — 20 — 20 ns

t

INR Interrupt Reset Time — 15 — 15 — 20 — 20 ns

t

IDT7024X35 IDT7024X55 IDT7024X70

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
INTERRUPT TIMING

t

AS Address Set-up Time 0 — 0 — 0 — ns
WR Write Recovery Time 0 — 0 — 0 — ns

t

INS Interrupt Set Time — 25 — 40 — 50 ns

t

INR Interrupt Reset Time — 25 — 40 — 50 ns

t

NOTE: 2740 tbl 16

1. "X" in part numbers indicates power rating (S or L).

(1)

Mil. Only

6.15 14

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

WAVEFORM OF INTERRUPT TIMING

ADDR

CE

R/

W

INT

ADDR"B"

CE

"B"

OE

"B"

"A"

"A"

"A"

"B"

t

AS

tAS

(3)

INTERRUPT SET ADDRESS

(3)

t

INS

INTERRUPT CLEAR ADDRESS

(3)

(3)

tINR

(1)

t

WC

tRC

(2)

(2)

t

WR

(4)

2740 drw 17

INT

"B"

2740 drw 18

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. See Interrupt truth table.

3. Timing depends on which enable signal (

4. Timing depends on which enable signal (

CE

or R/W ) is asserted last.

CE

or R/W ) is de-asserted first.

TRUTH TABLES
TRUTH TABLE III — INTERRUPT FLAG

Left Port Right Port

CECE

WW

CE

L

R/

W

CECE

WW

LL XFFFXXXXXL
X X X X X X L L FFF H
XXXXL
X L L FFE H

NOTES: 2740 tbl 17

1. Assumes

2. If

3. If

4.

INT

BUSY

L = VIL, then no change.

BUSY
BUSY

R = VIL, then no change.

R and

INT

OEOE

OE

L

L =

L must be initialized at power-up.

OEOE

BUSY

L A11L-A0L

R = VIH.

INTINT

INT

INTINT

(3)

(2)

L R/

(1,4)

CECE

WW

CE

W

R

CECE

WW

L L X FFE X Set Left

OEOE

OE

R

R A11R-A0R

OEOE

INTINT

INT

R Function

INTINT

(2)

Set Right

(3)

Reset Right

INT

XXXXXReset Left

INT

INT

R Flag

INT

L Flag

L Flag

R Flag

6.15 15

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE IV —
ADDRESS BUSY ARBITRATION

Inputs Outputs

0L-A11L

A

CECE

CECE

CE

CE

L

CECE

XX
HX
XH

LL

NOTES: 2740 tbl 16

1. Pins

IDT7024 are push pull, not open drain outputs. On slaves, the

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable

after the address and enable inputs of this port. If tAPS is not met, either
simultaneously.

3. Writes to the left port are internally ignored when

internally ignored when

R A0R-A11R

CECE

BUSY

L and

NO MATCH H H Normal

MATCH H H Normal
MATCH H H Normal
MATCH (2) (2) Write Inhibit

BUSY

R are both outputs when the part is configured as a master. Both are inputs when configured as a slave.

BUSY

(1)

BUSYBUSY

BUSY

L

BUSYBUSY

R outputs are driving low regardless of actual logic level on the pin.

BUSYBUSY

BUSY

BUSYBUSY

(1)

R

BUSY

Function

(3)

BUSY

asserted input internally inhibits write.

BUSY

L or

BUSY

R = Low will result.

L outputs are driving low regardless of actual logic level on the pin. Writes to the right port are

BUSY

L and

BUSY

X outputs on the

BUSY

R outputs cannot be low

TRUTH TABLE V — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE

(1,2)

Functions D0 - D15 Left D0 - D15 Right Status

No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024.

2. There are eight semaphore flags written to via I/O

FUNCTIONAL DESCRIPTION

The IDT7024 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7024 has an
automatic power down feature controlled by CE. The
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE High). When a port is enabled, access to the entire

0 and read from all the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.

memory location FFF (HEX) and to clear the interrupt flag
(

INT

R), the right port must access the memory location FFF.

The message (16 bits) at FFE or FFF is user-defined, since it
is an addressable SRAM location. If the interrupt function is

CE

not used, address locations FFE and FFF are not used as mail
boxes, but as part of the random access memory. Refer to
Truth Table for the interrupt operation.

memory array is permitted.

BUSY LOGIC

INTERRUPTS

If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (
writes to memory location FFE (HEX), where a write is defined
as the CE = R/W = VIL per the Truth Table. The left port clears
the interrupt by access address location FFE access when

CE

R = OER = VIL, R/

interrupt flag (

W

INT

R) is asserted when the left port writes to

INT

L) is asserted when the right port

is a "don't care". Likewise, the right port

Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.

The use of busy logic is not required or desirable for all

2740 tbl 19

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IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

MASTER

CE

Dual Port
RAM

BUSY

L

BUSY

R

MASTER

CE

Dual Port
RAM

BUSY

L

BUSY

BUSY

L

Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7024 RAMs.

R

applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/S pin. Once in slave mode the

BUSY

pin operates solely as a write inhibit input pin. Normal
operation can be programmed by tying the

BUSY

pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.

The busy outputs on the IDT 7024 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.

WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS

When expanding an IDT7024 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7024 RAM the busy pin is
an output if the part is used as a master (M/S pin = H), and the
busy pin is an input if the part used as a slave (M/S pin = L) as
shown in Figure 3.

If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.

The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an
access is a read or write. In a master/slave array, both
address and chip enable must be valid long enough for a busy
flag to be output from the master before the actual write pulse

SLAVE

CE

Dual Port
RAM

BUSY

SLAVE

L

BUSY

R

CE

DECODER

Dual Port
RAM

BUSY

L

BUSY

R

BUSY

R

2740 drw 19

can be initiated with either the R/W signal or the byte enables.
Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.

SEMAPHORES

The IDT7024 is an extremely fast Dual-Port 4K x 16 CMOS
Static RAM with an additional 8 address locations dedicated
to binary semaphore flags. These flags allow either processor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer’s software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.

The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where
and

SEM

Systems which can best use the IDT7024 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT7024's hardware semaphores, which pro­vide a lockout mechanism without requiring complex pro­gramming.

Software handshaking between processors offers the

SEM

, the semaphore enable. The CE and

are both high.

SEM

CE

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HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT7024 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.

An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.

HOW THE SEMAPHORE FLAGS WORK

The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
“Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
over the shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.

The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.

The eight semaphore flags reside within the IDT7024 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins A0 – A2. When accessing the
semaphores, none of the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communica­tions. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side

SEM

until the semaphore is freed by the first side.

When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side’s output register when that side's
semaphore select (

SEM

) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (

SEM

or OE)

to go inactive or the output will never change.

A sequence WRITE/READ must be used by the sema­phore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.

It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a sema­phore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side’s semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side’s
request latch. The second side’s flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.

The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.

One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a

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resource is secure. As with any powerful programming tech­nique, if semaphores are misused or misinterpreted, a soft­ware error can easily happen.

Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.

USING SEMAPHORES—SOME EXAMPLES

Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7024’s Dual-Port
RAM. Say the 4K x 16 RAM was to be divided into two 2K x
16 blocks which were to be dedicated at any one time to
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.

To take a resource, in this example the lower 2K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore 0. If this task were success­fully completed (a zero was read back rather than a one), the
left processor would assume control of the lower 2K. Mean­while the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore

0. At this point, the software could choose to try and gain
control of the second 2K section by writing, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.

Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and

perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 2K blocks of Dual-Port RAM with each
other.

The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be as­signed different meanings on different sides rather than being
given a common meaning as was shown in the example
above.

Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was “off-limits” to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.

Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both proces­sors can access their assigned RAM segments at full speed.

Another application is in the area of complex data struc­tures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.

L PORT

SEMAPHORE

REQUEST FLIP FLOP
D

0

D

WRITE

SEMAPHORE

READ

SEMAPHORE

REQUEST FLIP FLOP

Q

Figure 4. IDT7024 Semaphore Logic

6.15 19

Q

R PORT

D

D

0

WRITE

SEMAPHORE
READ

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IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

XXXXX

IDT

A

999

A

Device

Type

Power

SpeedAPackage

Process/

Temperature

Range

Blank
B

PF
G
J
F

15
17
20
25
35
55
70

S
L

Commercial (0°C to +70°C)
Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B
100-pin TQFP (PN100-1)

84-pin PGA (G84-3)
84-pin PLCC (J84-1)
84-pin Flatpack (F84-2)

Commercial Only
Commercial Only

Speed in nanoseconds

Military Only
Standard Power

Low Power

64K (4K x 16) Dual-Port RAM7024

2740 drw 21

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