Integrated Device Technology Inc IDT70121L25J, IDT70121L35J, IDT70121L45J, IDT70121L55J, IDT70121S25J Datasheet

Integrated Device Technology, Inc.

HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM WITH BUSY & INTERRUPT

IDT70121S/L
IDT70125S/L

FEATURES:

• High-speed access
– Commercial: 25/35/45/55ns (max.)

• Low-power operation
– IDT70121/70125S

Active: 500mW (typ.)
Standby: 5mW (typ.)

– IDT70121/70125L

Active: 500mW (typ.)
Standby: 1mW (typ.)

• Fully asychronous operation from either port

• MASTER IDT70121 easily expands data bus width to 18
bits or more using SLAVE IDT70125 chip

• On-chip port arbitration logic (IDT70121 only)

•

BUSY

output flag on Master;

•

INT

flag for port-to-port communication

BUSY

input on Slave

• Battery backup operation—2V data retention

• TTL-compatible, signal 5V (±10%) power supply

• Available in 52-pin PLCC

• Industrial temperature range (–40°C to +85°C) is avail­able, tested to military electrical specifications

FUNCTIONAL BLOCK DIAGRAM

OE

L

CE

L

R/

W

L

DESCRIPTION:

The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port
Static RAMs. The IDT70121 is designed to be used as a
stand-alone 9-bit Dual-Port RAM or as a “MASTER” Dual-Port
RAM together with the IDT70125 “SLAVE” Dual-Port in 18­bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 18-bit-or-wider memory
system applications results in full-speed, error-free operation
without the need for additional discrete logic.

Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asyn­chronous access for reads or writes to any location in memory.
An automatic power-down feature, controlled by CE, permits
the on-chip circuitry of each port to enter a very low standby
power mode.

The IDT70121/IDT70125 utilizes a 9-bit wide data path to
allow for Data/Control and parity bits at the user’s option. This
feature is especially useful in data communications
applications where it is necessary to use a parity bit for
transmission/reception error checking.

OE

R

CE

R

R/

W

R

I/O0L- I/O

NOTES:

1. 70121 (MASTER):

BUSY

is non-tri­stated push-pull
output.
70125 (SLAVE):

BUSY

2.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

is input.

INT

is totem-pole

output.

8L

(1,2) (1,2)

BUSY

L

A

INT

10L

A

0L

(2)

L

Address
Decoder

CE
OE

R/

W

L
L
L

I/O

Control

MEMORY

ARRAY

11

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

I/O

Control

Address
Decoder

11

CE

R

OE

R

R/

W

R

2654 drw 01

I/O0R-I/O

BUSY

A

11R

A

0R

INT

R

8R

R

(2)

COMMERCIAL TEMPERATURE RANGE OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-2654/4

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.10

1

IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE

DESCRIPTION (Cont'd):

Fabricated using IDT’s CMOS high-performance

technology, these devices typically operate on only 500mW of
power. Low-power (L) versions offer battery backup data

PIN CONFIGURATIONS

NDEX

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

I/O

2L

I/O

3L

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate the orientation of the actual part-marking.

L

0L

10L

OE

A

A

7

6

8
9
10
11
12
13
14
15
16
17
18
19
20

5

2122232425262728293031

4L

6L

5L

I/O

I/O

I/O

(1,2)

L

L

L

L

W

BUSY

CE

INT

R/

3

2

4

1

IDT70121/125

J52-1

PLCC

TOP VIEW

8L

7L

0R

I/O

I/O

GND

I/O

CC

V

52

1R

I/O

R

R

R

R

W

10R

INT

CE

BUSY

A

R/

51

50

49

48

4733

46

OE

R

45

A

0R

44

A

1R

43

A

2R

42

A

3R

41

A

4R

40

A

5R

3R

I/O

4R

I/O

32

5R

I/O

39
38
37
36
35
34

6R

I/O

A
A
A
A
I/O
I/O

6R
7R
8R
9R

8R
7R

2654 drw 02

(3)

2R

I/O

retention capability with each port typically consuming 200µW
from a 2V battery.

The IDT70121/IDT70125 devices are packaged in a 52-pin

PLCC.

RECOMMENDED OPERATING TEMPERATURE
AND SUPPLY VOLTAGE

Grade Ambient Temperature GND VCC

Commercial 0°C to +70°C 0V 5.0V ± 10%

2654 tbl 02

RECOMMENDED DC
OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5 5.5 V

GND Supply Voltage 0 0 0.0 V
V

IH Input High Voltage 2.2 – 6.0
IL Input Low Voltage –0.5

V

(1)

– 0.8 V

NOTES: 2654 tbl 03

1. VIL > -1.5V for pulse width less than 10ns.

2. V

TERM must not exceed Vcc + 0.5V.

(2)

V

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Unit

(2)

V

TERM

Terminal Voltage –0.5 to +7.0 V
with Respect to GND

T

A Operating 0 to +70 °C

Temperature

T

BIAS Temperature –55 to +125 °C

Under Bias

T

STG Storage –55 to +125 °C

Temperature

I

OUT DC Output 50 mA

Current

NOTES: 2654 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.

2. V

TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or

10ns maximum, and is limited to

0.5V.

< 20mA for the period of VTERM > Vcc +

CAPACITANCE

Symbol Parameter Condition

C

IN Input Capacitance VIN = 3dV 9 pF
OUT Output Capacitance VOUT = 3dV 10 pF

C

NOTES:

(1)

(TA = +25°C, f = 1.0MHz)

(2)

Max. Unit

2654 tbl 13

1. This parameter is determined by device characterization but is not
production tested.

2. 3dV represents the interpolated capacitance when the input and output

signals switch from 0V to 3V or from 3V to 0V.

6.10 2

IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Test Condition Min. Max. Min. Max. Unit

|I

LI| Input Leakage Current

|I

LO| Output Leakage Current

VOL Output Low Voltage IOL = 4mA — 0.4 — 0.4 V
V

OH Output High Voltage IOH = –4mA 2.4 — 2.4 — V

1. At Vcc

< 2.0V leakages are undefined.

(5)

(5)

VCC = 5.5V, VIN = 0V to VCC —10 — 5µA
VCC = 5.5V, CE = VIH —10 — 5µA

OUT = 0V to VCC

V

(VCC = 5.0V ± 10%)

70121S 70121L
70125S 70125L

2654 tbl 04NOTE:

DC ELECTRICAL CHARACTERISTICS OVER THE

(1,4)

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

70121X25 70121X35 70121X45 70121X55

Test 70125X25 70125X35 70125X45 70125X55

Symbol Parameter Condition Version Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit

I

CC Dynamic Operating

Current (Both Ports f = f
Active)

SB1 Standby Current

I

(Both Ports—TTL f = f
Level Inputs)

SB2 Standby Current

I

(One Port—TTL Active Port Outputs Open, L 80 145 80 135 80 130 80 125
Level Inputs) f = f

ISB3 Full Standby

Current (Both Ports V
CMOS Level Inputs) or V

ISB4 Full Standby

Current (One Port V
CMOS Level Inputs) V

NOTES: 2654 tbl 05

1. “X” in part numbers indicates power rating (S or L).

2. At f = f

3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

4. Vcc=5V, T

5. Port "A" may be either left or right port. Port "B" is opposite from port "A".

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST

CONDITIONS” of input levels of GND to 3V.

A=+25°C for Typical values, and they are not production tested.

CE

= VIL,Outputs Open, Com’l. S 125 260 125 250 125 245 125 240 mA

(2)

MAX

CE

"A" and CE"B" = VIH, Com’l. S 30 65 30 65 30 65 30 65 mA

(2)

MAX

(3)

MAX

(2)

(5)

Com’l. S 80 175 80 165 80 160 80 155 mA

(5

)

Com’l. S 70 170 70 160 70 155 70 150 mA

CE

"A"=VIL and CE"B"=VIH

(2)

MAX

CE

"A" and CE"B" ≥ VCC – 0.2V, Com’l. S 1.0 15 1.0 15 1.0 15 1.0 15 mA

IN ≥ VCC – 0.2V L 0.2 5 0.2 5 0.2 5 0.2 5

IN ≤ 0.2V, f = 0

CE

"A"<0.2V and CE"B">VCC-0.2V

IN ≥ VCC – 0.2V or L 70 140 70 130 70 125 70 120
IN ≤ 0.2V, Active Port

Outputs Open, f = f

L 125 220 125 210 125 205 125 200

L3045304530453045

(VCC = 5V ± 10%)

6.10 3

IDT 70121/70125S/L

1250Ω

30pF775Ω

DATA

OUT

BUSY

INT

5V

5V

1250Ω

5pF775Ω

DATA

OUT

2654 drw 04

HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE

DATA RETENTION CHARACTERISTICS (L Version Only)

70121L/70125L

Symbol Parameter Test Condition Min. Typ.

V

DR VCC for Data Retention 2 — — V

I

CCDR Data Retention Current VCC = 2.0V,

(3)

CDR

t

(3)

t

R

NOTES: 2654 tbl 06

1. VCC = 2V, TA = +25°C, and are not production tested.

RC = Read Cycle Time.

2. t

3. This parameter is guaranteed by device characterization but is not production tested.

Chip Deselect to Data Retention Time VIN ≥ VCC – 0.2V or VIN ≤ 0.2V 0 — — ns
Operation Recovery Time tRC

CE

≥ VCC – 0.2V Com’l. — 100 1500 µA

(2)

(1)

Max. Unit

——ns

DATA RETENTION WAVEFORM

DATA RETENTION MODE

Vcc

CE

V

t

CDR

IH

4.5V

≥

V

DR

2V

V

DR

4.5V
t

R

V

IH

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load Figures 1 and 2

2654 tbl 07

Figure 1. AC Output Test Load

Figure 2. Output Test Load

(For tLZ, tHZ, tWZ, tOW)

Including scope and jig.

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle

t

RC Read Cycle Time 25 — 35 — 45 — 55 — ns

t

AA Address Access Time — 25 — 35 — 45 — 55 ns

t

ACE Chip Enable Access Time — 25 — 35 — 45 — 55 ns

t

AOE Output Enable Access Time — 12 — 25 — 30 — 35 ns

t

OH Output Hold from Address Change 0 — 0 — 0 — 0 — ns

t

LZ Output Low-Z Time

t

HZ Output High-Z Time

t

PU Chip Enable to Power-Up Time

t

PD Chip Disable to Power-Down Time

NOTES: 2654 tbl 08

1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter guaranteed by device characterization, but is not production tested.

3. “X” in part numbers indicates power rating (S or L).

(1,2)

(1,2)

(2)

(2)

6.10 4

(3)

70121X25 70121X35 70121X45 70121X55
70125X25 70125X35 70125X45 70125X55

0—0—0—0—ns

—10—15—20—30ns

0—0—0—0—ns

—50—50—50—50ns

2654 drw 03