IDT IDT7008S-L User Manual

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HIGH-SPEED
64K x 8 DUAL-PORT
STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous
reads of the same memory location

◆

High-speed access

– Military: 25/35/55ns (max.)
– Industrial: 55ns (max.)
– Commercial: 20/25/35/55ns (max.)

◆

Low-power operation

– IDT7008S

Active: 750mW (typ.)
Standby: 5mW (typ.)

– IDT7008L

Active: 750mW (typ.)
Standby: 1mW (typ.)

◆

Dual chip enables allow for depth expansion without
external logic

Functional Block Diagram

IDT7008S/L

◆

IDT7008 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device

◆

M/S = VIH for BUSY output flag on Master,
M/S = V

◆

◆

◆

◆

◆

◆

◆

IL for BUSY input on Slave

Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds

R/

W

L

CE

0L

CE

1L

OE

L

I/O

0-7L

(1,2)

BUSY

L

A

15L

A

0L

SEM

L

(2)

INT

L

NOTES:

1. BUSY is an input as a Slave (M/S = V

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

©2000 Integrated Device Technology, Inc.

Address
Decoder

CE

0L
1L

CE

OE

L
L

R/

W

IL) and an output when it is a Master (M/S = VIH).

Control

16 16

I/O

64Kx8

MEMORY

ARRAY

7008

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

(1)

M/

S

1

I/O

Control

Address
Decoder

CE

0R
1R

CE

OE

R

R

R/

W

R

R/

W

CE

0R

CE

1R

OE

R

3198 drw 01

I/O

0-7R

(1,2)

BUSY

R

15R

A
A

0R

R

SEM

(2)

INT

R

MAY 2000

DSC 3198/6

IDT7008S/L

,

High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Description

The IDT7008 is a high-speed 64K x 8 Dual-Port Static RAM. The
IDT7008 is designed to be used as a stand-alone 512K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error­free operation without the need for additional discrete logic.

This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (CE

0 and CE1) permit the on-chip

circuitry of each port to enter a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these

devices typically operate on only 750mW of power.

The IDT7008 is packaged in a 84-pin Ceramic Pin Grid Array (PGA),
a 84-pin Plastic Leadless Chip Carrier (PLCC) and a 100-pin Thin Quad
Flatpack (TQFP).

Pin Configurations

INDEX

6R

A

12

5R

A

13

4R

A

14

3R

A

15

A

2R

16

A

1R

17

0R

A

18

R

INT

BUSY

M/

GND

BUSY

INT

NC
A
A
A
A
A
A
A

19

R

20

S

21
22

L

23

L

24
25

0L

26

1L

27

2L

28

3L

29

4L

30

5L

31

6L

32

33 34 35 36 37 38 39 40 41 42 43 44 45

(1,2,3)

R

R

9

8

7

A

A

A

1

1

1

A

A

A

R

R

R

2

1

0

R

R

R

R

4

3

1

1

A

A

D

5

N

C

C

1

A

N

G

N

11 10 9 8 7 6 5 4 3 2 1 84 83

IDT7008J

(4)

J84-1

84-Pin PLCC

Top View

(5)

R

R
0

E

C

C

N

R

R

1

E
C

R

D

M

W

E

/

S

R

D

E

N

N

O

G

G

82 81 80 79 78 77 76 75

46 47 48 49 50 51 52 53

74
73
72
71

70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

C
N

NC

7R

I/O

6R

I/O
I/O

5R

I/O

4R
3R

I/O
Vcc

2R

I/O

1R

I/O
I/O

0R

GND
Vcc

0L

I/O

L

I/O1
GND

2L

I/O

3L

I/O

4L

I/O

5L

I/O

6L

I/O

7L

I/O

L

8

7

9

A

A

A

NOTES:

1. This text does not indicate orientation of the actual part marking.

2. All Vcc pins must be connected to power supply.

3. Package body is approximately 1.15 in x 1.15 in x .17 in.

4. This package code is used to reference the package diagram.

5. All GND pins must be connected to ground supply.

2

0

1

1

1

1

A

A

A

L

L

L

L

c

3
1

A

C

5

4

1

A

c

1

N

V

A

L

C

C

0

N

N

E
C

L

L

L
1

E
C

L

D

E

M

W

I

N

O

E

R

S

G

D
N
G

3198drw 02

C
N

L

L

L

L

2

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Pin Configurations

(1,2,3)

(con't.)

Index

A
A

A
A
A
A
A
A
A

Vcc

CE

CE

SEM

R/

OE

GND

NC
NC

7L
8L

9L
10L
11L
12L
13L
14L
15L

NC

NC
NC
NC
NC

0L

1L

W

NC
NC

L

Y

L

L

L

L

C

C

6

N

N

A

100999897 969594939291908988 8786 85848382818079 7877 76

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

L

20

L

21

L

22
23
24
25

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

L

D

C

7

N

N

O

/

G

I

L

5

4

3

A

A

A

L

L

L

6

4

5

O

O

O

/

/

/

I

I

I

L

L

L

0

1

2

A

A

A

L

L

D

2

3

N

O

O

/

/

I

G

I

S

T

U

C

N

I

B

N

IDT7008PF

PN100-1

100-Pin TQFP

Top View

L

L

c

0

1

c

O

V

O

/

/

I

I

R

Y

D
N
G

D
N
G

R

S

S

/
M

(

4)

(5)

R

0

O

/

I

R

T

U

0

N

B

I

A

c

R

R

c

1

2

V

O

O

/

/

I

I

R

R

R

3

2

1

A

A

A

R

R

4

3

O

O

/

/

I

I

R

R

R

5

4

A

A

C

C

6

N

N

A

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
NC

7R

A
A

8R
9R

A
A

10R
11R

A

12R

A

13R

A

14R

A
A

15R

NC
GND
NC
NC
NC
NC

CE

CE

SEM

W

R/

OE

GND
GND
NC

0R
1R

R

R

R

,

C
N

3198 drw 03

C
N

R

R

R

5

O

/

I

C

7

6

N

O

O

/

/

I

I

NOTES:

1. This text does not indicate orientation of the actual part marking.

2. All Vcc pins must be connected to power supply.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. All GND pins must be connected to ground supply.

6.42

3

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

(1,2,3)

Pin Configurations

(con't)

63 61 60 58 55 54 51 48 46 45

11

66

10

67

09

69

08

72

BUSY

07

75

06

BUSY

76

INT

05

79

04

81

03

82

02

84346915131618

01

A

A

A

A

A

A

A

A

A

9R

7R

64

62

A

6R

4R

65

A

5R

3R

68

A

2R

1R

73

71

R

R

INT

74

70

A

0R

L

78

77

L

NC

80

A

2L

1L

83

A

3L

5L

12578

A

7L

4L

A

9L

6L

A

A

10R

59 56 49 50 40

A

A

8R

M/

S

GND

A

0L

A

A

8L

A

A

10L

ABC DEF GHJK L

INDEX

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 1.12 in x 1.12 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

A

15R

12R

A

14R

11R

57 53 52

A

13R

84-Pin PGA
Top View

A

13L

A

14L

11L

A

15L

12L

NC

NC

0R

CE

CE

1R

NC

GND

IDT7008G

(4)

G84-3

(5)

11

12

NC

Vcc

10

14 17 20

0L

CE

NC

CE

NC

1L

Pin Names

Left Port Right Port Names

R

SEM

47 44

R/

R

W

R/

L

W

L

SEM

R

OE

GND

33 35

I/O

0R

32 31

GND

28 29

GND

GND

L

OE

GND

43

NC

41

I/O

7R

38

I/O4RI/O

I/O

2R

Vcc

I/O1

L

26

I/O

3L

23

I/O

6L

22 24

I/O

7L

19 21

GND

3198 drw 04

42

NC

I/O

6R

39

I/O

5R

37

3R

34

I/O

1R

36

Vcc

30

I/O

0L

27

I/O

2L

25

I/O

4L

I/O

5L

NC

,

4

CE

0L

W

R/

OE

L

A0L - A

0L

I/O

SEM

INT

L

BUS Y

, CE

L

- I/O

L

L

15L

1L

7L

CE

W

R/

OE

A0R - A

I/O0R - I/O

SEM

INT

BUS Y

S

M/

CC

V

0R

, CE

R

R

15R

R

R

R

GND Ground

1R

Chip Enables
Read /Wri te En able
Output Enable

Address

7R

Dat a In p ut/ O ut p ut
Semaphore Enable
Interr up t Flag
Busy Flag
Master or Slave Select
Power

3198 tbl 01

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Truth Table I: Chip Enable

1

CE CE

V

L

< 0. 2V >VCC -0.2V Po rt Se lec te d (CMOS Ac tive )

V

H

>

VCC -0.2V X Po rt Des e lec te d (CMOS Inactive )

0

IL

IH

XV

CE

IH

V

X Port Deselected (TTL Inactive)

IL

(1)

Mode

Port Selected (TTL Active)

Port Deselected (TTL Inactive)

X<

NOTES:

1. Chip Enable references are shown above with the actual CE

0.2V Po rt Deselected (CMOS Inactive)

0 and CE1 levels, CE is a reference only.

Truth Table II: Non-Contention Read/Write Control

(1)

Inputs

(2)

W

CE

R/

OE SEM

H X X H High-Z Dese le c ted : P o wer-Do wn

LLXHDATAINWrite to me mory
LHLHDATA

X X H X Hig h-Z Outputs Dis abl e d

NOTES:

0L – A15L ≠ A0R – A15R.

1. A

2. Refer to Chip Enable Truth Table.

Truth Table III: Semaphore Read/Write Control

Inputs Outputs

(2)

W

R/

CE

HHLLDATA

OE SEM

Outputs

I/O

0-7

I/O

OUT

0-7

OUT

Read me mory

Read Semaphore Flag Data Out

Mode

(1)

Mode

3198 tbl 02

3198 t bl 03

↑

H
LXXL

NOTES:

1. There are eight semaphore flags written to via I/O

2. Refer to Chip Enable Truth Table.

XLDATAINWrite I/ O0 into Semaphore Flag

______

Not Al lo wed

0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2.

6.42

5

3198 tbl 04

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings

Symbol Rating Commercial

(2)

V

TERM

Terminal Voltage
with Re s p e ct
to G ND

T

BIAS

T emperature

Unde r Bias

T

I

OUT

STG

Storage

T emperature

DC Output Current 50 50 mA

NOTES:

& Industrial

-0.5 to +7.0 -0.5 to +7.0 V

-55 to +125 -65 to +135oC

-65 to +150 -65 to +150oC

(1)

Military Unit

3198 t bl 05

Recommended DC Operating
Conditions

Symbol Parameter Min. Typ. Max. Unit

CC

V

Sup p ly Vo ltag e 4.5 5. 0 5.5 V

GND Ground 0 0 0 V

IH

V

Inp u t Hi g h Vo l ta g e 2. 2

IL

V

Input Lo w Voltag e -0.5

NOTES:

1. V

IL > -1.5V for pulse width less than 10ns.
TERM must not exceed Vcc + 10%.

2. V

____

(1)

____

(2)

6.0

0.8 V

3198 tbl 07

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.

TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

2. V
maximum, and is limited to

< 20mA for the period of VTERM > Vcc + 10%.

Maximum Operating Temperature
and Supply Voltage

Grade

Ambient

Temperature GND Vcc

(1,2)

Capacitance

(TA = +25°C, f = 1.0mhz) (TQFP Only)

)1(

ecnaticapaCtupnIV

ecnaticapaCtuptuOV

C

NI

C

TUO

lobmySretemaraP

NOTES:

1. This parameter is determined by device characterization but is not production
tested.

2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.

snoitidnoC

NI

Vd3=9Fp

TUO

Vd3=01Fp

)2(

.xaMtinU

Military -55OC to+1 25OC0V 5.0V + 10%

O

Commercial 0

C to +7 0OC0V 5.0V + 10%

Industrial -40OC to +8 5OC0V 5.0V + 10%

NOTES:

1. This is the parameter T

A. This is the "instant on" case tempreature.

3198 tbl 06

2. Industrial Temperature: for other speeds, packages and powers contact your
sales office.

V

80lbt8913

DC Electrical Characteristics Over the Operating

(2)

Temperature and Supply Voltage Range

Symbol Parameter Test Conditions

|ILI| Input Leak ag e Current

|I

Output Leak age Current

LO

|

V

Output Low Voltag e IOL = 4mA

OL

V

Output High Vol tage IOH = -4mA 2.4

OH

NOTES:

1. At Vcc

< 2.0V, input leakages are undefined.

2. Refer to Chip Enable Truth Table.

(1)

VCC = 5.5V, VIN = 0V to V

CE

= V

, V

= 0V to V

IH

OUT

CC

CC

6

(VCC = 5.0V ± 10%)

7008S 7008L

___

___

___

10
10

0.4

___

2.4

UnitMin. Max. Min. Max.

___

___

___

5µA
5µA

0.4 V

___

V

3198 tbl 09