Integrated Device Technology Inc IDT7007L35PFB, IDT7007L55G, IDT7007L55GB, IDT7007L55J, IDT7007L55JB Datasheet

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Integrated Device Technology, Inc.
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
IDT7007S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta­neous access of the same memory location
• High-speed access — Military: 25/35/55ns (max.) — Commercial: 20/25/35/55ns (max.)
• Low-power operation — IDT7007S
Active: 750mW (typ.) Standby: 5mW (typ.)
— IDT7007L
Active: 750mW (typ.) Standby: 1mW (typ.)
• IDT7007 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading
FUNCTIONAL BLOCK DIAGRAM
OE
L
CE
L L
R/
W
more than one device
•M/S = H for M/S = L for
BUSY
output flag on Master,
BUSY
input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V electrostatic discharge
• TTL-compatible, single 5V (±10%) power supply
• Available in 68-pin PGA, 68-pin PLCC, and a 80-pin TQFP
• Industrial temperature range (–40°C to +85°C) is avail­able, tested to military electrical specifications
OE
R
CE
R
R/
W
R
I/O0L- I/O
BUSY
(1,2)
L
A
A
14L
0L
7L
Address Decoder
I/O
Control
MEMORY
ARRAY
15
I/O
Control
Address Decoder
15
I/O0R-I/O
(1,2)
R
BUSY
A
14R
A
0R
7R
ARBITRATION
CE
L
OE
L
R/
W
L
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
2.
BUSY
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
and
BUSY
is output; (SLAVE):
INT
outputs are non-tri-stated push-pull.
BUSY
is input.
INTERRUPT
SEMAPHORE
LOGIC
M/
S
CE
OE
R/
R R
W
R
SEM
R
(2)
INT
2940 drw 01
R
MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996
©1996 Integrated Device Technology, Inc. DSC-2940/4
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.08
1
IDT7007S/L HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION:
The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The IDT7007 is designed to be used as a stand-alone 256K-bit Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full­speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in
PIN CONFIGURATIONS
(1,2)
INDEX
1L
I/O
0L
I/O
N/C
L
OE
L
W
R/
L
SEM
memory. An automatic power down feature controlled by permits the on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 750mW of power.
The IDT7007 is packaged in a 68-pin pin PGA, a 68-pin PLCC, and a 80-pin TQFP (thin plastic quad flatpack). Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
L
CE
14L
A
13L
A
CC
V
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
A
CE
I/O I/O I/O I/O GND I/O I/O
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
98765432168676665
2L
10
3L
11
4L
12
5L
13 14
6L
15
7L
16 17 18 19 20 21 22 23 24 25 26
27 28 29 30 31 32 33 34 35 36 37 38 39
R
N/C
OE
R
W
R/
7R
I/O
TOP VIEW
R
R
14R
CE
A
SEM
IDT7007
J68-1
PLCC
13R
A
(3)
12R
A
GND
11R
A
40 41 42 43
9R
10R
A
A
64 63 62 61
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
7R
8R
6R
A
A
A
2940 drw 02
5R
A
A
5L 4L
A A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
GND M/
S
BUSY
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
L
R
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to power supply.
3. This text does not indicate orientation of the actual part marking.
6.08 2
IDT7007S/L HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D.)
0L
1L
I/O
N/C
10 11 12 13 14 15 16 17 18
19
20
I/O
80
78
79
1 2 3 4 5 6 7 8 9
23
21
7R
I/O
22
N/C
R
OE
24
R
W
R/
INDEX
N/C I/O I/O I/O I/O
GND I/O I/O
V
N/C
GND
I/O I/O I/O
V I/O I/O I/O I/O
N/C
2L 3L 4L 5L
6L 7L
CC
0R 1R 2R
CC
3R 4R 5R 6R
(1,2)
L
OE
77
R
SEM
L
W
R/
76
25
L
L
SEM
CE
N/C
74
75
73
TOP VIEW
28
26
27
R
14R
N/C
CE
A
13L
14L
CC
A
A
V
71
70
72
IDT7007
PN80-1
TQFP
30
31
29
13R
12R
GND
A
A
12L
A
69
(3)
32
11R
A
11L
A
68
33
10R
A
10L
A
67
34
9R
A
9L
A
66
35
8R
A
8L
A
36
7R
A
65
7L
A
37
6R
A
64
6L
A
63
38
5R
A
N/C
62
60 59 58
57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
39
N/C
N/C
40
N/C
61
2940 drw 03
N/C A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
L
INT
BUSY
GND M/
S
BUSY
INT
R
A
0R
A
1R
A
2R
A
3R 4R
A N/C N/C
L
R
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to power supply.
3. This text does not indicate orientation of the actual part marking.
6.08 3
IDT7007S/L HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D.)
(1,2)
11
10
09
08
07
06
05
04
03
02
01
51 50 48 46 44 42 40 38 36
M/
A4L A2L A0L A3R
A
5L
525449 39 37
53
A6L
47 45 43 41 34
A3L A1L
INT
L
BUSY
GND
L
BUSY
S
R
55
A9L
A8L
56
57
A11L
A10L
58
59
VCC
A12L
IDT7007
G68-1
60
61
A14L
63
SEM
65
67
I/O0L
68
I/O1L
A13L
62
L
CE
L
64
OE
L
R/
W
L
66
N/C
13579
I/O4L I/O7L
I/O2L
GND GND
2 4 6 8 10 12 14 16
I/O3L
I/O5L
I/O6L
68-PIN PGA
TOP VIEW
I/O
VCC
0R
(3)
11 13 15
I/O1R I/O4R
I/O2R I/O3R I/O5R I/O6R
A
INT
1R
R
35
A4R
A2R
A0RA7L
32
A7R
30
A9R
28 A11R
26 GND
24
A14R
22
SEM
20
OE
A5R
33
A6R
31
A8R
29
A10R
27
A12R
25
A13R
23
R
CE
21
R
R/
18 19
VCC N/C
I/O7R
17
R
W
R
ABCDEFGH J
INDEX
NOTES:
CC pins must be connected to power supply.
1. All V
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part marking.
PIN NAMES
Left Port Right Port Names
CE
L
R/
W
L R/WR Read/Write Enable
OE
L
A
0L – A14L A0R – A14R Address
I/O
0L – I/O7L I/O0R – I/O7R Data Input/Output
SEM
L
INT
L
BUSY
L
CE
R Chip Enable
OE
R Output Enable
SEM
R Semaphore Enable
INT
R Interrupt Flag
BUSY
R Busy Flag
M/
S
V
CC Power
Master or Slave Select
GND Ground
2940 tbl 01
K
L
2940 drw 04
6.08 4
IDT7007S/L HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL
Inputs
CECE
CE
CECE
R/
WW
W
WW
H X X H High-Z Deselected: Power-Down
L L X H DATA L H L H DATA
X X H X High-Z Outputs Disabled
NOTE: 2940 tbl 02
1. A0L — A14L A0R — A14R.
(1)
OEOE
OE
OEOE
SEMSEM
SEM
SEMSEM
Outputs
0-7 Mode
I/O
IN Write to Memory
OUT Read Memory
TRUTH TABLE: SEMAPHORE READ/WRITE CONTROL
(1)
Inputs Outputs
CECE
CE
CECE
H H L L DATA H X L DATA
R/
WW
W
WW
OEOE
OE
OEOE
SEMSEM
SEM
SEMSEM
0-7 Mode
I/O
OUT Read Semaphore Flag Data Out (I/O0-I/O7)
IN Write I/O0 into Semaphore Flag
L X X L Not Allowed
NOTE: 2940 tbl 03
1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Commercial Military Unit
(2)
V
TERM
T
A Operating 0 to +70 –55 to +125 °C
T
BIAS Temperature –55 to +125 –65 to +135 °C
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V with Respect to GND
Temperature
(1)
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Grade Temperature GND V
Military –55°C to +125°C 0V 5.0V ± 10% Commercial 0°C to +70°C 0V 5.0V ± 10%
CC
2940 tbl 05
Under Bias
STG Storage –55 to +125 –65 to +150 °C
T
Temperature
I
OUT DC Output 50 50 mA
Current
NOTES: 2940 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect reliability.
2. V
TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to + 0.5V.
< 20mA for the period of VTERM > Vcc
RECOMMENDED DC OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
CC Supply Voltage 4.5 5.0 5.5 V
V GND Supply Voltage 0 0 0 V
IH Input High Voltage 2.2 6.0
V V
IL Input Low Voltage –0.5
NOTES: 2940 tbl 06
1. VIL > -1.5V for pulse width less than 10ns.
TERM must not exceed Vcc + 0.5V.
2. V
CAPACITANCE
(1)
(1)
0.8 V
(2)
V
(TA = +25°C, f = 1.0MHz)TQFP ONLY
Symbol Parameter Conditions
IN Input Capacitance VIN = 3dV 9 pF
C
OUT Output VOUT = 3dV 10 pF
C
Capacitance
NOTES: 2940 tbl 07
1. This parameter is determined by device characterization but is not production tested.
2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
(1)
Max. Unit
6.08 5
IDT7007S/L HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
LI| Input Leakage Current
|I
LO| Output Leakage Current
|I
OL Output Low Voltage IOL = 4mA 0.4 0.4 V
V
OH Output High Voltage IOH = – 4mA 2.4 2.4 V
V
NOTE: 2940 tbl 08
1. At Vcc < 2.0V, input leakages are undefined.
(1)
VCC = 5.5V, VIN = 0V to VCC —10—5µA
CE
= VIH, VOUT = 0V to VCC —10—5µA
(VCC = 5.0V ± 10%)
IDT7007S IDT7007L
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
Test Com'l. Only
Symbol Parameter Condition Version Typ.
CC Dynamic Operating
I
Current (Both Ports Active) f = f
SB1 Standby Current
I
(Both Ports — TTL Level Inputs) f = f
SB2 Standby Current
I
(One Port — TTL Active Port Outputs Open, L 105 200 Level Inputs) f = f
I
SB3 Full Standby Current Both Ports CEL and MIL. S 1.0 30 mA
(Both Ports — All CMOS Level Inputs) V
SB4 Full Standby Current
I
(One Port — All CMOS Level Inputs)
NOTES: 2940 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. V
CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = f
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions”
of input levels of GND to 3V.
CE
= VIL, Outputs Open MIL. S 170 345 mA
SEM
= V
IH L 170 305
(3)
MAX
CE
R = CEL = VIH MIL. S 25 100 mA
SEM
R =
SEM
L = VIH L— —25 80
(3)
MAX
CE
"A" = VIL and CE"B" = VIH
(3)
MAX
SEM
R =
SEM
L = VIH L 115 180 105 170
CE
R > VCC - 0.2V L 0.2 10
IN > VCC - 0.2V or COM’L. S 1.0 15 1.0 15
V
IN < 0.2V, f = 0
SEM
R =
CE
"A" < 0.2V and MIL. S 100 200 mA
CE
"B" > VCC - 0.2V
R =
SEM
IN VCC - 0.2V or VIN 0.2V COM’L. S 110 185 100 275
V
(4)
SEM
L > VCC - 0.2V
SEM
L > VCC - 0.2V
(5)
COM’L. S 180 315 170 305
COM’L. S 30 85 25 85
(5)
MIL. S 105 230 mA
COM’L. S 115 210 105 200
Active Port Outputs Open L 110 160 100 230
(3)
MAX
f = f
(1)
(VCC = 5.0V ± 10%)
7007X20 7007X25
(2)
Max. Typ.
L 180 275 170 265
L30 6025 60
L 0.2 5 0.2 5
L 100 175
(2)
Max. Unit
6.08 6
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