Integrated Device Technology Inc. IDT29FCT52A, IDT29FCT52B, IDT29FCT52C, IDT29FCT53A, IDT29FCT53B User Manual

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

Integrated Device Technology, Inc.

FAST CMOS
OCTAL REGISTERED
TRANSCEIVERS

IDT29FCT52A/B/C
IDT29FCT53A/B/C

FEATURES:

• Equivalent to AMD’s Am2952/53 and National’s
29F52/53 in pinout/function

• IDT29FCT52A/53A equivalent to FAST speed

• IDT29FCT52B/53B 25% faster than FAST

• IDT29FCT52C/53C 37% faster than FAST

•IOL = 64mA (commercial) and 48mA (military)

•IIH and IIL only 5µA max.

• CMOS power levels (2.5mW typ. static)

• TTL input and output level compatible

• CMOS output level compatible

• Available in 24-pin DIP, SOIC, 28-pin LCC with JEDEC
standard pinout

• Product available in Radiation Tolerant and Radiation
Enhanced versions

• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

CPA
CEA

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A

7

(1)

D
D

D
D

D
D
D
D

DESCRIPTION:

The IDT29FCT52A/B/C and IDT29FCT53A/B/C are 8-bit
registered transceivers manufactured using an advanced
dual metal CMOS technology. Two 8-bit back-to-back regis­ters store data flowing in both directions between two bidirec­tional buses. Separate clock, clock enable and 3-state output
enable signals are provided for each register. Both A outputs
and B outputs are guaranteed to sink 64mA.

The IDT29FCT52A/B/C is a non-inverting option of the
IDT29FCT53A/B/C.

OEB

CE CP

0
1

2
3

4
5
6
7

A

Reg.

Q

0

Q

1

Q

2

Q

3

Q

4

Q

5

Q

6

Q

7

B

0
1

B
B

2

B

3

B

4

B

5

B

6

B

7

D

0

D

1

D

2

D

3

B

D

4

D

5

D

6

D

7

CPB

OEA

Q
Q
Q
Q
Q
Q
Q
Q

0
1
2
3
4
5
6
7

CE CP

Reg.

CEB

NOTE: 2533 drw 01

1. IDT29FCT52 function is shown.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1992

1992 Integrated Device Technology, Inc. 7.1 DSC-4605/3

1

IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

1

7

B

2

B

6

3

B

5

B

4

B

3

B

2

B

1
0

B
OEB
CPA OEA
CEA CPB

GND

4
5
6
7
8
9
10
11
12

P24-1,
D24-1,

E24-1

SO24-2

24

Vcc

23

A

22
21
20
19

&

18
17
16
15
14
13

7
6

A
A

5

A

4

A

3

A

2

A

1

A

0

CEB

DIP/CERPACK/SOIC

TOP VIEW

INDEX

B

4

B

3

B

2

NC

B

1

B

0

OEB

7

B5B6B

432128 27 26

5
6
7
8
9
10
11

L28-1

12 13 14 15 16 17 18

CPA

CEA

GND

LCC

TOP VIEW

NC

NC

Vcc

CEB

7A6

A

CPB

25
24
23
22
21
20
19

OEA

A
A
A

NC
A
A
A

5
4
3

2
1
0

2533 drw 02

PIN DESCRIPTION

Name I/O Description

0-7 I/O Eight bidirectional lines carrying the A Register inputs or B Register outputs.

A

0-7 I/O Eight bidirectional lines carrying the B Register inputs or A Register outputs.

B
CPA I Clock for the A Register. When

of the CPA signal.

CEA

I Clock Enable for the A Register. When

transition of the CPA signal. When
transitions.

OEB

I Output Enable for the A Register. When

OEB

is HIGH, the B

0-7 outputs are in the high-impedance state.

CPB I Clock for the B Register. When

of the CPB signal.

CEB

I Clock Enable for the B Register. When

transition of the CPB signal. When
transitions.

OEA

I Output Enable for the B Register. When

OEA

is HIGH, the A

0-7 outputs are in the high-impedance state.

CEA

is LOW, data is entered into the A Register on the LOW-to-HIGH transition

CEA

is LOW, data is entered into the A Register on the LOW-to-HIGH

CEA

is HIGH, the A Register holds its contents, regardless of CPA signal

OEB

is LOW, the A Register outputs are enabled onto the B

CEB

is LOW, data is entered into the B Register on the LOW-to-HIGH transition

CEB

is LOW, data is entered into the B Register on the LOW-to-HIGH

CEB

is HIGH, the B Register holds its contents, regardless of CPB signal

OEA

is LOW, the B Register outputs are enabled onto the A

0-7 lines. When

0-7 lines. When

2533 tbl 01

REGISTER FUNCTION TABLE

(1)

(Applies to A or B Register)

Inputs Internal

DCP

X X H NC Hold Data
L ↑ L L Load Data
H ↑ LH

CE

CE

Q Function

2533 tbl 02

OUTPUT CONTROL

(1)

Internal Y-Outputs

OE

OE

Q 52 53 Function

H X Z Z Disable Outputs

L L L H Enable Outputs
LHHL

NOTE: 2533 tbl 03

1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
NC = No Change
↑ = LOW-to-HIGH Transition

7.1 2

IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

V

TERM

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND

(3)

V

TERM

Terminal Voltage –0.5 to VCC –0.5 to VCC V
with Respect
to GND

T

A Operating 0 to +70 –55 to +125 °C

Temperature

T

BIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

T

STG Storage –55 to +125 –65 to +150 °C

Temperature

P

T Power Dissipation 0.5 0.5 W

OUT DC Output Current 120 120 mA

I

NOTES: 2533 tbl 04

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed +0.5V unless otherwise noted.

2. Inputs and V

3. Outputs and I/O terminals only.

CC terminals only.

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

C

IN Input VIN = 0V 6 10 pF

Capacitance

I/O I/O VOUT = 0V 8 12 pF

C

Capacitance

NOTE: 2533 tbl 05

1. This parameter is guaranteed by characterization data and not tested.

(1)

Conditions Typ. Max. Unit

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

IH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V

V
V

IL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V

I

IH Input HIGH Current VCC = Max. VI =VCC ——5µA

(Except I/O Pins) V

(1)

I = 2.7V — — 5

Min. Typ.

IIL Input LOW Current VI = 0.5V — — –5

(Except I/O Pins) VI = GND — — –5

I

IH Input HIGH Current VCC = Max. VI = VCC ——15µA

(I/O Pins Only) V

I = 2.7V — — 15

IIL Input LOW Current VI = 0.5V — — –15

(I/O Pins Only) VI = GND — — –15

V

IK Clamp Diode Voltage Vcc = Min., IN = –18mA — –0.7 –1.2 V

I

OS Short Circuit Current Vcc = Max.

V

OH Output HIGH Voltage Vcc = 3V, VIN = VLC or VHC, IOH = –32µAVHC VCC —V

Vcc = Min. I
V

IN = VIH or VIL IOH = –15mA MIL. 2.4 4.0 —

V

OL Output LOW Voltage Vcc = 3V, VIN = VLC or VHC, IOL = 300µA — GND VLC V

Vcc = Min. I
VIN = VIH or VIL IOL = 48mA MIL.

NOTES: 2533 tbl 06

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. This parameter is guaranteed but not tested.

5. These are maximum I
384mA for military. Derate I

CC = 5.0V, +25°C ambient and maximum loading.

OL values per output, for 8 outputs turned on simultaneously. Total maximum IOL (all outputs) is 512mA for commercial and

OL for number of outputs exceeding 8 turned on simultaneously.

(3)

, VO = GND –60 –120 — mA

OH = –300µAVHC VCC —

I

OH = –24mA COM’L. 2.4 4.0 —

OL = 300µA — GND VLC

I

OL = 64mA COM’L.

(5)

— 0.3 0.55

(5)

— 0.3 0.55

(2)

Max. Unit

(4)

(4)

(4)

(4)

(4)

7.1 3

IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

VLC = 0.2V; VHC = VCC – 0.2V

Symbol Parameter Test Conditions

CC Quiescent Power Supply VCC = Max. — 0.5 1.5 µA

I

Current V

∆ICC Quiescent Power Supply Vcc = Max. — 0.5 2.0 mA

Current TTL Inputs HIGH V

ICCD Dynamic Power Supply Vcc = Max. VIN ≥ VHC — 0.15 0.25 mA/

I

C Total Power Supply Vcc = Max. VIN ≥ VHC — 2.0 4.0 mA

Current

Current

(4)

(6)

IN ≥ VHC; VIN ≤ VLC

IN = 3.4V

(3)

Outputs Open VIN ≤ VLC MHz

OEA

or

OEB

= GND
One Input Toggling
50% Duty Cycle

Outputs Open VIN ≤ VLC
fCP = 10MHz (FCT)
50% Duty Cycle

OEA

or

OEB

= GND
One Bit Toggling V
at fi = 5MHz V
50% Duty Cycle

CC = Max. VIN ≥ VHC — 4.3 7.8

V
Outputs Open VIN ≤ VLC
fCP = 10MHz (FCT)
50% Duty Cycle

OEA

or

OEB

= GND
Eight Bits Toggling V
at fi = 2.5MHz VIN = GND
50% Duty Cycle

(1)

IN = 3.4V — 2.5 6.0
IN = GND

IN = 3.4V — 6.5 16.8

Min. Typ.

(2)

Max. Unit

(5)

(5)

NOTES: 2533 tbl 07

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input (V

4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

5. Values for these conditions are examples of the I

C = IQUIESCENT + IINPUTS + IDYNAMIC

6. I
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)

CC = Quiescent Current

I
∆I

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

H = Duty Cycle for TTL Inputs High

D

T = Number of TTL Inputs at DH

N
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
f

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
i = Input Frequency

f

i = Number of Inputs at fi

N
All currents are in milliamps and all frequencies are in megahertz.

CC = 5.0V, +25°C ambient.

IN = 3.4V); all other inputs at VCC or GND.

CC formula. These limits are guaranteed but not tested.

7.1 4

IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

IDT29FCT52A/53A IDT29FCT52B/53B IDT29FCT52C/53C
Com’l. Mil. Com’l. Mil. Com’l. Mil.

(1)

(2)

Min.

Symbol Parameter Condition

Max. Min.

tPLH Propagation Delay CL = 50pF 2.0 10.0 2.0 11.0 2.0 7.5 2.0 8.0 2.0 6.3 2.0 7.3 ns
t

PHL CPA, CPB to An, Bn RL = 500Ω
PZH Output Enable Time 1.5 10.5 1.5 13.0 1.5 8.0 1.5 8.5 1.5 7.0 1.5 8.0 ns

t
t

PZL

OEA

n or Bn

A

or

OEB

to

tPHZ Output Disable Time 1.5 10.0 1.5 10.0 1.5 7.5 1.5 8.0 1.5 6.5 1.5 7.5 ns
t

PLZ

OEA

n or Bn

A

or

OEB

to

tSU Set-up Time HIGH 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns

or LOW A

n, Bn to

CPA, CPB

t

H Hold Time HIGH 2.0 — 2.0 — 1.5 — 1.5 — 1.5 — 1.5 — ns

or LOW A

n, Bn to

CPA, CPB

SU Set-up Time HIGH 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

t

or

LOW

CEA, CEB

to

CPA, CPB

H Hold Time HIGH 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns

t

or LOW

CEA, CEB

to

CPA, CPB

t

W Pulse Width, HIGH

(3)

3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

or LOW CPA or CPB

NOTES: 2533 tbl 08

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. This parameter is guaranteed but not tested.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Unit

7.1 5

IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

VCC

500Ω

Pulse

Generator

VIN

D.U.T.

RT

VOUT

50pF

CL

500Ω

7.0V

SWITCH POSITION

Test Switch

Open Drain

Disable Low Closed

Enable Low

All Other Tests Open

DEFINITIONS: 2533 tbl 09

CL = Load capacitance: includes jig and probe capacitance.

T = Termination resistance: should be equal to ZOUT of the Pulse

R

Generator.

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLOCK ENABLE

CLEAR

ETC.

t

tSU

SU

t

REM

t

t

H

H

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

LOW-HIGH-LOW

HIGH-LOW-HIGH

PULSE

PULSE

1.5V

t

W

1.5V

SAME PHASE

INPUT TRANSITION

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

t

t

PLH

PLH

t

t

PHL

PHL

3V

1.5V
0V

V

OH

1.5V
V

OL

3V

1.5V
0V

ENABLE AND DISABLE TIMESPROPAGATION DELAY

ENABLE DISABLE

3V

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

t

PZL

SWITCH
CLOSED

t

PZH

SWITCH
OPEN

3.5V

1.5V

1.5V
0V

t

PHZ

t

PLZ

NOTES 2533 drw 04

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; Z
t

R ≤ 2.5ns.

1.5V
0V

3.5V

0.3V

V

OL

V

OH

0.3V
0V

O ≤ 50Ω; tF ≤ 2.5ns;

7.1 6

IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT29FCT

XXX

Device

Type

X

Package

X

Process/

Temperature

Range

Blank
B

P
D
E
L
SO

52A
53A
52B
53B
52C
53C

Commercial (0
Military (–55

°C to +70°C)

°C to +125°C)

Compliant to MIL-STD-883, Class B

Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC

Non-Inverting Octal Registered Transceiver
Inverting Octal Registered Transceiver
Fast Non-Inverting Octal Registered Transceiver
Fast Inverting Octal Registered Transceiver
Super Fast Non-Inverting Octal Registered Transceiver
Super Fast Inverting Octal Registered Transceiver

2533 drw 03

7.1 7