IDT ICS8OSK270GILF Schematic [ru]

PRELIMINARY DATASHEET

27 MHZ FIXED AND SPREAD CLOCK GENERATOR ICS8OSK270

Description

The ICS8OSK270 is a low cost integrated clock
synthesizer solution replacing crystals and crystal
oscillators.

The ICS8OSK270 generates a very accurate 27.00
MHz fixed clock output, and a 27.00 MHz spread
spectrum clock output from a 14.31818 MHz reference
clock or crystal input.

Block Diagram

14.318 MHz

crystal or clock

input

X1/ICLK

X2

S0

Crystal

Oscillator/

Clock Buffer

VDD

Features

• 14.31818 MHz crystal or clock input

• The 27 MHz_Fixed clock output is non-spread with

<10 ppm synthesis error

• 27 MHz_SS clock output with selectable spread

spectrum for EMI reduction

• Output duty cycle 45/55% (worst case)

• Advanced, low-power CMOS process

• Industrial temperature range (-40 to 85°C)

• Packaged in 8-pin MSOP (3.00 mm body)

• RoHS 5 (green) or RoHS 6 (green and lead free)

compliant packaging

2

27M_Fixed

PLL

27M_SS

IDT™ / ICS™

External capacitors are

required with a crystal input

GND

27 MHZ FIXED AND SPREAD CLOCK GENERATOR 1

ICS8OSK270 REV C 050406

ICS8OSK270
27 MHZ FIXED AND SPREAD CLOCK GENERATOR SSCG

Pin Assignment

8

S0

1

VDD

VDD

X1/I CLK

X2

2

3

4

7

6

5

GND

27M_SS

27M_FIXED

Spread Spectrum Percentage Selection Table

S0 27M_SS Down

Spread

0 -0.5%

1 -1.5%

Pin Descriptions

Pin

Number

1 S0 Input Spread Spectrum percentage select 0. See table above.

2 VDD Power Connect to +3.3 V.

3 X1/ICLK Input Crystal connection. Connect to14.31818 MHz crystal or clock

4 X2 Output Crystal connection. Connect to14.31818 MHz crystal.

Pin

Name

Pin

Typ e

input.

Pin Description

5 27M_FIXED Output 27 MHz fixed clock output at 3.3 V.

6 27M_SS Output 27 MHz spread spectrum clock output at 3.3 V.

7 GND Power Connect to ground.

8 VDD Power Connect to +3.3 V.

IDT™ / ICS™

27 MHZ FIXED AND SPREAD CLOCK GENERATOR 2

ICS8OSK270 REV C 050406

ICS8OSK270
27 MHZ FIXED AND SPREAD CLOCK GENERATOR SSCG

External Components

Decoupling Capacitor

As with any high-performance mixed-signal IC, the
ICS8OSK270 must be isolated from system power
supply noise to perform optimally.

A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.

Series Termination Resistor

Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.

Crystal Load Capacitors

The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors must
be connected from each of the pins X1 and X2 to
ground.

PCB Layout Recommendations

For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.

1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.

2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.

3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.

4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS8OSK270. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.

The value (in pF) of these crystal caps should equal (C

-6 pF)*2. In this equation, C
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be 20 pF
[(16-6) x 2 = 20].

IDT™ / ICS™

27 MHZ FIXED AND SPREAD CLOCK GENERATOR 3

= crystal load capacitance

L

L

ICS8OSK270 REV C 050406