Page 1
Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
LOCK GENERATOR
C
GENERAL DESCRIPTION
The ICS8702 is a very low skew, ÷1, ÷2 Clock
,&6
HiPerClockS™
els. True or inverting, single-ended to LVCMOS translation
can be achieved with a resistor bias on the nCLK or CLK
inputs, respectively. The effective fanout can be increased
from 20 to 40 by utilizing the ability of the outputs to drive two
series terminated lines.
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The bank enable
inputs, BANK_EN0:1, supports enabling and disabling each
bank of outputs individually. The master reset input, nMR/OE,
resets the internal frequency dividers and also controls the
enabling and disabling of all outputs simultaneously.
The ICS8702 is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output, multiple frequency and part-to-part skew characteristics make the ICS8702 ideal for those clock distribution applications demanding well defined performance and
repeatability.
Generator and a member of the HiPerClockS
family of High Performance Clock Solutions
from ICS. The ICS8702 is designed to translate any differential signal levels to LVCMOS lev-
FE ATURES
20 LVCMOS outputs, 7Ω typical output impedance
Output frequency up to 250 MHz
150ps bank skew, 200ps output, 250ps multiple frequency
skew, 650ps part-to-part skew
Translates any differential input signal (PECL, HSTL, LVDS)
to LVCMOS levels without external bias networks
Translates any single-ended input signal to LVCMOS levels
with a resistor bias on nCLK input
Translates any single-ended input signal to inverted LVCMOS
levels with a resistor bias on CLK input
LVCMOS / LVTTL control inputs
Bank enable logic allows unused banks to be disabled
in reduced fanout applications
3.3V or mixed 3.3V input, 2.5V output operating
supply modes
48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
0°C to 70°C ambient operating temperature
Other divide values available on request
BLOCK DIAGRAM PIN ASSIGNMENT
GND
CLK
nCLK
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
÷1
÷1
÷2
÷2
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Bank Enable
Bank Enable
Logic
Logic
QAO - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
QC3
VDDO
QC4
QD0
VDDO
QD1
GND
QD2
GND
QD3
VDDO
QD4
GND
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
DIV_SELD
QC1
QC2
VDDI
nMR/OE
DIV_SELC
48-Lead LQFP
QC0
QB4
VDDO
VDDO
ICS8702
VDDI
BANK_EN0
GND
BANK_EN1
Y Package
Top View
QB3
nCLK
GND
QB2
DIV_SELB
CLK
GND
36
35
34
33
32
31
30
29
28
27
26
25
DIV_SELA
QB1
VDDO
QB0
QA4
VDD0
QA3
GND
QA2
GND
QA1
VDDO
QA0
8702 www.icst.com REV. A - AUGUST 7, 2000
1
Page 2
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
,62,11,5,2
44,14,53,23
,03,82,9,7
84,64,93,73
02,61IDDVrewoP.V3.3ottcennoC.ylppusrewoptupnI
81DNGrewoP.dnuorgottcennoC.ylppusrewoptupnI
,92,72,52
33,13
,83,63,43
24,04
,74,54,34
3,1
,8,6,4
21,01
22KLCtupnInwodlluP .slevellaitnereffidynastpeccA.tupnikcolclaitnereffidgnitrevni-noN
12KLCntupnIpulluP.slevellaitnereffidynastpeccA.tupnikcolclaitnereffidgnitrevnI
31DLES_VIDtupnIpulluP .slevelecafretniSOMCVL.stuptuoDknabrofnoisividycneuqerfslortnoC
41CLES_VIDtupnIpulluP .slevelecafretniSOMCVL.stuptuoCknabrofnoisividycneuqerfslortnoC
32BLES_VIDtupnIpulluP .slevelecafretniSOMCVL.stuptuoBknabrofnoisividycneuqerfslortnoC
42ALES_VIDtupnIpulluP .slevelecafretniSOMCVL.stuptuoAknabrofnoisividycneuqerfslortnoC
91,71
51EO/RMntupnIpulluP
ODDVrewoP.V5.2roV3.3ottcennoC.ylppusrewoptuptuO
DNGrewoP.dnuorgottcennoC.ylppusrewoptuptuO
ICS8702
LOW SKEW ¸1, ¸2
C
LOCK GENERATOR
,2AQ,1AQ,0AQ
4AQ,3AQ
,2BQ,1BQ,0BQ
4BQ,3BQ
,2CQ,1CQ,0CQ
4CQ,3CQ
,2DQ,1DQ,0DQ
4DQ,3DQ
,1NE_KNAB
0NE_KNAB
tuptuO7.stuptuoAknaB Ω .ecnadepmituptuolacipyt
tuptuO7.stuptuoBknaB Ω .ecnadepmituptuolacipyt
tuptuO7.stuptuoCknaB Ω .ecnadepmituptuolacipyt
tuptuO7.stuptuoDknaB Ω .ecnadepmituptuolacipyt
tupnIpulluP .slevelecafretniSOMCVL.sknabybstuptuoselbasiddnaselbanE
llaselbasiddnaselbanE.sredividkcolcsteseR.teserretsamsuonorhcnysA
.slevelecafretniSOMCVL.stuptuo
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
NICecnaticapaCtupnI Fp
PULLUPRrotsiseRpulluPtupnI 15KΩ
NWODLLUPRrotsiseRnwodlluPtupnI 15KΩ
DPCecnaticapaCnoitapissiDrewoP
)tuptuorep(
TUORecnadepmItuptuO 7
V564.3=ODDV,IDDV Fp
V526.2=ODDV,V564.3=IDDV Fp
TABLE 3A. CONTROL INPUTS FUNCTION TABLE
stupnI stuptuO
EO/RMn1NE_KNAB0NE_KNABxLES_VID4AQ-0AQ4BQ-0BQ4CQ-0CQ4DQ-0DQycneuqerfxQ
0X XX ZiHZiHZiHZiHorez
10 00 evitcAZiHZiHZiH2/NIf
11 00 evitcAevitcAZiHZiH2/NIf
10 10 evitcAevitcAevitcAZiH2/NIf
11 10 evitcAevitcAevitcAevitcA2/NIf
10 0 1 evitcAZiHZiHZiHNIf
11 01 evitcAevitcAZiHZiHNIf
10 11 evitcAevitcAevitcAZiHNIf
11 11 evitcAevitcAevitcAevitcANIf
Ω
8702 www.icst.com REV. A - AUGUST 7, 2000
2
Page 3
Integrated
Circuit
Systems, Inc.
LOW SKEW ¸1, ¸2
LOCK GENERATOR
C
ICS8702
TABLE 3B . CLOCK INPUTS FUNCTION TABLE
stupnIstuptuO
EO/RMnKLCKLCn4xQurht0xQ
10 1 WOLdednEelgniSotlaitnereffiDgnitrevnInoN
110 HGIHdednEelgniSotlaitnereffiDgnitrevnInoN
10 1ETON;desaiBWOLdednEelgniSotdednEelgniSgnitrevnInoN
11 1ETON;desaiBHGIHdednEelgniSotdednEelgniSgnitrevnInoN
11ETON;desaiB0HGIHdednEelgniSotdednEelgniSgnitrevnI
11ETON;desaiB1WOLdednEelgniSotdednEelgniSgnitrevnI
1.0adnadnuorgµ .Vm003±2/DDVyletamixorppasitniophctiwsgnitluserehT.dnuorgottupniehtmorfroticapacF
edoMtuptuOottupnIytiraloP
roftniophctiwsehtstestupnidesaibehttaegatlovehT.desaibebstupnilaitnereffidehtfoenotahtseriuqeresutupnidedneelgniS:1ETON
oteulavlauqeforotsisera,IDDVotrotsiserasikrowtensaibtupnidednemmocerehtsleveltupniSOMCVLroF.tupnidedneelgniseht
ABSOLUTE MAXIMUM RATINGS
Supply Voltage 4.6V
Inputs -0.5V to VDD + 0.5V
Outputs -0.5V to VDDO + 0.5V
Ambient Operating Temperature 0°C to 70°C
Storage Temperature -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Electrical
Characteristics or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
8702 www.icst.com REV. A - AUGUST 7, 2000
3
Page 4
Integrated
Circuit
Systems, Inc.
LOW SKEW ¸1, ¸2
C
LOCK GENERATOR
ICS8702
TABLE 4A. DC ELECTRICAL CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
IDDVegatloVylppuSrewoPtupnI 531.33.3564.3V
ODDVegatloVylppuSrewoPtuptuO 531.33.3564.3V
HIVegatloVhgiHtupnIKLCn,KLCtpecxellAV564.3=IDDV28.3V
LIVegatloVwoLtupnI;KLCn,KLCtpecxellAV531.3=IDDV3.0-8.0V
PPV
RMCV
HIItnerruChgiHtupnI
LIItnerruCwoLtupnI
DDItnerruCylppuSrewoPtnecseiuQ
HOVegatloVhgiHtuptuO
LOVegatloVwoLtuptuO
egatloV
.1erugiFeeS.egatlov
tupnIkaeP-ot-kaeP
tupnIedoMnommoC
1ETON;egatloV
KLCn,KLC51.03.1V
KLCn,KLC
KLCtpecxellAV564.3=NIV=IDDV5Aµ
KLCV564.3=NIV=IDDV051Aµ
KLCtpecxellAV0=NIV,564.3=IDDV051-Aµ
KLC0=NIV,564.3=IDDV5-Aµ
sleveLLCEPVL8.14.2V
sleveL
LTSS,SDVL,LTSH,MCD
V564.3=HIV=IDDV
V0=LIV
V531.3=ODDV=IDDV
Am63-=HOI
V531.3=ODDV=IDDV
Am63=LOI
13.03.1V
07Am
6.2V
5.0V
=ICCVroferaA4elbaTnidetonseulavLCEPVLehT.HIVmuminimehtsadenifedsiLCEPVLrofegatlovtupniedomnommoC:1ETON
revossorcehtsadenifedsiLTSSdnaSDVL,LTSH,MCDrofegatlovtupniedomnommoC.ICCVhtiw1:1yravlliwLCEPVLrofRMCV.V3.3
TABLE 5A. AC ELECTRICAL CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
XAMfycneuqerFtupnImumixaM 052zHM
HLpthgiH-ot-woL,yaleDnoitagaporPZHM0 < f ≤ zHM0022.25.3sn
LHptwoL-ot-hgiH,yaleDnoitagaporPZHM0 < f ≤ zHM0022.25.3sn
)b(kst2ETON;wekSknaB 2/ODDVtaegdegnisirnoderusaeM051sp
)o(kst3ETON;wekStuptuO 2/ODDVtaegdegnisirnoderusaeM002sp
(kst ω)4ETON;wekSycneuqerFelpitluM 2/ODDVtaegdegnisirnoderusaeM052sp
)pp(kst5ETON;wekStraPottraP 2/ODDVtaegdegnisirnoderusaeM056sp
Rt6ETON;emiTesiRtuptuO%07ot%03082058sp
Ft6ETON;emiTllaFtuptuO%07ot%03082058sp
WPthtdiWesluPtuptuO
NEtemiTelbanEtuptuO6ETON;zHM01=f6sn
SIDtemiTelbasiDtuptuO6ETON;zHM01=f6sn
ZHM0 < f < zHM002
zHM002=f25.23sn
.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:6ETON
2/ELCYCt
5.0-
2/ELCYCt
.snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofoknabanihtiwwekssadenifeD:2ETON
.snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofosknabssorcawekssadenifeD:3ETON
2/ELCYCt
5.0+
05htiwdetanimretstuptuollA.esiwrehtodetonsselnuVm003=PPVdnazHM002=NIftaderusaemsretemarapllA:1ETON Ω .2/ODDVot
sn
.snoitidnocdaollauqednasegatlovylppusemasehthtiwycneuqerftnereffidtagnitarepostuptuofosknabssorcawekssadenifeD:4ETON
.snoitidnocdaollauqehtiwdnasegatlovylppusemasehttagnitareposecivedtnereffidnostuptuotnereffidtaweksehtsadenifeD:5ETON
8702 www.icst.com REV. A - AUGUST 7, 2000
4
Page 5
Integrated
Circuit
Systems, Inc.
LOW SKEW ¸1, ¸2
LOCK GENERATOR
C
ICS8702
TABLE 4B. DC ELECTRICAL CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
IDDVegatloVylppuSrewoPtupnI 531.33.3564.3V
ODDVegatloVylppuSrewoPtuptuO 573.25.2526.2V
HIVegatloVhgiHtupnIKLCn,KLCtpecxellAV564.3=IDDV28.3V
LIVegatloVwoLtupnIKLCn,KLCtpecxellAV531.3=IDDV3.0-8.0V
PPV
RMCV
HIItnerruChgiHtupnI
LIItnerruCwoLtupnI
DDItnerruCylppuSrewoPtnecseiuQ
HOVegatloVhgiHtuptuO
LOVegatloVwoLtuptuO
kaeP-ot-kaeP
egatloVtupnI
edoMnommoC
;egatloVtupnI
1ETON
.1erugiFeeS.egatlov
KLCn,KLC51.03.1
KLCn,KLC
KLCtpecxellAV564.3=NIV=IDDV5Aµ
KLCV564.3=NIV=IDDV051Aµ
KLCtpecxellAV0=NIV,V564.3=IDDV051-Aµ
KLCV0=NIV,V564.3=IDDV5-Aµ
sleveLLCEPVL8.14.2
sleveLLTSS,SDVL,LTSH,MCD13.03.1
V564.3=HIV=IDDV
V0=LIV
Am72-=HOI
V573.2=ODDV,V531.3=IDDV
V573.2=ODDV,V531.3=IDDV
Am72=LOI
9.1V
07Am
5.0V
=ICCVroferaB4elbaTnidetonseulavLCEPVLehT.HIVmuminimehtsadenifedsiLCEPVLrofegatlovtupniedomnommoC:1ETON
revossorcehtsadenifedsiLTSSdnaSDVL,LTSH,MCDrofegatlovtupniedomnommoC.ICCVhtiw1:1yravlliwLCEPVLrofRMCV.V3.3
TABLE 5B. AC ELECTRICAL CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
XAMfycneuqerFtupnImumixaM 052zHM
HLpthgiH-ot-woL,yaleDnoitagaporPZHM0 < f ≤ zHM0023.26.3sn
LHptwoL-ot-hgiH,yaleDnoitagaporPZHM0 < f ≤ zHM0023.26.3sn
)b(kst2ETON;wekSknaB 2/ODDVtaegdegnisirnoderusaeM051sp
)o(kst3ETON;wekStuptuO 2/ODDVtaegdegnisirnoderusaeM002sp
(kst ω)4ETON;wekSycneuqerFelpitluM 2/ODDVtaegdegnisirnoderusaeM052sp
)pp(kst5ETON;wekStraPottraP 2/ODDVtaegdegnisirnoderusaeM007sp
Rt6ETON;emiTesiRtuptuO%07ot%03082058sp
Ft6ETON;emiTllaFtuptuO%07ot%03082058sp
WPthtdiWesluPtuptuO
NEt6ETON;emiTelbanEtuptuOzHM01=f6sn
SIDtemiTelbasiDtuptuO6ETON;zHM01=f6sn
ZHM0 < f < zHM002
zHM002=f25.23sn
.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:6ETON
2/ELCYCt
5.0-
2/ELCYCt
.snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofoknabanihtiwwekssadenifeD:2ETON
.snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofosknabssorcawekssadenifeD:3ETON
2/ELCYCt
5.0+
05htiwdetanimretstuptuollA.esiwrehtodetonsselnuVm003=PPVdnazHM002=NIftaderusaemsretemarapllA:1ETON Ω .2/ODDVot
sn
.snoitidnocdaollauqednasegatlovylppusemasehthtiwycneuqerftnereffidtagnitarepostuptuofosknabssorcawekssadenifeD:4ETON
.snoitidnocdaollauqehtiwdnasegatlovylppusemasehttagnitareposecivedtnereffidnostuptuotnereffidtaweksehtsadenifeD:5ETON
8702 www.icst.com REV. A - AUGUST 7, 2000
5
Page 6
Integrated
Circuit
Systems, Inc.
FIGURE 1A, 1B - TIMING DIAGRAMS
CLK
nCLK
Qx, ÷1
Qx, ÷2
FIGURE 1A - ACTIVE, ÷1, ÷2
ICS8702
LOW SKEW ¸1, ¸2
C
LOCK GENERATOR
nMR/OE
CLK
n CLK
Qx, ÷1
Qx, ÷2
High Impedance Active
FIGURE 1B - RESET TO A CTIVE, ÷1, ÷2
8702 www.icst.com REV. A - AUGUST 7, 2000
6
Page 7
Integrated
Circuit
Systems, Inc.
FIGURE 2A, 2B, 2C - INPUT CLOCK WAVEFORMS
VDDI
CLK
ICS8702
LOW SKEW ¸1, ¸2
LOCK GENERATOR
C
nCLK
GND
VDDI
CLK
nCLK
GND
VPP
CROSS POINTS
VCMR
FIGURE 2A - DCM, HSTL, LVDS, SSTL DIFFERENTIAL INPUT LEVELS
VPP
CROSS POINTS
VCMR
FIGURE 2B - LVPECL DIFFERENTIAL INPUT LEVEL
VDDI
CLK
or
nCLK
GND
FIGURE 2C- LVCMOS AND LVTTL SINGLE ENDED I NPUT LEVEL
8702 www.icst.com REV. A - AUGUST 7, 2000
7
Page 8
Integrated
Circuit
Systems, Inc.
FIGURE 3A, 3B - TIMING WAVEFORMS
CLK
Vpp
nCLK
ICS8702
LOW SKEW ¸1, ¸2
C
LOCK GENERATOR
nMR/OE,
BANK_ENx
BANK_ENx
Q
VDDO/2
3.3V
0V
VOH
VDDO/2
VDDO/2
tPHL
Q
tPLH
FIGURE 3 A - PROPAGATION DELAYS
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
tPHZ
VOH - 300mV
tPLZ
tPZH
tPZL
VOL
Q
VOL + 300mV
FIGURE 3B - DISABLE AND ENABLE TIMES
fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps
8702 www.icst.com REV. A - AUGUST 7, 2000
8
Page 9
Integrated
Circuit
Systems, Inc.
LOW SKEW ¸1, ¸2
LOCK GENERATOR
C
ICS8702
FIGURE 4A, 4B- SKEW DEFINITIONS & WAVEFORMS
Bank Skew - Skew between outputs within a bank. Outputs operating at the same temperature, supply voltages and with equal
load conditions.
CLK
Vpp
nCLK
Qx0
○○○○○○○○
VDDO/2 VDDO/2
tsk(b) tsk(b)
Qx4
VDDO/2 VDDO/2
FIGURE 4A - BANK SKEW
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
Output Skew - Skew between outputs of any bank. Outputs operating at the same temperature, supply voltages and with equal
load conditions.
CLK
Vpp
nCLK
QA0 - QA4
VDDO/2 VDDO/2
tsk(o) tsk(o)
QB0 - QB4
QC0 - QC4
QD0 - QD4
VDDO/2 VDDO/2
FIGURE 4B - OUTPUT SKEW
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
8702 www.icst.com REV. A - AUGUST 7, 2000
9
Page 10
Integrated
Circuit
Systems, Inc.
LOW SKEW ¸1, ¸2
C
LOCK GENERATOR
ICS8702
FIGURE 4C, 4D- SKEW DEFINITIONS & WAVEFORMS
Multiple Frequency Skew - Skew between banks of outputs operating at different frequencies. Outputs operating at the same
temperature, supply voltages and with equal load conditions.
CLK
Vpp
nCLK
QA0 - QA4,
QB0 - QB4,
QC0 - QC4,
or
QD0 - QD4
in ÷1
VDDO/2 VDDO/2
tsk(w) tsk(w)
VDDO/2 VDDO/2
QA0 - QA4,
QB0 - QB4,
QC0 - QC4,
or
QD0 - QD4
in ÷2
FIGURE 4C - MULTIPLE FREQUENCY S KEW
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
Part to Part Skew - Skew between outputs of any bank on different parts. Outputs operating at the same temperature, supply
voltages and with equal load conditions.
CLK
Vpp
nCLK
PART 1 QA0 - QA4
PART 2 QA0 - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
QB0 - QB4
QC0 - QC4
QD0 - QD4
VDDO/2 VDDO/2
tsk(p) tsk(p)
VDDO/2 VDDO/2
FIGURE 4B - OUTPUT SKEW
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
8702 www.icst.com REV. A - AUGUST 7, 2000
10
Page 11
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE AND D IMENSIONS - Y SUFFIX
NOTE 4
NOTE 4
D
D
NOTE 5, 7
NOTE 5, 7
D1
D1
NOTE 3
NOTE 3
-D-
-D-
NOTE 3
NOTE 3
-A-
-A-
e
e
N/4 TIPS
N/4 TIPS
0.20 C A-B D4X
0.20 C A-B D4X 0.20 C A-B D0.20 C A-B D4X
SEE DETAIL “A”
SEE DETAIL “A”
8 PLACES
8 PLACES
11 / 13°
11 / 13°
D/2
D/2
D1/2
D1/2
NOTE 3
NOTE 3
-B-
-B-
E/2
E/2
E1/2
E1/2
A
A
NOTE 2 / / 0.10 C
NOTE 2 / / 0.10 C
-H-
-H-
-C-
-C-
SEE DETAIL “B”
SEE DETAIL “B”
ccc
ccc
ICS8702
LOW SKEW ¸1, ¸2
LOCK GENERATOR
C
e / 2
e / 2
-A, B, OR -D-
-A, B, OR -D-
b
b
E
E1
E
E1
N
N
N
N
O
O
O
O
T
T
T
T
E
E
E
E
4
4
5,
5,
7
7
NOTES:
1. A LL DIMENSIONS AND TOLERA NCING CONFO RM T O ANSI
Y14.5-1982
2. DATUM PLANE -H-LOCATED AT MOLD PARTING LINE AND
COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY
AT BOTT OM OF PARTING LINE.
3. DA TUMS A-B AND -D- TO BE DETERMINED AT CE NT ERLINE
BETWEEN LEADS WHERE LEADS EXIT PLA STIC AT DATUM
PLANE -H- .
4. TO BE DETERMINED AT SEATING PLACE -C- .
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOL D
PROT RUSION.
6. “N” IS THE TOTAL NUMBER OF TERMINALS.
7. THESE DIMENSIONS TO BE DETEREMINED AT DATUM PL ANE
-H-.
8. PACKAGE TOP DIMENSI ONS ARE SMALLER THAN BOTTOM
DIM ENSIONS AND TOP OF PACKAGE WILL NOT OVER HANG
BOTTOM OF PACKAGE.
9. DIMENSION b DOES NOT INCL UDE DAMBAR PROTRUSION.
ALLOWABL E DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL
IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL
CONDITION.
10. CONTROLLING DIMENSION: MILLIMETER.
11. THIS OUT LINE CONFORMS TO JE DEC PUBLIBCATION 95
REGISTRAT ION M S-026, VARIATION BBC.
12. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
TO THE LOWEST POINT OF THE PACKAGE.
-A, B, OR -D-
-A, B, OR -D-
b
b
b
b
1
1
0.08
0.08
R. MIN.
R. MIN.
0.20 MIN.
0.20 MIN.
1.00 REF.
1.00 REF.
ddd M C A-B S D S
WITH LEAD FINISH
WITH LEAD FINISH
BASE METAL
BASE METAL
0° MIN.
0° MIN.
0° -7 °
0° -7 °
L
L
0.08/0.20 R.
0.08/0.20 R.
0.25
0.25
GAUGE PLANE
GAUGE PLANE
S
M
O
A
A
A
A
D
D
E
E
b1
b1
ccc
ccc
ddd
ddd
S
Y
Y
M
B
B
O
L
L
A
A
1
1
2
2
D
D
1
1
E
E
1
1
L
L
N
N
e
e
b
b
JEDEC VARIATIO N
JEDEC VARIATIO N
ALL DIM E NSIONS IN MILLIM ETERS
ALL DIM E NSIONS IN MILLIM ETERS
MIN. NOM. MAX.
MIN. NOM. MAX.
0.05 0.15
0.05 0.15
1.35 1.40 1.45
1.35 1.40 1.45
9.00 BSC.
9.00 BSC.
7.00 BSC.
7.00 BSC.
9.00 BSC.
9.00 BSC.
7.00 BSC.
7.00 BSC.
0.45 0.60 0.75
0.45 0.60 0.75
0.5 BSC.
0.5 BSC.
0.17 0.22 0.27
0.17 0.22 0.27
0.17 0.20 0.23
0.17 0.20 0.23
BBC
BBC
48
48
1.60
1.60
0.08
0.08
0.08
0.08
12
12
7, 8
7, 8
7, 8
7, 8
N
N
O
O
T
T
E
E
4
4
4
4
9
9
NOTE 9 ddd M C A-B S D S
NOTE 9
0.09 / 0.20 0.09 / 0.16
0.09 / 0.20 0.09 / 0.16
-0.05 S
-0.05 S
-0.05 S
DATUM
DATUM
A2
A2
PLANE
PLANE
-H-
-H-
A1
A1
8702 www.icst.com REV. A - AUGUST 7, 2000
11
Page 12
Integrated
Circuit
Systems, Inc.
ORDERING INFORMATION
YB2078SCIYB2078SCIPFQLdaeL84yartrep052C°07otC°0
TYB2078SCIYB2078SCIleeRdnaepaTnoPFQLdaeL840002C°07otC°0
ICS8702
LOW SKEW ¸1, ¸2
C
LOCK GENERATOR
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
8702 www.icst.com REV. A - AUGUST 7, 2000
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