ICT PEEL16CV8J-25, PEEL16CV8P-25, PEEL16CV8S-25, PEEL16CV8T-25 Datasheet

CMOS Programmable Electrically Erasable Logic Device

Features

•

Compatible with Popular 16V8 Devices

- 16V8 socket and function compatible

- Programs with standard 16V8 JEDEC file

- 20-pin DIP, SOIC, TSSOP, and PLCC

•

CMOS Electrically Erasable Technology

- Superior factory testing

- Reprogrammable in plastic package

- Reduces retrofit and development costs

•

Application Versatility

- Replaces random logic

- Super sets standard 20-pin PLDs (PALs)

General Description

PEEL™ 16CV8 -25

•

Multiple Speed, Power Options

- Speeds range 25ns

- Power as low as 37mA @ 25mHZ

•

Development / Programmer Support

- Third party software and programmers

- ICT PLACE Development Software

- Automatic programmer translation and JEDEC file translation
software available for the most popular PAL devices

Commercial

The PEEL

TM

16CV8 is a Programmable Electrically Erasable Logic

(PEEL) device providing an attractive alternative to ordinary PLDs. The

TM

16CV8 offers the performance, flexibility, ease of design and

PEEL
production practicality needed by logic designers today.

The PEEL

TM

16CV8 is available in 20-pin DIP , PLCC, SOIC and TSSOP
packages (see Figure 1) with 25ns speed and power consumption as
low as 37mA. EE-Reprogrammability provides the convenience of
instant reprogramming for development and reusable production inven­tory minimizing the impact of programming changes or errors. EE­Reprogrammability also improves factory testability, thus assuring the
highest quality possible.

Figure 1 - Pin Configuration

I/CLK1

GND

DIP

PLCC-J

GND

GND

1
2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

1
2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9
10

I/O 2I/O

I/CLK1

3

1

9I10

20

11I12

GND

I

4

I

5

I

6

I

7

I

8

20
19
18
17
16
15
14
13
12
11

VCC19I/O

I/O13I/O

V

I/CLK1

CC

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I

I/CLK1

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

20

V

CC

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

I/O

12

I/O

11

I

TSSOP

20

V

CC

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

I/O

12

I/O

11

I

SOIC

The PEELTM 16CV8 architecture allows it to replace over standard 20-

TM

pin PLDs (PAL, GAL, EPLD etc.). See Figure 2. ICT’s PEEL

16CV8

can be programmed with existing 16CV8 JEDEC file. Some program-

TM

mers also allow the PEEL

16CV8 to be programmed directly from

PLD 16L8, 16R4, 16R6 and 16R8 JEDEC files. Additional development

TM

and programming support for the PEEL

16CV8 is provided by popular
third-party programmers and development software. ICT also offers free
PLACE development software.

Figure 2 - Block Diagram

CLK

/CLK

I/OE

PEEL

"AND"

ARRAY

64 TERMS

X

32 INPUTS

MACRO

CELL

O

I/
I/O
I/O
I/O
I/O
I/O
I/O
I/O

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Functional Description

The PEELTM 16CV8 implements logic functions as sum-of- products
expressions in a programmable-AND/fixed-OR logic array. User-defined
functions are created by programming the connections of input signals
into the array. User-configurable output structures in the form of macro­cells further increase logic flexibility.

Architecture Overview

The PEEL
which allow a total of up to 16 inputs and 8 outputs for creating logic
functions. At the core of the device is a programmable electrically-eras­able AND array which drives a fixed OR array. With this structure the

PEEL
sions.

TM

16CV8 features ten dedicated input pins and eight I/O pins,

TM

16CV8 can implement up to 8 sum-of-products logic expres-

PEELTM 16CV8

•

64 product terms:

-56 product terms (arranged in 8 groups of 7) form sum-of-product
functions for macrocell combinatorial or registered logic

-8 product terms (arranged 1 per macrocell) add an additional
product term for macrocell sum-of-products functions or I/O pin
output enable control

At each input-line/product-term intersection there is an EEPROM mem­ory cell which determines whether or not there is a logical connection at
that intersection. Each product term is essentially a 32-input AND gate.
A product term which is connected to both the true and complement of
an input signal will always be FALSE and thus will not affect the OR
function that it drives. When all the connections on a product term are
opened, that term will always be TRUE.

Associated with each of the eight OR functions is a macrocell which can
be independently programmed to one of up to four different basic config­urations. The programmable macrocells allow each I/O to create
sequential or combinatorial logic functions of active-high or active-low
polarity, while providing two possible feedback paths into the array.

Three different device modes, Simple, Complex, and Registered, sup­port various user configurations. In Simple mode a macrocell can be
configured for combinatorial function with the output buffer permanently
enabled, or the output buffer can be disabled and the I/O pin used as a
dedicated input. In Complex mode a macrocell is configured for combi­natorial function with the output buffer enable controlled by a product
term. In Registered mode, a macrocell can be configured for registered
operation with the register clock and output buffer enable controlled
directly from pins, or can be configured for combinatorial function with
the output buffer enable controlled by a product term. In most cases the
device mode is set automatically by the development software, based
on the features specified in the design.

The three device modes support designs created explicitly for the

TM

PEEL

16CV8, as well as designs created originally for popular PLD
devices such as the 16R4, 16R8, and 16L8. Table 1 shows the device
mode used to emulate the various PLDs. Design conversion into the
16CV8 is accommodated by JEDEC-to-JEDEC translators available
from ICT, as well as several programmers which can read the original
PLD JEDEC file and automatically program the 16CV8 to perform the
same function.

AND/OR Logic Array

The programmable AND array of the PEEL
lines intersecting product terms. The input lines and product terms are
used as follows:

•

32 input lines:

-16 input lines carry the true and complement of the signals applied
to the 8 dedicated input pins

-16 additional lines carry the true and complement of 8 macrocell
feedback signals or inputs from I/O pins or the clock/ OE pins

TM

16CV8 is formed by input

When programming the PEEL

TM

16CV8, the device programmer first
performs a bulk erase to remove the previous pattern. The erase cycle
opens every logical connection in the array. The device is configured to
perform the user-defined function by programming selected connections

in the AND array. (Note that PEEL

TM

device programmers automatically
program all of the connections on unused product terms so that they will
have no effect on the output function.

Table 1 : PEEL

PLD Archit ec tu r e

TM

16CV8 Device Comp atibi lity

Compatibility

10H8 Simple
10L8 Simple
10P8 Simple
12H6 Simple
12L6 Simple
12P6 Simple
14H4 Simple
14L4 Simple
14P4 Simple
16H2 Simple

16HD8 Simple

16L2 Simple

16LD8 Simple

16P2 Simple
16H8 Complex
16L8 Complex
16P8 Complex
16R4 Registered
16R6 Registered
16R8 Registered

16RP4 Registered

PEELTM 16CV8

Device Mode

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PEELTM 16CV8

Table 1 : PEEL TM 16CV8 Devi ce Co mpati bili ty

PLD Architecture

Compatibility

16RP6 Registered
14RP8 Registered

PEELTM 16CV8

Device Mode

Programmable Macrocell

The macrocell provides complete control over the architecture of each
output. The ability to configure each output independently permits users

TM

to tailor the configuration of the PEEL

16CV8 to the precise require-

ments of their designs.

Macrocell Archit ecture

Each macrocell consists of an OR function, a D-type flip-flop, an output
polarity selector, and a programmable feedback path. Four EEPROM
architecture bits MS0, MS1, OP, and RC control the configuration of
each macrocell. Bits MS0 and MS1 are global, and select between Sim­ple, Complex, and Registered mode for the whole device. Bits OP and
RC are local for each macrocell; bit OP controls the output polarity and
bit RC selects between registered and combinatorial operation and also
specifies the feedback path. Table 2 shows the architecture bit settings
for each possible configuration.

Simple Mode

In Simple mode, all eight product terms feed the OR array which can
generate a purely combinatorial function for the output pin. The pro­grammable output polarity selector allows active-high or active-low logic,
eliminating the need for external inverters. For output functions, the
buffer can be permanently enabled. Feedback into the array is available
on all macrocell I/O pins, except for pins 15 and 16. Figure 6 shows the

logic array of the PEEL
Simple mode also provides the option of configuring an I/O pin as a ded-

icated input. In this case, the output buffer is permanently disabled, and
the I/O pin feedback is used to bring the input signal from the pin into the
logic array. This option is available for all I/O pins except pins 15 and 16.
Figure 3 shows the possible Simple mode macrocell configurations.

1

Simple Mode
Active Low Output

3

Simple Mode
I/O Pin Input

TM

16CV8 configured in Simple mode.

2

Simple Mode
Active High Output

VCC

VCC

Equivalent circuits for the possible macrocell configurations are illus­trated in Figures 3, 4, and 5. When creating a PEEL

TM

device design,
the desired macrocell configuration generally is specified explicitly in the
design file. When the design is assembled or compiled, the macrocell
configuration bits are defined in the last lines of the JEDEC program­ming file.

TM

Table 2 : PEEL

Config. Mode Architecture Bits

#MSOMS1OPRC

1 Simple 1 0 0 0 Combinatorial Active Low I/O Pin
2 Simple 1 0 1 0 Combinatorial Active High I/O Pin
3 Simple 1 0 X 1 None None I/O Pin
1 Complex 1 1 0 1 Combinatorial Active Low I/O Pin
2 Complex 1 1 1 1 Combinatorial Active High I/O Pin
1 Registered 0 1 0 0 Registered Active Low Registered

16CV8 Device Mode/Macrocell Configuration Bits

Figure 3 - Macrocell Configurations for Si mple mode of t he PEEL
16CV8 (see Figure 6 for Logic Array)

Function Polarity Feedback

TM

2 Registered 0 1 1 0 Registered Active High Registered
3 Registered 0 1 0 1 Combinatorial Active Low I/O Pin
4 Registered 0 1 1 1 Combinatorial Active High I/O Pin

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