ICST MK2049-01STR, MK2049-01SITR, MK2049-01S, MK2049-01SI Datasheet
MK2049-01
Communications Clock PLL
Description
The MK2049 is a Phase-Locked Loop (PLL) based
clock synthesizer, which accepts an 8 kHz clock
input as a reference and generates T1, E1, T3, E3,
and OC3 frequencies. The device can also accept a
T1, E1, T3, or E3 input clock and provide the
same output for loop timing. All outputs are
frequency locked together and to the input. This
allows for the generation of locked clocks to an
8 kHz backplane clock, simplifying clock
distribution in communications systems.
MicroClock can customize this device for many
other different frequencies. Contact your
MicroClock representative for more details.
For a fixed input-output phase relationship, refer
to the MK2049-02, -03, or -3x. The MK2049-3x
are 3.3 V devices.
Block Diagram
VDD GND
44
Features
• Packaged in 20 pin SOIC
• Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
• Accepts multiple inputs: 8 kHz backplane clock or
Loop Timing frequencies
• Locks to 8 kHz ±100 ppm (External mode)
• Exact internal ratios eliminate the need for external
dividers
• Zero ppm synthesis error in all output clocks.
• Output clock rates include T1, E1, T3, E3, and
OC3÷8
• 5 V ±5% operation
• Offered in Commercial and Industrial temperature
versions
FS3:0
Clock
Input
Reference
Crystal
MDS 2049-01 J 1 Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
4
Output
Buffer
Output
Buffer
Output
Buffer
CLK1
CLK2
8 kHz
X1
X2
Crystal
Oscillator
External/
Loop
Timing
Mux
CAP1
PLL
Clock
Synthesis,
Control, and
Jitter
Attenuation
Circuitry
CAP2
MK2049-01
Communications Clock PLL
Pin Assignment
FS1 FS0
X2
X1
VDD
VDD
VDD
GND
CLK2
CLK1
8K
1
2
3
4
5
6
7
8
9
10
20 pin (300 mil) SOIC
20
19
18
17
16
15
14
13
12
11
GND
CAP2
GND
CAP1
VDD
GND
ICLK
FS3
FS2
Output Decoding Table – External Mode (MHz)
Input FS3 FS2 FS1 FS0 CLK1 CLK2 Crystal
8 kHz 0 0 0 0 1.544 3.088 12.288
8 kHz 0 0 0 1 2.048 4.096 12.288
8 kHz 0 0 1 0 22.368 44.736 12.288
8 kHz 0 0 1 1 17.184 34.368 12.288
8 kHz 0 1 1 1 19.44 38.88 12.96
Output Decoding Table – Loop Timing Mode (MHz)
Input FS3 FS2 FS1 FS0 CLK1 CLK2 Crystal
1.544 1 0 0 0 1.544 3.088 12.288
2.048 1 0 0 1 2.048 4.096 12.288
44.736 1 0 1 0 22.368 44.736 12.288
34.368 1 0 1 1 17.184 34.368 12.288
• 0 = connect directly to ground, 1 = connect directly to VDD.
• Crystal is applied to pins 2 and 3; clock input is applied to pin 13.
Pin Descriptions
Number Name Type Description
1 FS1 I Frequency Select 1. Determines CLK input/outputs per tables above.
2 X2 O Crystal conection. Connect to a 12.288 MHz or 12.96 MHz crystal.
3 X1 I Crystal conection. Connect to a 12.288 MHz or 12.96 MHz crystal.
4 VDD P Connect to +5V.
5 VDD P Connect to +5V.
6 VDD P Connect to +5V.
7 GND P Connect to ground.
8 CLK2 O Clock 2 output determined by status of FS3:0 per tables above.
9 CLK1 O Clock 1 output determined by status of FS3:0 per tables above. CLK2 divided by 2.
10 8K O Recovered 8 kHz clock output. On External mode only.
11 FS2 I Frequency Select 2. Determines CLK input/outputs per tables above.
12 FS3 I Frequency Select 3. Determines CLK input/outputs per tables above.
13 ICLK I Input clock connection. Connect to 8 kHz backplane or to Loop Timing clock.
14 GND P Connect to ground.
15 VDD P Connect to +5V.
16 CAP1 LF Connect a 0.030 µF ceramic capacitor and a 7.5 MΩ resistor in series between this pin and CAP2.
17 GND P Connect to ground.
18 CAP2 LF Connect a 0.030 µF ceramic capacitor and a 7.5 MΩ resistor in series between this pin and CAP1.
19 GND P Connect to ground.
20 FS0 I Frequency Select 0. Determines CLK input/outputs per tables above.
Type: I = Input, O = output, P = power supply connection, LF = loop filter connection
MDS 2049-01 J 2 Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MK2049-01
ABSOLUTE MAXIMUM RATINGS (Note 1)
DC CHARACTERISTICS (VDD = 5 V unless noted)
AC CHARACTERISTICS (VDD = 5 V unless noted)
Communications Clock PLL
Electrical Specifications
Parameter Conditions Minimum Typical Maximum Units
Supply Voltage, VDD Referenced to GND 7 V
Inputs and Clock Outputs -0.5 VDD+0.5 V
Ambient Operating Temperature 0 70 °C
MK2049-01SI only -40 85 °C
Soldering Temperature Max of 10 seconds 250 °C
Storage Temperature -65 150 °C
Operating Voltage, VDD 4.75 5.25 V
Input High Voltage, VIH 2 V
Input Low Voltage, VIL 0.8 V
Output High Voltage IOH=-4mA VDD-0.4 V
Output High Voltage IOH=-25mA 2.4 V
Output Low Voltage IOL=25mA 0.4 V
Operating Supply Current, IDD No Load, VDD=5.0V 20 mA
Short Circuit Current Each output ±100 mA
Input Capacitance, FS3:0 7 pF
Input Frequency, External Mode ICLK 8.0000 kHz
Input Crystal Frequency X1, X2 12.2880 MHz
Input Crystal Frequency X1, X2. Selection 0111 12.9600 MHz
Output Clock Rise Time 0.8 to 2.0V 1.5 ns
Output Clock Fall Time 2.0 to 0.8V 1.5 ns
Output Clock Duty Cycle, High Time At VDD/2 40 49 to 51 60 %
Actual mean frequency error versus target Any clock selection 0 0 ppm
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
MDS 2049-01 J 3 Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MK2049-01
Communications Clock PLL
OPERATING MODES
The MK2049-01 has two operating modes: External and Loop Timing. Although both modes use an input
clock to generate various output clocks, there are important differences in their input requirements.
External Mode
The MK2049-01 accepts an external 8 kHz clock and will produce a number of common communication
clock frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as
narrow as 10 ns is acceptable.
Loop Timing Mode
This mode can be used to remove the jitter from standard high-frequency communication clocks. For T1
and E1 inputs, the CLK1 output will be the same as the input frequency, with CLK2 at twice the input
frequency. For T3 and E3 inputs, CLK1 will be 1/2 the input frequency and CLK2 will be the same as the
input frequency.
FREQUENCY LOCKING TO THE INPUT
In both modes, the output clocks are frequency-locked to the input. The output will remain at the specified
output frequency as long as the combined variation of the input frequency and the crystal does not exceed
100 ppm. For example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the
input frequency can vary by up to 60 ppm and still have the output clock remain frequency-locked.
INPUT AND OUTPUT SYNCHRONIZATION
The rising edges of CLK1 and CLK2 do not have a fixed phase alignment with the rising edge of ICLK.
Each time the device is powered-up, the phase relationship could change. Refer to one of the other
MK2049 versions (e.g., MK2049-02, -03, -34) if input-output phase alignment is important in your
application.
MDS 2049-01 J 4 Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
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