ICST MK1418S, MK1418STR, MK1420S, MK1420STR Datasheet

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ICST MK1418S, MK1418STR, MK1420S, MK1420STR Datasheet

MK1418/MK1420

OPL3, OPL4 + Codec Clock Source

Description

The MK1418 and MK1420 are the ideal way to generate clocks for new sound cards. The MK1420 provides clocks for Analog Devices’ AD1848, Crystal Semiconductor’s CS4231, and Yamaha’s OPL3L, OPL3LS, and OPL4. The MK1420 uses either a 14.318 MHz crystal, or a 14.318 MHz bus clock input to synthesize the clocks required to drive the codec, and the 33.868 MHz required for the FM or wavetable music synthesizer. The chips are ideal for add-in sound cards and motherboards with integrated sound. In an 8 pin SOIC, the MK1420 can save component count, board space, and cost over surface mount crystals, and increase reliability by eliminating three or four mechanical devices from the board.

MicroClock offers many other parts with stereo codec support. The MK1430 has 5 output clocks, the MK1448 has 7, the MK1444 has eight including DSP clocks, and the MK1450/1 offers Pentium™ and SCSI support, plus the stereo codec clocks.

Block Diagram

VDD GND

Features

• Packaged in 8 pin SOIC

Input crystal or clock frequency of 14.318 MHz

MK1418 is clock input only

MK1420 output clock frequencies of 16.934MHz, 24.576 MHz, 33.868 MHz, and 14.318 MHz

Advanced, low power CMOS process

Lowest jitter in industry for best audio performance

Insensitive to input clock duty cycle

50% (typ) 14.318 MHz duty cycle with crystal

AC Coupling/Portable Applications

For applications in portable computers, it is possible to drive the input clock with a 3.3V, 14.318MHz clock by a.c. coupling using a 0.01µF capacitor connected in series to the CLKIN pin. But the operating VDD on pin 2 must be 5V±10%. This technique is also effective if the input clock doesn’t meet the VIH and VIL specifications on page 3.

Additional Clocks or Features

If more than these four output clocks or features such as power down are needed, MicroClock has many other products in development. Consult MicroClock for your specific needs.

 

 

Output

16.934 MHz

 

 

Buffer

 

 

 

 

Clock Synthesis

Output

 

14.318 MHz

Circuitry

24.576 MHz

Buffer

crystal or clock

 

 

 

 

 

X1

 

Output

33.868 MHz

 

 

 

 

Buffer

Crystal

 

(MK1420 only)

 

 

Oscillator

 

 

 

X2

 

Output

14.318 MHz

 

 

 

 

Buffer

 

 

(MK1420 only)

 

 

 

MDS 1418/20 A

1

Revision 013098

Printed 11/15/00

MicroClock Division of ICS•1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax

MK1418/MK1420

OPL3, OPL4 + Codec Clock Source

Pin Assignments

 

 

 

 

MK1418

 

ICLK

 

1

8

 

 

 

 

 

 

 

 

7

 

VDD

 

2

 

 

 

 

 

 

GND

 

3

6

 

 

 

16.9M

 

4

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MK1420

 

X1

 

1

8

 

 

 

 

 

 

 

 

7

 

VDD

 

2

 

 

 

 

GND

 

3

6

 

 

 

16.9M

 

4

5

 

 

 

 

 

 

 

 

 

 

 

Suggested Layout

 

 

 

 

for MK1420

clock only

 

 

GND

 

14.318 MHz

 

 

 

 

 

VDD

 

crystal

 

 

Pin 1

8

 

 

 

 

GND

V

2

7

14.3MHz out

 

24.6M

0.1µF

 

33Ω (optional)

 

 

 

3

6

33.9MHz out

 

G

 

33Ω (optional)

 

 

4

5

 

 

 

 

X2

 

 

 

 

14.3M

33Ω (optional)

33Ω (optional)

 

33.9M

 

 

 

 

24.6M

 

16.9MHz out

24.6MHz out

 

 

 

 

Pin Descriptions for MK1420

Number

Name

Type

Description

1

X1

I

Crystal Connection. Connect to a 14.318 MHz crystal or clock.

2

VDD

P

Connect to +5V.

3

GND

P

Connect to ground.

4

16.9M

O

16.9344 MHz clock output for stereo codec.

5

24.6M

O

24.576 MHz clock output for stereo codec.

6

33.9M

O

33.868 MHz clock output for OPL4.

7

14.3M

O

14.318 MHz clock buffered output for OPL3 or PCMCIA controller.

8

X2

O

Crystal Connection to a 14.318 MHz crystal, or leave unconnected for clock input.

Key: I = Input, O = output, P = power supply connection

External Components/Crystal Selection

A minimum number of external components are required for proper oscillation. For a crystal input, one 22pF load capacitor should be connected to each of the X1 and X2 pins and ground, and a parallel resonant 14.318 MHz, 16pF load, crystal is recommended. Values near these are acceptable, as is a series resonant crystal, but either will result in frequencies which are slightly (up to 0.06%) different from the ideal. For a clock input, connect to X1 and leave X2 unconnected. A decoupling capacitor of 0.1µF should be connected between VDD and GND, and 33Ω terminating resistors may be used on the clock outputs. These terminating resistors are unnecessary for clock traces less than 1” (25mm).

MDS 1418/20 A 2 Revision 013098 Printed 11/15/00

MicroClock Division of ICS•1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax

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