ICST MK1704A, MK1704ATR Datasheet
MK1704A
ICRO
C
LOCK
Description
The MK1704A is an upgraded version of the
MK1704 and is recommended for all new designs.
It offers more reduction in the frequency
amplitude peaks, and will support frequencies up
to 140 MHz.
The MK1704A generates a low EMI output clock
from a clock input. The part is designed to dither
the LCD interface clock or other clocks for flat
panel graphics controllers. The MK1704A uses
ICS/MicroClock’s proprietary mixture of analog
and digital Phase-Locked Loop (PLL) technology
to synthesize the frequency, and our patented
technique to spread the frequency spectrum of the
output, thereby reducing the frequency amplitude
peaks by several dB.
Low EMI Clock Generator
Features
• Packaged in 8 pin SOIC
• Provides a spread spectrum output clock
• Supports leading flat panel controllers
• Accepts a clock input, provides same frequency
dithered output
• Optimized for higher resolutions that require up
to 140 MHz, as well as 40 MHz (SVGA) and
65 MHz (XVGA) clocks
• Peak reduction by 7dB - 14 dB typical on 3rd 19th odd harmonics
• Low EMI feature can be disabled
• 3.3 V or 5 V ±10% supply voltage
We offer many other clocks for computers and
computer peripherals. Consult us when you need
to remove crystals and oscillators from your board.
Block Diagram
VDD GND
S0
S1
Low EMI
Enable
Input Clock
Crystal
Oscillator
• Advanced, low power CMOS process
• See the MK1714-01 for a multiplier with low
EMI which can operate from a crystal
PLL Clock
Synthesis and
Spread Spectrum
Circuitry
Output
Buffer
Clock Out
MDS 1704A B 1 Revision 062599 Printed 11/15/00
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax
MK1704A
ICRO
C
LOCK
Low EMI Clock Generator
Pin Assignment
Clock Output Select Table (in MHz)
ICLK
VDD
GND
CLK
1 8
2
3
4
8 pin SOIC
DC
7
S0
6
S1
5
LEE
S1 S0 Min Nom Max Multiplier Mode vs. CLK
0 0 60 135 140 x1 * +0.5, -1.5%
0 1 60 80 120 x1 * +0.5, -1.5%
1 0 30 40 60 x1 SVGA Down 2.5%
1 1 40 65 100 x1 XGA +0.5, -1.5%
*Note: Use only MK1704A with date code of 9909 or later.
Input Freq. spread
Pin Descriptions
Pin # Name Type Description
1 ICLK I Connect to a clock input as shown in the table above.
2 VDD P Connect to +3.3V or +5V.
3 GND P Connect to ground.
4 CLK O Clock Output; equal to input frequency.
5 LEE I Low EMI Enable. Turns on the spread spectrum when high. Internal pull-up.
6 S1 I Frequency Select 1 Input. Selects input/output clock range per table above. Internal pull-up.
7 S0 I Frequency Select 0 Input. Selects input/output clock range per table above. Internal pull-up.
8 DC - Don't Connect. Do not connect anything to this pin.
Key: I = Input, O = output, P = power supply connection
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of
0.01µF should be connected between VDD and GND on pins 2 and 3, and a 33 Ω terminating resistor
may be used on the clock output if the trace is longer than 1 inch. The MK1704A is designed for use with a
clock input only. For a crystal input, use the MK1704S or the MK1714-01R.
MDS 1704A B 2 Revision 062599 Printed 11/15/00
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax
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