ICST MK1413S, MK1413STR Datasheet
PRELIMINARY INFORMATION
MPEG Audio Clock Synthesizer
MK1413
Description
The MK1413 is the ideal way to generate clocks
for MPEG audio devices in computers. The device
uses MicroClock’s proprietary mixture of analog
and digital Phase-Locked Loop (PLL) technology
to synthesize one of four frequencies from the
14.31818 MHz reference. In an 8 pin SOIC, the
MK1413 can save component count, board space,
and cost over crystals and oscillators, and increase
reliability by eliminating three expensive
mechanical devices from the board.
MicroClock offers many other clocks for
computers and computer peripherals. Consult
MicroClock when you need to remove crystals and
oscillators from your board.
Features
• Packaged in 8 pin SOIC
• Input crystal or clock frequency of 14.31818 MHz
• Provides master MPEG clocks for 32 kHz,
44.1 kHz and 48 kHz sampling rates
• Output clock frequencies of 8.192 MHz,
11.2896 MHz, 12.288 MHz, and 16.9344 MHz
• Low jitter
• 25mA drive capability at TTL levels
• 3.3V or 5V±10% supply voltage
• Advanced, low power CMOS process
Block Diagram
VDD GND
S1
S0
Clock Synthesis
and Control
14.31818 MHz
crystal
or clock
MDS 1413 B 1 Revision 091697 Printed 11/15/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com
X1
X2
Clock
Buffer/
Crystal
Oscillator
Circuitry
Output
Buffer
CLK
Pin Assignment
X1
VDD
GND
NC
1 8
2
3
4
8 pin SOIC
Pin Descriptions
PRELIMINARY INFORMATION
MK1413
MPEG Audio Clock Synthesizer
Audio Clock Output Select Table
X2
7
S0
6
S1
5
CLK
S1 S0 Audio Clock Accuracy
pin 6 pin 7 pin 5 (ppm)
0 0 8.192 MHz -2 ppm
0 1 11.2896 MHz -24 ppm
1 0 12.288 MHz -2 ppm
1 1 16.9344 MHz -24 ppm
Number Name Type Description
1 X1 I Crystal Connection. Connect to a 14.31818 MHz crystal or clock.
2 VDD P Connect to +3.3V or +5V.
3 GND P Connect to ground.
4 NC - No Connect.
5 CLK O Audio Clock Output as per table above.
6 S1 I Frequency Select 1 Input. Determines CLK output as per table above.
7 S0 I Frequency Select 0 Input. Determines CLK output as per table above.
8 X2 O Crystal Connection to a 14.31818 MHz crystal, or leave unconnected for clock input.
Key: I = Input, O = output, P = power supply connection
External Components/Crystal Selection
A minimum number of external components are required for proper oscillation. For a crystal input, one
load capacitor should be connected to each of the X1 and X2 pins and ground, and a parallel resonant
14.31818 MHz crystal is recommended. The value (in pF) of each crystal load capacitor should equal
(CL-4)*2, where CL is the crystal’s load (correlation) capacitance in pF. The frequency tolerance of the
crystal should be 50ppm or better. For a clock input, connect to X1 and leave X2 unconnected. A
decoupling capacitor of 0.1µF should be connected between VDD and GND on pins 2 and 3, and 33Ω
terminating resistor may be used on the clock output if the trace is longer than 1 inch.
MDS 1413 B 2 Revision 091697 Printed 11/15/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com
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