Integrated
Circuit
Systems, Inc.
ICS8431-01
200MHZ, LOW JITTER,
L VPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
,&6
HiPerClockS™
bandwidth PLL timing channel. A 16.666MHz crystal is used
as the input to the on-chip oscillator. The M is configured to
produce a fixed output frequency of 200MHz.
Programmable features of the ICS8431-01 support four
operational modes. The four modes are spread spectrum
clocking (SSC), non-spread spectrum clock and two test
modes which are controlled by the SSC_CTL[1:0] pins. Unlike other synthesizers, the ICS8431-01 can immediately
change spread-spectrum operation without having to reset
the device.
In SSC mode, the output clock is modulated in order to
achieve a reduction in EMI. In one of the PLL bypass test
modes, the PLL is disconnected as the source to the
differential output allowing an external source to be
connnected to the TEST_I/O pin. This is useful for incircuit testing and allows the differential output to be driven
at a lower frequency throughout the system clock tree. In the
other PLL bypass mode, the oscillator divider is used as the
source to both the M and the Fout divide by 2. This is useful
for characterizing the oscillator and internal dividers.
The ICS8431-01 is a general purpose clock
frequency synthesizer for IA64/32 application and
a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8431-01 consists of one independent low
FEATURES
• Fully integrated PLL
• Differential 3.3V L VPECL output
• 200MHz output frequency
• 48% to 52% duty cycle
• Crystal oscillator interface
• Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI. T ypical10dB EMI
reduction can be achieved with spread spectrum modulation
• LVTTL / L VCMOS control inputs
• PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
• 28 lead SOIC
• RMS cycle-to-cycle jitter of 2ps
• Typical cycle-to-cycle jitter of 18ps
• 0° to 85°C ambiant operating temperature
BLOCK DIAGRAM PIN ASSIGNMENT
nc
XTAL1
XTAL2
SSC_CTL0
SSC_CTL1
ICS8431CM-01 www.icst.com/products/hiperclocks.html REV. A JUNE 5, 2001
OSC
÷ 16
PHASE
DETECTOR
÷ M
SSC
Control
Logic
PLL
VCO
÷ 2
FOUT
nFOUT
TEST_I/O
1
SSC_CTL0
SSC_CTL1
TEST_I/O
1
nc
2
nc
3
nc
4
nc
5
nc
6
nc
7
nc
8
nc
9
10
11
VEE
12
13
VDD
14
ICS8431-01
28-Lead SOIC
M Package
Top View
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nc
VDDI
XTAL2
XTAL1
nc
nc
VDDA
VEE
RESERVED
nc
VDDO
FOUT
nFOUT
VEE
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
,91,9-1
82,42,32
11,01
21DNGrewoP.tuptuotsetdnaerocrofnipdnuorG
31O/I_TSET
72,41DDVrewoP.tuptuotsetdnaerocrofnipylppusrewoP
51DNGrewoP.tuptuorofnipdnuorG
71,61TUOF,TUOFntuptuO
81ODDVrewoP.tuptuorofnipylppusrewoP
02DEVRESERevreseR.nipevreseR
12EEVrewoP.nipdnuorG
22ADDVrewoP.nipylppusrewopLLP
62,522LATX,1LATXtupnI.tupnirotallicsolatsyrC
72IDDVrewoP.V3.3ottcennoC.nipylppusrewoperocdnatupnI
cndesunU.snipdesunU
,0LTC_CSS
1LTC_CSS
tupnIpulluP.slevelecafretniSOMCVL/LTTVL.sniplortnocCSS
/tupnI
tuptuO
ICS8431-01
200MHZ, LOW JITTER,
L VPECL FREQUENCY SYNTHESIZER
..elbaTnoitcnuF3elbaTnidenifedsademmargorP
.rezisehtnysehtrofsrevirdtuptuoniamerastuptuolaitnereffidesehT
LCEPVLdecnereferevitisopdetanimrethtiwelbitapmocerayehT
.cigol
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
NICecnaticapaCniPtupnI 4Fp
PULLUPRrotsiseRpulluPtupnI 15KΩ
NWODLLUPRrotsiseRnwodlluPtupnI 15KΩ
TABLE 3. SSC CONTROL INPUTS FUNCTION TABLE
stupnI
1LTC_CSS0LTC_CSS
00 lanretnIdelbasiDLATXf ÷ 23
01LLPdelbanEzHM002Z-iHtnecreP½=rotcaFnoitaludoM;CSStluafeD
10 lanretxEdelbasiDklCtseTtupnI
11LLPdelbasiDzHM002Z-iHnoitaludoMCSSoN
O/I_TSET
ecruoS
CSS
,TUOF
TUOFn
.noitaziretcarahcdnagubedesuohnirofdesU:1ETON
stuptuO
LATXf ÷ 61
÷ M
sedoMlanoitarepO
O/I_TSET
1ETON.edomtsetsredivid
1ETON;edoMcitsongaiD
zHM1( ≤ klCtseT ≤ )zHM002
NdnaM,rotallicso,rotallicsO;ssapybLLP
ICS8431CM-01 www.icst.com/products/hiperclocks.html REV. A JUNE 5, 2001
2
Integrated
Circuit
Systems, Inc.
ICS8431-01
200MHZ, LOW JITTER,
L VPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage 4.6V
Inputs -0.5V to VDD + 0.5V
Outputs -0.5V to VDDO + 0.5V
Ambient Operating T emperature 0°C to 85°C
Storage T emperature -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in
DC Characteristics
the
periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
DDVegatloVylppuSrewoP 531.33.3564.3V
ODDVegatloVylppuSrewoPtuptuO 531.33.3564.3V
ADDVegatloVylppuSrewoPgolanA 531.33.3564.3V
IDDVegatloVylppuSrewoPtupnI 531.33.3564.3V
EEI 041Am
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended
TABLE 4B. L VCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
,0LTC_CSS
HIVegatloVhgiHtupnI
LIVegatloVwoLtupnI
HIItnerruChgiHtupnI
LIItnerruCwoLtupnI
,1LTC_CSS
O/I_TSET
,0LTC_CSS
,1LTC_CSS
O/I_TSET
,0LTC_CSS
,1LTC_CSS
OI_TSET
,0LTC_CSS
,1LTC_CSS
OI_TSET
V531.3 ≤ DDV ≤ V564.32 3.0+DDVV
V531.3 ≤ DDV ≤ V564.33.0-8.0V
V564.3=NIV=DDV5Aµ
V0=NIV,V564.3=DDV051-Aµ
TABLE 4C. L VPECL DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
HOV1ETON;egatloVhgiHtuptuO 82.1-ODDV089.0-ODDVV
LOVegatloVwoLtuptuO1ETON;0.2-ODDV7.1-ODDVV
GNIWSVgniwSegatloVtuptuOkaeP-ot-kaeP006007058Vm
05htiwdetanimrettuptuO:1ETON Ω .V2-ODDVot
ICS8431CM-01 www.icst.com/products/hiperclocks.html REV. A JUNE 5, 2001
3
Integrated
Circuit
Systems, Inc.
ICS8431-01
200MHZ, LOW JITTER,
L VPECL FREQUENCY SYNTHESIZER
TABLE 5. CRYST AL CHARACTERISTICS
retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
noitallicsOfoedoM latnemadnuF
ycneuqerF 666.61zHM
ecnareloTycneuqerF 05-05+mpp
ytilibatSycneuqerF 001-001+mpp
leveLevirD 001Wµ
)RSE(ecnatsiseRseireStnelaviuqE 05
ecnaiticapaCtnuhS 37Fp
ecnaiticapaCdaoL 018123Fp
ecnatcudnIniPseireS 37Hn
egnaRerutarepmeTgnitarepO 007C°
gnigAC°52@raeyreP5-5+mpp
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C, 16.666MHZ CRYST AL
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
DOIREPt2ETON;doirePtuptuOegarevAzHM002=TUOF59945005sp
t
j)cc(ti
cdo;elcyCytuDtuptuO2ETONzHM002=TUOF8425%
Rt2,1ETON;emiTesiRtuptuO%08ot%02003054006sp
Ft2,1ETON;emiTllaFtuptuO%08ot%02003054006sp
latxFegnaRtupnIlatsyrC41666.6181zHM
mF
fmF
derCSS;noitcudeRlartcepS2,1ETON701Bd
ELBATSttuptuOkcolCelbatSotpu-rewoP 01sm
t
j.snoitinifed56DSEJCEDEJotmrofnoccdo,Ft,Rt,)cc(ti
2,1ETON
2,1ETON
2ETON;rettiJelcyC-ot-elcyCzHM002=TUOF8103sp
;ycneuqerFnoitaludoMCSS
;rotcaFnoitaludoMCSS
.delbanegnikcolcmurtcepSdaerpS:1ETON
05htiwdetanimretstuptuO:2ETON Ω .V2-ODDVot
0333.33zHK
4.06.0%
Ω
ICS8431CM-01 www.icst.com/products/hiperclocks.html REV. A JUNE 5, 2001
4
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
ICS8431-01
200MHZ, LOW JITTER,
L VPECL FREQUENCY SYNTHESIZER
Clock Inputs
and Outputs
X_CLK, 1X_FOUT
nX_CLK, n1X_FOUT
nX_CLK, n1X_FOUT
X_CLK, 1X_FOUT
80%
20%
➤
➤
trise tfall
FIGURE 1 — INPUT AND OUTPUT SLEW RATES
➤
t
cycle n
t
jit(cc) = tcycle n –tcycle n+1
➤
➤
FIGURE 2 — CYCLE-TO-CYCLE JITTER
➤
Pulse Width (
➤
t
pw)
odc =
➤
t
PERIOD
t
pw
t
PERIOD
80%
➤
t
cycle n+1
➤
Vswing
20%
➤
➤
➤
➤
FIGURE 3 — odc & tPERIOD
ICS8431CM-01 www.icst.com/products/hiperclocks.html REV. A JUNE 5, 2001
5
Integrated
Circuit
Systems, Inc.
CRYSTAL INPUT AND OSCILLATOR INTERFACE
The ICS8431-01 features an internal oscillator that uses an
external quartz crystal as the source of its reference frequency .
A 16.666 MHz crystal divided by 16 before being sent to the phase
detector provides the reference frequency. The oscillator is a
series resonant, multi-vibrator type design. This design provides
better stability and eliminates the need for large on chip capacitors.
Though a series resonant crystal is preferred, a parallel resonant
crystal can be used. A parallel resonant mode crystal used in a
series resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified. A few hundred ppm translates
to KHz inaccuracy. In general computing applications this level
of inaccuracy is irrelevant. If better ppm accuracy is required, an
external capacitor can be added to a parallel resonant crystal in
series to pin 25.
Figure 1A
Figures 1A, 1B, and 1C show various crystal parameters
which are recommended only as guidelines. Figure 1A shows
how to interface a capacitor with a parallel resonant crystal.
Figure 1B shows the capacitor value needed for the optimum
PPM performance over various parallel resonant crystals.
Figure 1C shows the recommended tuning capacitance for a
16.666MHz parallel resonant crystal.
shows how to interface with a crystal.
ICS8431-01
200MHZ, LOW JITTER,
L VPECL FREQUENCY SYNTHESIZER
ICS8431-01
XTAL2
(Pin 26, SOIC)
XTAL1
(Pin 25, SOIC)
Quartz Crystal Selection:
(1) Raltron Series Resonant: AS-16.66-S-SMD-T -MI
(2) Raltron Parallel Resonant: AS-16.66-18-SMD-T -MI
FIGURE 1A. CRYSTAL INTERFACE
➤
Optional
FIGURE 1B. Recommended tuning capacitance for various parallel
resonant crystals.
60
14.318
50
40
30
20
10
Series Capacitor, C1 (pF)
0
15.000
16.667
14 15 16 17 18 19 20 21 22 23 24 25
Crys t al F requency (MHz )
19.440
20.000
24.000
IGURE 1C. Recommended tuning capacitance for 16.666MHz
F
parallel resonant crystal.
100
80
60
40
20
0
0 102030405060
-20
-40
-60
Frequency Accuracy (ppm)
-80
-100
16.666MHz
Series Capacit or, C1 (pF)
ICS8431CM-01 www.icst.com/products/hiperclocks.html REV. A JUNE 5, 2001
6
Integrated
Circuit
Systems, Inc.
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a
30KHz triangle waveform is used with 0.5% down-spread
(+0.0% / -0.5%) from the nominal 200MHz clock frequency.
An example of a triangle frequency modulation profile is shown
Figure 2
in
• Fnom = Nominal Clock Frequency in Spread OFF mode
• Fm = Nominal Modulation Frequency (30KHz)
• δ = Modulation Factor (0.5% down spread)
(1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t < ,
(1 - δ) fnom - 2 fm x δ x fnom x t when < t <
Fnom
below. The ramp profile can be expressed as:
(200MHz with 16.666MHz IN)
1
2 fm
➤
1
2 fm
1
fm
ICS8431-01
200MHZ, LOW JITTER,
L VPECL FREQUENCY SYNTHESIZER
The ICS8431-01 triangle modulation frequency deviation will
not exceed 0.6% down-spread from the nominal clock frequency (+0.0% / -0.5%). An example of the amount of down
spread relative to the nominal clock frequency can be seen in
the frequency domain, as shown in
width to the fundamental frequency is typically 0.4%, and will
not exceed 0.6%. The resulting spectral reduction will be
greater than 7dB, as shown in Figure 3. It is important to note
the ICS8431-01 7dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the
same as the system EMI reduction.
Figure 3.
∆ − 10 dBm
The ratio of this
(1 - δ) Fnom
0.5/fm
FIGURE 2. TRIANGLE FREQUENCY MODULATION
1/fm
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry , the power supply pins
are vulnerable to random noise. The ICS8431-01 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD, VDDI, VDDA, and
VDDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be used
for each pin. To achieve optimum jitter performance, better
power supply isolation is required.
10Ω along with a 10µF and a .01µF bypass capacitor should
be connected to each power supply pin.
Figure 4
illustrates how a
➤
B
A
δ = .4%
FIGURE 3. 200MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN
(A) SPREAD-SPECTRUM OFF
(B) SPREAD-SPECTRUM ON
3.3V
VDD
.01µF
VDDA
.01µF
FIGURE 4. POWER SUPPLY FILTERING
10Ω
10 µF
ICS8431CM-01 www.icst.com/products/hiperclocks.html REV. A JUNE 5, 2001
7
Integrated
Circuit
Systems, Inc.
TERMINATION FOR PECL OUTPUTS
The clock layout topology shown below is typical for
IA64/32 platforms. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/PECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality . These outputs are designed to
ICS8431-01
200MHZ, LOW JITTER,
L VPECL FREQUENCY SYNTHESIZER
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize signal distortion. There are a few simple termination
schemes.
Figures 5A and 5B
are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
show two different layouts which
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
5
FINFOUT
Zo = 50Ω Zo = 50Ω
3.3V
5
Z
o
2
Z
o
2
FOUT FIN
RTT =
(VOH + VOL / VCC –2) –2
50Ω
1
Z
o
FIGURE 5A. L VPECL OUTPUT TERMINATION
RTT
50Ω
➤
VCC-2V
Z
= 50Ω Zo = 50Ω
o
3
Z
o
2
3
Z
o
2
FIGURE 5B. L VPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
The schematic of the ICS8431-01 layout example used in this layout guideline is shown in
PCB board layout for this example is shown in
Figure 6B.
This layout example is used as a general guideline. The layout in the actual
system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of
the P .C. board.
U1
1
nc
2
nc
3
nc
4
nc
5
nc
6
nc
7
nc
8
nc
9
nc
10
SSC_CTL0
11
SSC_CTL1
12
VEE
13
VDD
C1
0.1uF
TEST_IO
14 15
VDD VEE
8431-01
VDDI
XTAL2
XTAL1
VDDA
VEE
VDDO
FOUT
nFOUT
28
nc
27
VDD
26
25
24
nc
23
nc
22
21
20
nc
19
nc
VDD
18
17
16
C2
0.1uF
X1
VDDA
C3
0.01uF
C6
0.01uF
R5
10
C4
10uF
Zo = 50 Ohm
TL1
Zo = 50 Ohm
TL2
Figure 6A.
Termination A
VDD0
R1
125
IN+
IN-
R2
84
The ICS8431-01 recommended
Termination
B (not shown
in the layout)
IN+
IN-
R3
125
R4
84
R1
R2
50
50
R3
50
FIGURE 6A. RECOMMENDED SCHEMATIC LAYOUT
ICS8431CM-01 www.icst.com/products/hiperclocks.html REV. A JUNE 5, 2001
8
Integrated
Circuit
Systems, Inc.
ICS8431-01
200MHZ, LOW JITTER,
L VPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
The Crystal X1 is Raltron Part # AS-16.666-18-SMD.
POWER AND GROUNDING
Place the decoupling capacitors C1, C2 and C3, C4, C5, C6 as
close as possible to the power pins. If space allows, placing the
decoupling capacitor at the component side is preferred. This can
reduce unwanted inductance between the decoupling capacitor
and the power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If VDDA shares the same power supply with VDD, insert the RC
filter R5, C3, and C4 in between. Place this RC filter as close to
the VDDA as possible.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality . Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The trace shape and the trace
delay might be restricted by the available space on the board and
the component location. While routing the traces, the clock signal
traces should be routed first and should be locked prior to routing
other signals traces.
• The traces with 50Ω transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
• Keep the clock trace on same layer. Whenever possible,
avoid any vias on the clock traces. Any via on the trace
can affect the trace characteristic impedance and hence
degrade signal quality.
• T o prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
• Make sure no other signal trace is routed between the
clock trace pair.
The matching termination resistors R1, R2, R3 and R4 should be
located as close to the receiver input pins as possible. Other termination scheme can also be used but is not shown in this example.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
26 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
C1
U1
ICS8431-01
C6
X1
C3
FIGURE 6B. PCB BOARD LAYOUT FOR ICS8431-01
C4
R5
C2
TL1 (50 Ohm)
TL2 (50 Ohm)
Close to the input
pins of the
receiver
IN+
IN-
GND
VDD
Signals
VIA
R1
R2
R3
R4
ICS8431CM-01 www.icst.com/products/hiperclocks.html REV. A JUNE 5, 2001
9
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - M SUFFIX
ICS8431-01
200MHZ, LOW JITTER,
L VPECL FREQUENCY SYNTHESIZER
N
1
D
A2
e
TABLE 7. PACKAGE DIMENSIONS
C
1528
H
E
14
h x 45º
A
A1
B
SEATING
PLANE
.10 (.004)
L
α
LOBMYS
N82
A--56.2--401.0
1A01.0--0400.0--
2A50.255.2180.0001.0
B33.015.0310.0020.0
C81.023.0700.0310.0
D07.7104.81796.0427.0
E04.706.7192.0992.0
eCISAB72.1CISAB050.0
H00.0156.01493.0914.0
h52.057.0010.0920.0
L04.072.1610.0050.0
α
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-013, MO-1 19
ICS8431CM-01 www.icst.com/products/hiperclocks.html REV. A JUNE 5, 2001
NIMXAMNIMXAM
°0 °8 °0 °8
sretemilliMsehcnI
10
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
10-MC1348SCI10-MC1348SCICIOSdaeL82ebuTreP62C°58otC°0
T10-MC1348SCI10-MC1348SCIleeRdnaepaTnoCIOSdaeL820001C°58otC°0
ICS8431-01
200MHZ, LOW JITTER,
L VPECL FREQUENCY SYNTHESIZER
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
ICS8431CM-01 www.icst.com/products/hiperclocks.html REV. A JUNE 5, 2001
11
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