ICST AV9248F-81, ICS9248F-81 Datasheet

Integrated Circuit Systems, Inc.

General Description Features

ICS9248 -81

Block Diagram

Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation

Frequency Generator & Integrated Buffers

9248-81 Rev E 10/12/99

Pin Configuration

 Generates the following system clocks:

- 3 CPU(2.5V/3.3V) up to 133.3MHz.

- 6 PCI(3.3V) (including 1 free-running)

- 13 SDRAMs(3.3V) up to 133.3MHz.

- 3 REF (3.3V) @ 14.318MHz

- 1 clock @ 24/14.3 MHz selectable output for SIO

- 1 Fixed clock at 48MHz (3.3V)

- 1 IOAPIC @ 2.5V / 3.3V

 Skew characteristics:

- CPU  CPU<175ps

- SDRAM  SDRAM < 250ps

- CPUSDRAM < 500ps

- CPU(early)  PCI : 1-4ns (typ. 3ns)

- PCI  PCI <500ps

 Supports Spread Spectrum modulation ±0.25 & ±0.5%

center spread

 Serial I

C interface for Power Management, Frequency

Select, Spread Spectrum.

 Efficient Power management scheme through PCI,

SDRAM, CPU STOP CLOCKS and PD#.  Uses external 14.318MHz crystal  48 pin 300mil SSOP.

48-Pin SSOP

Power Groups

VDDREF = REF [2:0], X1, X2 VDDPCI = PCICLK_F, PCICLK [4:0] VDDSD/C = SDRAM [11:0], supply for PLL core, 24 MHz, 48MHz VDD/CPU = CPUCLK [3:1] VDDLAPIC = IOAPIC GNDFIX = Ground for fixed clock PLL and output buffers

* Internal Pull-up Resistor of 120K to 3.3V on indicated inputs

The ICS9248-81 is the single chip clock solution for Desktop/ Notebook designs using the SIS style chipset. It provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-81 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. The SD_SEL latched input allows the SDRAM frequency to follow the CPUCLK frequency(SD_SEL=1) or other clock frequencies (SD_SEL=0)

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

ICS9248-81

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor

to program logic Hi to VDD or GND for logic low.

Pin number Pin name Type Description

1 VDDR /X Power Isolated 3. 3 V p ower f or c ryst al & referenc e

REF 0 Outp ut 3.3V , 14.318 MHz referenc e c loc k out put .

Mode Input Funct ion s ele c t pin, 1= des k t op m ode, 0= m obile m ode . Lat c hed input .

3,9,16, 22,

27,33, 39

GND Power 3.3 V Ground

4 X1 Input 14.318 M Hz c r

st al input

5 X2 Outp ut 14.318 M Hz c r

st al out put

6,14 VDDP C I Power 3 .3 V powe r for the P CI c loc k out puts

FS 1 Input Lo

ic input frequency select bit. Input lat c hed at power-on.

PCI CLK_F Outp ut 3.3 V free runnin

PCI c loc k outp ut, will not be s to pped by the PCI_STOP#

PCICLK 0 Output 3.3 V P CI c loc k outputs ,

enerating timing requirements for P entium I I

FS 2 Input Lo

ic input frequency select bit. Input lat c hed at power-on.

13, 12, 11, 10 PCI CLK [ 4:1] Outp ut 3.3 V P CI clo c k outpu ts , generati ng tim i ng requirem ents f or Pen tiu m II

15,28,29,31,32,

34,35,37,38

SDRA M 12,

SDRAM [7:0]

Outp ut SDRAM cl oc k outp uts . Frequency is s elec t ed by S D-Se l latc h ed input .

SDRA M 11 Output SD RA M c loc k out puts . Freque nc y is s elec t ed by S D-S el lat ch ed input .

CPU_ STO P# Input

As y nchronous act ive low input pin used to st op the CPUCLK in low state, all other clock s will co ntinue to run. The CPUCLK will hav e a "Turnon" latenc y of at leas t 3 CP U c loc k s .

SDRA M 10 Output SD RA M c loc k out put s . F re

uency is s ele ct ed by SD-SEL latched input.

PCI-STOP# Input

Sy nc h ronous ac tiv e l ow input us ed to st op t he P CI CLK in a low s t ate. I t will no t effect PCICLK_F or an

other outputs.

19 V DDS D/ C Power 3.3 V pow er for SD RA M out puts and c o re

SDRA M 9 Out put S DRA M c loc k out put s . F re

uency is s ele ct ed by SD-Sel latc hed input.

SDRAM_STOP# Input

As y nchronous act ive low input used to s top the SDRA M in a low state. It will not effect any other outputs.

SDRA M 8 Out put S DRA M c loc k out put s . F re

uency is s ele ct ed by SD-Sel latc hed input.

PD# Input

As y nchronous act ive low input pin used to power down the devic e into a low power state. The internal cloc k s are disabled and the VCO and t he cry s tal are stopped. The latenc

of the power down will not be greater than 3ms .

23 SDATA Input

Data input for I

C serial input .

24 SCLK Input

Clock input of I

C input

SE L24_14# Input

This input pin c ontrols the f requency of the S IO . I f logic 0 at power on SIO=14.318 MHz . If lo

ic 1 at powe r-on S I O=24M Hz .

SIO Output Super I/O output. 24 or 14.318 MHz. S electable at power-up b

SE L24_14MHz

FS 0 I np ut Logic input f requency s elect bit . I nput lat ched at po wer-on.

48 MHz Output

3.3 V 48 M Hz c loc k out put , f ix ed f requenc y c loc k t ypi c ally us ed wit h USB devic es

30,36 VDDS DR Power 3.3 V power for SDRAM out puts

40,41,43 CPUCLK [ 3:1] 0utput 2.5 V CPU and Hos t c loc k outputs

42 VDDLCPU Power 2.5 V power for CPU

REF 2 Outp ut 3.3V , 14.318 MHz referenc e c loc k out put .

CPU3 .3#_2.5 Inp ut

This pin s elect s t he operating voltage for the CPU. I f logic 0 at power on CPU=3.3 V and i f logic 1 at powe r on CPU=2.5 V operat ing v olt age.

45 GNDL Power 2.5 V Ground for the IOAP IC or CPU

REF 1 Outp ut 3.3V , 14.318 MHz referenc e c loc k out put .

SD_SE L Input This input pin c ontrols the f re

uency of the SDRAM. 47 IOA P IC Output 2.5V fix ed 14.318 M Hz IOAPIC c loc k outputs 48 V DDLAPIC Power 2.5 V power for IOAPIC

1,2

ICS9248-81

Power Management Functionality

Mode Pin - Power Management Input Control

CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.

PD# CPU_STOP# PCI_STOP# SDRA M_STOP

PCICLK

(0:4)

SDRAM

(0:12)

PCICLK_F CPUCLK

Crystal

OSC

VCO

0X X X

Stopped

Low

Stopped

Low

Stopped

Low

Stopped

Low

Stopped

Low

Stopped

Low

1 1 1 1 Running Running Running Running Running Running 1 1 1 0 Running

Stopped

Low

Running Running Running Running

11 0 1

Stopped

Low

Running Running Running Running Running

11 0 0

Stopped

Low

Stopped

Low

Running Running Running Running

1 0 1 1 Running Running Running

Stopped

Low

Running Running

1 0 1 0 Running

Stopped

Low

Running

Stopped

Low

Running Running

10 0 1

Stopped

Low

Running Running

Stopped

Low

Running Running

10 0 0

Stopped

Low

Stopped

Low

Running

Stopped

Low

Running Running

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ICS9248-81

Functionality

VDD1, 2, 3, 4 = 3.3V±5%, V

DDL

= 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C

Crystal (X1, X2) = 14.31818MHz

SD_SEL FS2 FS1 FS0

CPU

MHZ

SDRAM

MHZ

PCI

MHZ

REF, IOAPIC

MHZ

0 0 0 0 90.00 90.00 30.00 14.318 0 0 0 1 66.70 100.05 33.35 14.318 0 0 1 0 95.00 63.33 31.66 14.318 0 0 1 1 100.00 66.66 33.33 14.318 0 1 0 0 100.00 75.00 30.00 14.318 0 1 0 1 112.00 74.66 37.33 14.318 0 1 1 0 124.00 82.66 31.00 14.318 0 1 1 1 133.30 88.86 33.32 14.318 1 0 0 0 66.70 66.70 33.35 14.318 1 0 0 1 75.00 75.00 30.00 14.318 1 0 1 0 83.30 83.30 33.32 14.318 1 0 1 1 95.00 95.00 31.66 14.318 1 1 0 0 100.00 100.00 33.33 14.318 1 1 0 1 112.00 112.00 37.33 14.318 1 1 1 0 124.00 124.00 31.00 14.318 1 1 1 1 133.30 133.30 33.33 14.318

ICS9248-81

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.

Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I2C programming application note.

How to Write:

 Controller (host) sends a start bit.  Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge  Controller (host) sends a dummy command code  ICS clock will acknowledge  Controller (host) sends a dummy byte count  ICS clock will acknowledge  Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.  Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.  Controller (host) sends the read address D3

(H)

 ICS clock will acknowledge  ICS clock will send the byte count  Controller (host) acknowledges  ICS clock sends first byte (Byte 0) through byte 5  Controller (host) will need to acknowledge each byte  Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

(H)

Byte Count

ACK

Byte

ACK

Byte 1

ACK

Byte

ACK

Byte

ACK

Byte 4

ACK

Byte

ACK

Stop Bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit Address

(H)

Dummy Command Code

Dummy Byte Count

Byte 0

Byte 1

ACK

Byte 2

Byte 3

Byte 4

Byte 5

Stop Bit

How to Write:

ICS9248-81

Byte 0: Functionality and frequency select register (Default = 0)

Serial Configuration Command Bitmap

Note 1: Default at power-up will be for latched logic inputs to define frequency. Note 2: PWD = Power-Up Default

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