ICST AV2495N, AV2495M Datasheet
Dual Video/Memory Clock Generator
Integrated
Circuit
Systems, Inc.
ICS2495
Notes:
1. ICS2495M(SOIC) pinout is identical to ICS2495N(DIP).
Pin Configuration
XTAL2 1 16 XTAL1
EXTFREQ 2 15 VCLK
FS0 3 14 XTALOUT
FS1 4 13 VSS
STROBE 5 12 VDD
FS2 6 11 N/C
FS3 7 10 MCLK
MS0 8 9 MS1
16-Pin DIP or SOIC
Features
•• Low cost - eliminates need for multiple crystal clock
oscillators in video display subsystems
•• Mask-programmable frequencies
•• Pre-programmed versions for Industry Standard VGA
chips
•• Glitch-free frequency transitions
•• Internal clock remains locked when the external frequency
input is selected
•• Low power CMOS device technology
•• Small footprint - 16-pin DIP or SOIC
•• Buffered Xtal Out
•• Integral Loop Filter components
•• Fast acquisition of selected frequencies, strobed or non-
strobed
•• Guaranteed performance up to 135 MHz
•• Excellent power supply rejection
•• Advanced PLL for low phase-jitter
•• Frequency change detection circuitry enhances new fre-
quency acquisition and eliminates problems caused by
programs that rewrite frequency information
Description
The ICS2495 Clock Generator is an integrated circuit dual
phase-locked loop frequency synthesizer capable of generating
16 video frequencies and 4 memory clock frequencies for use
with high performance video display systems. Utilizing CMOS
technology to implement all linear, digital and memory functions, the ICS2495 provides a low-power, small-footprint,
low-cost solution to the generation of video dot clocks. Outputs
are compatible with XGA, VGA, EGA, MCGA, CGA, MDA,
as well as the higher frequencies needed for advanced applications in desktop publishing and workstation graphics. Provision is made via a single level custom mask to implement
customer specific frequency sets. Phase-locked loop circuitry
permits rapid glitch-free transitions between clock frequencies.
In addition to providing 16 clock rates, the ICS2495 has
provisions to multiplex an externally-generated signal source
into the VCLK signal path. Internal phase-locked frequencies
continue to remain locked at their preset values when this mode
is selected. This feature permits instantaneous transition from
an external frequency to an internally-generated frequency.
Printed circuit board testing is simplified by the use of these modes
as an external clock generated by the ATE tester can be fed
through, permitting synchronous testing of the entire system.
ICS2595RevA090694
Figure 1
VCLK
XTALOUT
N/C
MCLK
MS1
EXTFREQ
FS0
FS1
STROBE
FS2
FS3
MS0
10
C3 C2
.1 22
ICS2495
5.0V
NOTES: FS3-FS0, MS1-MS0, EXTFREQ, and STROBE inputs are all equipped with pull-ups and need not be tied high.
Mount decoupling capacitors as close as possible to the device and connect device ground to the ground plane where available.
Mount crystal and its circuit traces away from switching digital lines and the VCLK, MCLK and XTALOUT lines.
Reference Oscillator & Crystal Selection
In cases where the on-chip crystal oscillator is used to generate
the reference frequency, the accuracy of the crystal oscillation
frequency will have a very small effect on output accuracy.
The external crystal and the on-chip circuit implement a Pierce
oscillator. In a Pierce oscillator, the crystal is operated in its
parallel-resonant (also called anti-resonant mode). This means
that its actual frequency of oscillation depends on the effective
capacitance that appears across the terminals of the quartz
crystal. Use of a crystal that is characterized for use in a
series-resonant circuit is fine, although the actual oscillation
frequency will be slightly higher than the value stamped on the
crystal can (typically 0.025%-0.05% or so). Normally, this
error is not significant in video graphics applications, which is
why the ICS2495 will typically derive its frequency reference
from a series resonant crystal connected between pins 1 and
16.
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, the crystal should be
mounted as close as possible to the package. Avoid routing
digital signals or the ICS2495 outputs underneath or near these
traces. It is also desirable to ground the crystal can to the
ground plane, if possible.
Power Supply Conditioning
The ICS2495 is a member of the second generation of dot clock
products. By incorporating the loop filter on chip and upgrading the VCO, the ease of application has been substantially
improved over earlier products. If a stable and noise-free power
supply is available, no external components are required. However, in most applications it is judicious to decouple the power
supply as shown in Figure 1.
Layout Considerations
Utilizing the ICS2495 in video graphics adapter cards or on
PS2 motherboards is simple, but does require precautions in
board layout if satisfactory jitter-free performance is to be
realized. Care should be exercised to ensure that components
not related to the ICS2495 do not share its ground. In applications utilizing a multi-layer board, V
SS
should be directly
connected to the ground plane.
Frequency Reference
The internal reference oscillator contains all of the passive
components required. An appropriate crystal should be connected between XTAL1 (16) and XTAL2 (1). In IBM compat-
ible applications this will typically be a 14.31818 MHz crystal,
but fundamental mode crystals between 10 MHz and 25 MHz
have been tested. Maintain short lead lengths between the
crystal and the ICS2495. In some applications, it may be
desirable to utilize the bus clock. If the signal amplitude is
equal to or greater than 3.5 volts, it may be connected directly
to XTAL1 (16). If the signal amplitude is less than 3.5 volts,
connect the clock through a .047 microfarad capacitor to
XTAL1 (16), and keep the lead length of the capacitor to
XTAL1 (16) to a minimum to reduce noise susceptibility. This
input is internally biased at V
DD/
2. Since TTL compatible
clocks typically guarantee a V
OH
of only 2.8V, capacitively
coupling the input restores noise immunity. The ICS2495 is
not sensitive to the duty cycle of the bus clock; however, the
quality of this signal varies considerably with different motherboard designs. As the quality of this signal is typically outside
of the control of the graphics adapter card manufacturer, it is
suggested that this signal be buffered on the graphics adapter
board. XTAL2 (1) must be left open in this configuration.
ICS2495
2
Buffered XTALOUT
In motherboard applications it may be desirable to have the
ICS2495 provide the bus clock for the rest of the system. This
eliminates the need for an additional 14.31818 MHz crystal
oscillator in the system, saving money as well as board space.
Depending on the load, it may be judicious to buffer XTALOUT when using it to provide the system clock.
Output Circuit Considerations
As the dot clock is usually the highest frequency present in a
video graphics system, consideration should be given to EMI.
To minimize problems with meeting FCC EMI requirements,
the trace which connects VCLK or MCLK and other compo-
nents in the system should be kept as short as possible. The
ICS2495 outputs have been designed to minimize overshoot.
In addition, it may be helpful to place a ferrite bead in these
signal paths to limit the propagation of high-order harmonics
of this signal. A suitable device would be a Ferroxcube 56-59065/4B or equivalent. This device should be placed physically
close to the ICS2495. A 33 to 47 Ohm series resistor, sometimes called source termination, in this path may be necessary
to reduce ringing and reflection of the signal and may thereby
reduce phase jitter as well as EMI.
External Frequency Sources
EXTFREQ on versions so equipped by the programming, is
an input to a digital multiplexer. When this input is enabled by
the FS0-3 selection, the signal driving pin 2 will appear at
VCLK (15) instead of the PLL output. Internally, the PLL will
remain in lock at the frequency selected by the ROM code.
The programming option also exists to output the crystal oscillator output on VCLK. In the case where XTAL1 is being
driven by an external oscillator, then this frequency would
appear on VCLK if so programmed.
Digital Inputs
FS0 (3), FS1 (4), FS2 (6), and FS3 (7), are the TTL compatible
frequency select inputs for the binary code corresponding to
the frequency desired. STROBE (5) when high, allows new
data into the frequency select latches; and when low, prevents
address changes per Figure 2. The internal power-on-clear
signal will force an initial frequency code corresponding to an
all zeros input state. MS0 (8) and MS1 (9) are the correspond-
ing memory select inputs and are not strobed.
ICS2495
3
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