ICST AV2008BY, AV2008BV Datasheet

Integrated
Circuit
Systems, Inc.

General Description Features

ICS2008B

ICS2008B Rev B 6/6/01

Block Diagram

SMPTE Time Code Receiver/Generator

• Internal and external sync sources

– Genlock to video or house sync inputs
– Internally generated timing from oscillator input
– External click input

• LTC and VITC Generators

– Real Time SMPTE Rates: 30 Hz , 29.97 Hz,

25 Hz, 24 Hz
– Time Code Modes: Drop Frame and Color Frame
– VITC can be inserted on two lines from 10-40

(SMPTE specifies lines 10-20)
– Jam Sync, freewheeling, error bypass/correction,

and plus-one-frame capability

• LTC Receiver

– Meets SMPTE and EBU LTC specifications
– Synchronize bit rates from 1/30th nominal to 80X

nominal playback speed.

• VITC Receiver

– Reads code from any or all selected scan lines.
– Meets SMPTE VITC specifications

New, Improved Features

• Time Code Burn-in Window with programmable
position, size and character attributes

• Internal Timer, allows 1/4 Frame MIDI Time Code
Messages

• LTC edge rate control, conforms to EBU Tr and Tf
specification

• Improved video timing lock during VCR pause and
shuttle modes

• VITC search mode, will search through VBI lines until
VITC is found

• New U AR T frequency of 38.4 K baud for tape transport
control

• Improved video output performance

The ICS2008B, SMPTE Time Code Receiver / Generator
chip, is a VLSI device designed in a low power CMOS
process. This device provides the timing coordination for
Multimedia sight and sound events. Although it is aimed at
a PC Multimedia environment, the ICS2008B is easily
integrated into products requiring SMPTE time code
generation and/or reception in LTC (Longitudinal Time
Code) and/or VITC (Vertical Interval Time Code) formats
and MTC (MIDI Time Code) translation.

Taking its input from composite video, S-Video, or an
audio track, the ICS2008B can read SMPTE time code in
VITC and L TC formats. T ime code output formats are L T C
and VITC. All are available simultaneously. A UART is
provided for the user to support MTC or tape transport
control.

The processor interface is compatible with the IBM PC and
ISA bus compatible computers and is easily interfaced to
other processors.

The ICS2008B is an improved version of the ICS2008,
with additional features and capabilities.

ICS2008 ICS2008B 2008 2008B

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

ICS2008B

2

ICS2008B Rev B 6/6/01

Package Pinouts

181920 21 22 23 24 25 26 27 28

29

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65432

1

40414243

44

D2
D1
D0
IOW*
VDD
VSS
IOR *
UARTCS*
SMPTECS*
A1
A0

Y

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LTCOUT

LFC
XTAL2
XTAL1

AVDD

AVSS

COUT

YOUT

C2
Y2
C1

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44 43 42 41 40 39 3435363738

D2
D1
D0
IOW*
VDD
VSS
IOR *
UARTCS*
SMPTECS*
A1
A0

Y

1

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LFC
XTAL2
XTAL1

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ICS2008B

ICS2008B Rev B 6/6/01

Pin Descriptions

TYPE:

A – Analog • P – Power • I – Input • O – Output 2008 2008B ICS2008

PIN NUMBER

PIN

NAME

TYPE DES CRIPTI ON

TQFP PLCC

12, 10 18, 16 Y1 , Y2 AI

Video i nputs fr om camera or othe r source. NOTE: This is also the Y
(Luma) input fo r S-VHS and HI-8 systems.

11, 9 17, 15 C 1 , C2 AI

C (Chroma) inputs f or S-VHS and HI-8 sys tems. In NTSC systems, t his
pin should be t ied to it s respect ive Y input.

15 21 DTHR ESH AI Data Threshold bypa ss input.
13 19 STHR ESH AI SYNC Threshold bypass input.
14 20 C THRE SH A I Clamp Threshold by pass i nput.

8 14 Y OUT AO Video out put. This is also t he Y (Luma) output i n S-Video mode.
7 13 C OUT AO C (Chroma) output for S-VHS and HI-8 systems.

41 3 FRA ME

AI

Color Frame A/B input. This input is self biased (See Applications).
42 4 CLI CK AI LTC SYNC input. This input is self biased (Se e Applicati ons).
44 6 LTCIN+ AI SMPTE LTC input+. This input is se lf biase d (See Applica tions) .
43 5 LTCI N AI SMPTE LTC input . This input i s self bi ased (Se e Applicat ions).

1 7 LTCOUT AO SMPTE LTC output
20 26 LRCLK O SMPTE LTC receive cl oc k out put .
22 28 VI TCOUT O SMPTE VITC output to video mixer circui t.

21 27 VIT CGATE O VITC gate ind icates VITC code i s being out put for vi deo overlay.
18

24 TxD O UART Transmit data
16 22 Rx D I UART Rec eive da ta
17 23 CTS * I Clear to Sen d
19 25 RTS* O Ready to Send

4 10 XTAL1 I 14.318 MHz crystal i nput.
3 9 XTAL2 O 14.318 MHz crystal oscill ator out put.
2 8 LFC AI Tie to +5 VDC

24, 23 30, 29 A1 - A 0 I Addr ess bus

27 33 I OR * I Read En abl e (a cti ve low)
30 36 I OW* I Wri te En abl e (a ct ive low)
25 31 SMPTECS* I SMPTE port chip select (active low)
26 32 UARTCS* I UART chip select (active low)
40 2 RESET I Master reset (active high)

38 31 44 37 D7- D0 I/O Bi-di recti onal dat a bus

39 1 INTR O Interrupt Reque st (act ive high)

5 11 AV DD P Analog V

DD

6 12 AVSS P Analog Ground

29 35 VDD P Digital V

DD

28 34 V SS P Dig ita l

ICS2008B

4

ICS2008B Rev B 6/6/01

Functional Description

The following is a functional description of the hardware regis­ters in the ICS2008B chip. It also describes how those
registers can be utilized by the software to facilitate specific
application services.

Hardware En vir onments

The ICS2008B operates as a peripheral to a processor such as
a PC or a single chip microprocessor. Many of the real time
requirements are satisfied by double buffering both incoming
and outgoing time codes.

LTC Input

LTCIN is a differential analog input feeding a comparator
with hysteresis. It requires capacitive coupling to the LTC
source. The output of the comparator goes to the LTC re­ceiver, which is capable of receiving LTC in a forward or
backward direction at a rate from 1/30

th

to 80X nominal

frame rates. The incoming LTC data is sampled with a phase­locked clock and loaded into the receive buffer following the
receipt of a valid LTC SYNC pattern. When a complete frame
has been received, an interrupt is generated.

LTC Output

The LTC output can be analog or digital. When set up as an
analog output, it can drive a high impedance load.

The LTC generator outputs a L TC frame at the selected frame
rate, such as 24 Hz, 25 Hz, 29.97 Hz or 30 Hz, and starts the
frame based on a start time generated by the selected LTC
SYNC source.

The output edge rate is programmable for SMPTE code
(25µsec) and EBU code (50µsec) rise and fall times.

Video Inputs

There are two sets of video inputs. In a composite NTSC or
P AL system, the Y input is the only one used. It is capacitively
coupled to the source. In S- Video systems, capacitively couple
Y and C to their respective sources. Proper termination of the
source should be observed. One of the two video sources is
selected by the VIDSEL bit in the SMPTE control registers as
the video SYNC source. Internal timers are synchronized with
the incoming video to extract timing information used to re­ceive and generate VITC.

The VITC receiver samples the incoming video looking for a
valid VITC code on selected scan lines. When a valid code is
received it is written to a VITC receive buffer . More than one

line can contain VITC code, and the codes can be different. For
this reason, VITC codes from selected lines of a frame are writ­ten to separate VITC buffers.

Video Output

The video output combines the selected video input with the
outputs from the VITC generator and the character generator.
It can be a composite or an S-Video output as selected by the
SVID bit in the SMPTE control registers.

VITC code is generated from data in the VITC generator
buffer and output during the selected line time(s). The CRC
and synchronizing bits are automatically generated by the
VITC generator, but all of the data fields are sent directly from
the buffer with no modification.

A character generator is provided to insert the time code in a
burn-in window which overlays the incoming video. The ver­tical and horizontal position of the burn-in window is
programmable.

SMPTE SYNC Sources

A time code generator must have a SYNC input from a stable
source in order to position the LTC code properly on a audio
track of video tape or film. Three SYNC sources, video, click
input, and free running, are available. In the case of a video
tape, LTC code must start within plus or minus one line of the
beginning of line 5. This requires “Genlocking” to the incom­ing video. The video timing section locks to the video’s
horizontal and vertical SYNC signal and generates a SMPTE
SYNC. If some external SYNC source is available it can be
input on the CLICK input. Otherwise, a free running SMPTE
SYNC is generated from the oscillator at the selected frame
rate.

Video Timing Generator

The video timing generator is “Genlocked” to the video
input’s SYNC separator. It extracts NTSC or PAL timing in­formation from the video input and generates line and pixel
rate timing for the VITC receiver, VITC generator, LTC gen­erator and character generator. If no video input is present, it
generates free running timing.

Overlay Character Generator

It is sometimes desirable to display the time code on a video
display along with the picture. A character generator is pro­vided for that purpose. The time code display, or burn-in
window, can be positioned anywhere on the screen. It can be
displayed in two sizes with white or black characters on a
black, white or live video background.

5

ICS2008B

ICS2008B Rev B 6/6/01

UART

A general purpose UART is provided for MIDI, video trans­port control, etc. Most serial interface transport controls use
9600 and 38.4K BAUD. The CTS and RTS modem controls are
needed in these applications. MIDI ports use 31.25K BAUD,
but they do not require modem controls. The receiver includes
a four byte FIFO to reduce the real time interrupt servicing re­quirements. This is particularly important in MIDI applications
because of the high data rate and the fact that many MIDI mes­sages are three bytes long. The transmitter is doubled
buffered. Interrupts can be generated on both
receiver data available and/or transmit buffer empty .

Interrupt Timer

The interrupt timer is a general purpose 10 bit timer with three
clock sources (100 kHz, the LTC receive clock and the LTC
transmit clock). Although the timer is general purpose in
nature, its main purpose is to facilitate the timed generation of
MIDI time code messages.

Processor Interface

The ICS2008B supports standard microprocessor interfaces
and busses, such as the PC bus, to allow access to six control/
status and data registers. These six registers are organized into
two groups, one set of four for SMPTE control and the other
set of two for direct UART port control. Each set of registers is
selected with its own chip select, SMPTECS* and UARTCS.*

SMPTE Registers

The SMPTE register set allows access to four direct and
64 indirect registers. The first two direct access registers
addressed at locations 0 and 1 are for status and interrupt con­trol. The 64 indirect registers are accessed by writing an
indirect address into SMPTE2 and reading from or writing to
SMPTE3. If the AUTOINC bit in SMPTE2 is set to 1, the
indirect register address is automatically incremented after an
access to SMPTE3. This eases the task of reading or writing
sequential indirect locations.

The SMPTE0 Register contains the SMPTE interrupt controls
and status and the VITC read status. The four interrupt bits,

LRI, LXI, VLI and TMI reflect the status of the potential
interrupt sources to the processor. When a bit is set to one and
the corresponding enable bit, LRIEN, LXIEN or VLIEN, is also
set, the INTR output will be activated. Interrupts are cleared by
reading SMPTE0.

LRI — This bit indicates that a LTC receive interrupt has
occurred. In order for an actual processor interrupt to occur,
the LRIEN bit must also be set. An LRI interrupt occurs upon
reception of the last byte of LTC receive data which was pre-

ceded by a valid LTC SYNC pattern. That is after the 64

th

LTC receive bit time in the forward direction. At normal
frame rates, if the LTC transmitter is synchronized with the
L TC receiver, there is about 3 milliseconds after this interrupt
before the LTC transmit data for the next output frame is
transferred to the output buffer.

LXI — This bit indicates that a LTC transmit interrupt has
occurred. When this bit is set, and the corresponding LXIEN
bit has been set, the INTR output will be activated. The LTC
transmit interrupt is activated after the transfer of LTC trans­mit data to the output buffer . This occurs after L TXEN is set to

one and after the 72nd LTC transmits bit time of the current
frame, “N.” Data loaded after this interrupt will appear in out­put frame “N+2” since the transmitter is double buffered.

VLI — This is a status bit that indicates that the video line
selected via the Video Interrupt Line Register, VR9, has
passed. When the VLIEN bit is also set, the processor will be
interrupted. This interrupt can be used by the processor to
determine when to sample the VITC time code when time
locked to a video source. It will also be used to facilitate
detection of LTC time code dropout and off speed LTC code,
e.g. shuttling operations.

TMI — This bit indicates that a timer interrupt has occurred.
When the TMIEN bit is also set to a one, the INTR output will
be activated. This interrupt is intended to facilitate timing
MIDI clocks and MIDI Quarter Frame messages.

Interrupt Control/Status

LRI (LTC RCV Interrupt)
LXI (LTC XMT Interrupt)
VLI (Video Line Interrupt)
LRIEN (1-enable, 0-disable)
LXIEN (1-enable, 0-disable)
VLIEN (1-enable, 0-disable)
TMI (Timer Interrupt)
TMIEN (1-enable, 0-disable)

7 6 5 4 3 2 1 0

SMPTE0

*SCETPMS1A0ARETSIGER

000 sutatS/lortnoCtpurretnI0ETPMS
001 sutatSETPMS1ETPMS
010 sserddAretsigeRtceridnI2ETPMS
011 ataDretsigeRtceridnI3ETPMS

ICS2008B

6

ICS2008B Rev B 6/6/01

The SMPTE Status Register is a read only register which
contains video and LTC status.

FRAMEIN — This bit indicates the state of the FRAME
input pin. It is used as an alternate source for B/A frame
status. This is useful when the quality of the video signal is
not good enough to extract the B/A frame status.

CLICK — This bit indicates the state of the CLICK input
pin. It can be used as a synchronization source for the LTC
transmitter.

LTCLOCK — When a valid forward or backward LTC sync
pattern is detected, this bit is set to one. It is reset to zero when
an expected LTC sync pattern is missed or an invalid LTC bit
is detected.

CODEDIR — The code direction bit works in conjunction
with the L TCLOCK bit. When the L TCLOCK bit is set to one,
the CODEDIR bit is valid. Otherwise, it is not. See the table
below.

VLOCK — This is a hardware driven bit which indicates that
genlock has been achieved with the selected video SYNC
source.

FRAME & FIELD — The hardware SYNC separator detects
the field and frame from the selected video input. The even/
odd fields are identified by a 1/0 in bit 6. Bit 7, FRAME, is
valid for PAL video after line 6. Bit 6, FIELD, is valid after
line 5 in NTSC mode or line 2 in PAL mode.

The SMPTE2 register is the register which points to the 57
indirect registers. When reading or writing an indirect
register, the value in the ADDRESS pointer, SMPTE2 bits 5
to 0, is the address of the register accessed through SMPTE3.
If the AUTOINC bit is set to one, at the end of an access cycle
to SMPTE3, ADDRESS will automatically increment.
Otherwise, ADDRESS holds its value.

SMPTE3 is the data register through which all of the indirect
registers are accessed. The address for a given register must
first be set in SMPTE2 before accessing that register.

Indirect Registers

The following describes the functions controlled by the
indirect registers. A map of the indirect registers follows this
section, on page 11.

LTC Read Registers IR0-IR7 (read-only)

These read only registers contain the LTC data as received.
Both forward and backward frames are stored with LTC bit 0
in the LSB of IR0 and LTC bit 63 in the MSB of IR7.

LTC Write Registers IR8-IRF

These registers contain the data to be sent by the LTC trans­mitter. The LSB of IR8 is sent as LTC bit 0, and the MSB of
IRF is sent as L TC bit 63. The data is transmitted as it is stored
in IR8-IRF.

LTCLOCK CODEDIR LTC RECEIVER STATUS

0 X Looking for SYNC pattern
1 0 Receiving LTC (FORWARD)
1 1 Receiving LTC (BACKWARD)

SMPTE Status Register

FRAMEIN (input = 1-high, 0-low)
CLICK (input = 1-high, 0-low)
LTCLOCK (1-locked, 0-not locked)
CODEDIR (1-bkwd, 0-fwd)
Reserved
VLOCK (1-locked, 0-not locked)
FIELD
FRAME (PAL only)

7 6 5 4 3 2 1 0

SMPTE1

Indirect Address Register

ADDRESS
Reserved
AUTOINC (1-increment, 0-hold)

SMPTE2

7 6 5 4 3 2 1 0

Indirect Address Register

SMPTE3

7 6 5 4 3 2 1 0

7

ICS2008B

ICS2008B Rev B 6/6/01

VITC Read 1 Registers IR10-IR17 (read-only)

These read only registers contain the VITC data as received
from the video line selected in IR30. The frame is stored with
VITC bit 2 in the LSB of IR10 and VITC bit 80 in the MSB of
IR17. Note that a binary 10 sync pattern precedes every eight
data bits of the VITC frame. The 10 sync pattern is not stored.
The CRC is checked by the VITC receiver, and the result is
reported in IR30.

VITC Read 2 Registers IR18-IR1F (read-only)

As with the VITC Read 1 registers, these read only registers
contain the VITC data as received from the video line selected
in IR31. The frame is stored with VITC bit 2 in the LSB of
IR18 and VITC bit 80 in the MSB of IR1F. The result of the
CRC check is reported in IR31.

VITC Write Registers IR20-IR27

These registers contain the data to be output by the VITC
generator. The VITC frame is output with the LSB of IR20 in
VITC bit 2 and the MSB of IR27 in VITC bit 80. Note that the
binary 10 sync pattern which precedes every eight data bits of
the VITC frame is automatically generated by the VITC
generator. The CRC is also automatically generated by the
VITC generator.

BI Window Registers IR28 & 29

The next two registers control the position of the SMPTE
video display, burn-in, window within the video raster. IR28
selects the video column (horizontal position) in which the
burn-in window starts.

IR29 selects the video line which starts the SMPTE video
display window in the video output. When this register is set
to zero, there will be no Burn-In Window displayed in the
video output.

BI Character Registers IR2A-IR2D

These registers contain the character codes used for the
SMPTE time code in the burn-in window which overlays the
source in the video output. An internal character generator
converts the BCD nibbles to display characters.

ITC Write Line Select Registers IR2E & IR2F

VITC code is normally output on two separate video lines in
each field for redundancy. These two registers allow the indi­vidual line selection & output enables for the two VITC lines.

Write Line – Selects the video line on which the VITC code
will be output. The video line on which the code is output will
be the number in this register plus 10; e.g. writing a one to this
register will cause the code to be output on line 11.

VITC Write Enable – Enables the output of VITC code on the
specified line.

Burn-in Window Column

Column

IR28

Burn-in Window Line

Line (00 - disable)

IR29

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

VITC Write Line 1

Write Line #10-40 (N+10)
Reserved
VITC Write Enable (1-enable)

IR2E

7 6 5 4 3 2 1 0

VITC Write Line 2

Write Line #10-40 (N+10)
Reserved
VITC Write Enable (1-enable)

IR2F

Burn-in Window Registers

IR2A – (Frame)
IR2B – (Seconds)
IR2C – (Minutes)
IR2D – (Hours)

7 6 5 4 3 2 1 0

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