ICST AV1890 Datasheet
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS1890
10Base-T/100Base-TX Integrated PHYceiver
ICS1890RevG 10/21/97
Block Diagram
One chip integrated physical layer
All CMOS, Low power design (<200mA max)
Small footprint 64-pin 14mm 2 QFP package
ISO/IEC 8802-3 CSMA/CD compliant
Media Independent Interface (MII)
Alternate 100M stream and 10M 7-wire serial
interfaces provided
10Base-TX Half & Full Duplex
100Base-TX Half & Full Duplex
Fully integrated TP-PMD including Stream
Cipher Scrambler, MLT-3 encoder, Adaptive
Equalization, and Baseline Wander Correction
Circuitry
PHYceiver and QuickPoll are trademarks of Integrated
Circuit Systems, Inc. Patents pending.
The ICS1890 is a fully integrated physical layer device
supporting 10 and 100Mb/s CSMA/CD Ethernet applications.
DTE (adapter cards or motherboards), switching hub, repeater
and router applications are fully supported. The ICS1890
is compliant with the ISO/IEC 8802-3 Ethernet standard
for 10 and 100Mb/s operation. A Media Independent Interface
allowing direct chip-to-chip connection, motherboard-todaughterboard connection or connection via an AUI-like
cable is provided. A station management interface is
provided to enable command information and status
information exchange. The ICS1890 interfaces directly to
transmit and receive isolation transformers and can support
shielded twisted pair (STP) and unshielded twisted pair
(UTP) category 5 cables up to 105 meters. Operation in half
duplex or full duplex modes at either 10 or 100 Mbps
speeds is possible with control by Auto-Negotiation or
manual selection. By employing Auto-Negotiation the
technology capabilities of the remote link partner may be
determined and operation automatically adjusted to the
highest performance common operating mode.
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
2
ICS1890
Introduction
The ICS1890 is essentially a nibble/bit stream processor.
When transmitting, it takes sequential nibbles presented at
the Media Independent Interface (MII) and translates them to
a serial bit stream for transmission on the media. When receiving,
it takes the serial bit stream from the media and translates it to
sequential nibbles for presentation to the MII. It has no
knowledge of the underlying structure of the MAC frame it is
conveying.
100Base-TX Operation
When transmitting, the ICS1890 encapsulates the MAC
frame (including the preamble) with the start-of-stream and
end-of-stream delimiters. When receiving, it strips off the
SSD and substitutes the normal preamble pattern and then
presents this and subsequent preamble nibbles to the MII.
When it encounters the ESD, it ends the presentation of
nibbles to the MII. Thus, the MAC reconciliation layer sees
an exact copy of the transmitted frame.
During periods when no frames are being transmitted or
received, the device signals and detects the idle condition.
This allows the higher levels to determine the integrity of the
connection. In the 100Base-TX mode, a continuous stream of
scrambled ones is transmitted signifying the idle condition.
The receive channel includes logic that monitors the IDLE
data stream to look for this pattern and thereby establishes
the link integrity.
The 100M Stream Interface option allows access to raw groups
of 5-bit data with lower latency through the PHY. This is useful
in building repeaters where latency is critical.
10Base-T Operation
In 10Base-T mode, the bit stream on the cable is identical to
the de-composed MAC frame. Link pulses are used to establish
the channel integrity. When receiving, the ICS1890 first
synchronizes to the preamble. Once lock is detected, it begins
to present preamble nibbles to the MII. On detection of the
SFD, it frames the subsequent 4-bits which are the first data
nibble.
Configuration
The ICS1890 is designed to be fully configurable using
either hardware pins or the (usually) software-driven MII
Management interface, as selected with the HW/SW pin. A
rich set of configuration options are provided. This allows
diverse system implementations and costs.
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ICS1890
Modes of Operation
Reset & Basic Initialization
Reset can be accomplished using either register bit 0:15 or the
RESET pin.
For a hardware reset, RESET must be held at a logic zero level
for at least two clock cycles and may be held low as long as
desired.
While RESET is held low the device is in Low Power mode.
After the RESET pin is released to a logic one level, Low
Power mode is exited, the PHY address is latched into register
16, and the reset process continues to completion.
For a software reset, a management agent must write a logic
one to register bit 0:15. This will start the reset process. The
software reset bit will clear itself automatically when reset is
completed.
All reset timing parameters are specified in the Electricals
section of the data sheet.
Low Power and Automatic 100Base-T PowerDown
The ICS1890 supports two power saving modes. The ICS1890
device can be placed into a state where very littler power is
drawn by the device. This Low Power mode can be activated
by holding the RESET pin continuously low or by writing a
logic one to the Power-down bit (0:11).
When the device is in Low Power mode, all functions are
disabled except for register access through the MII Management
Interface.
All register values are maintained during Low Power mode,
except for latching status bits, which are reset to their default
values.
The ICS1890 can also automatically reduce its total power
requirements when operating in 10Base-T mode by automatically
powering-down the 100Base-TX modules.
The power required by the ICS1890 in normal, 100Base-TX
power-down, and Low Power modes is given in the Electricals
section of the data sheet.
Auto-Negotiation
A link can automatically be established using Auto-Negotiation.
When enabled, Auto-Negotiation will exchange information
about the local nodes capabilities with its remote link partner.
After the information is exchanged, each device compares its
capabilities with those of its partner and then the highest
performance operational mode is automatically selected.
As an example, if one device supports 10Base-T and 100BaseTX, and the other device supports 100Base-TX and 100BaseT4, 100Base-TX will automatically be selected.
See the Auto-Negotiation section for more details on how the
process is initiated and controlled.
100Base-TX
The primary operational mode of the ICS1890 is to provide
100Base-TX physical layer services. This consists mainly of
converting data from parallel to serial at a 100 Mb/s data rate.
The device may be configured in a number of different ways
and also provides detailed operational status information.
10Base-T
The ICS1890 also provides 10Base-T physical layer services
to allow easy migration from 10 to 100 Mb/s service. Complete
data service is provided with configuration and status available
to management.
Full Duplex
The ICS1890 supports either half and full duplex operation
for both 10Base-T and 100Base-TX. Full Duplex operation
allows simultaneous transmission and reception of data which
can effectively double data throughput to 20 or 200 Mb/s.
To operate in Full Duplex mode, some of the standard 10BaseT and 100Base-TX behaviors are modified.
In 10Base-T Full Duplex mode, transmitted data is not looped
back to the receiver and SQE test is not performed.
In both 10Base-T and 100Base-TX Full Duplex modes, CRS is
asserted in response only to receive activity and COL always
remains inactive.
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ICS1890
Interface Overviews
Overview of MAC/Repeater to PHY Interfaces
To accommodate different applications, the ICS1890 provides
four types of MAC/Repeater to PHY interfaces. The four
interfaces are - 10/100 MII Data Interface, 100M Stream Interface, 10M Serial Interface and the Link Pulse Interface.
The standard and most commonly used interface is the 10/100
MII Data Interface which provides framed 4-bit nibbles and
control signals.
The 100M Stream Interface provides 5-bits of unframed data
as well as the normal CRS signal which can be used as a fast
look-ahead. This interface is intended for 100Base-TX repeater
applications that require nothing more than recovered parallel
data where all framing is handled in the repeater core logic.
The 10M Serial Interface provides a framed single data bit
interface with control signals and is ideally suited to applications
that already incorporate a serial 10Base-T MAC with a standard
7-wire interface.
The Link Pulse Interface is provided for applications that wish
to fully control the Auto-Negotiation process themselves but
not the actual generation and reception of Link Pulses.
MII Data Interface
The ICS1890 implements a fully compliant IEEE 802.3u
Media Independent Interface for connection to MACs or
repeaters allowing connection between the ICS1890 and
MAC on the same board, motherboard/daughter board or via
a cable in a similar manner to AUI connections.
The MII is a specification of signals and protocols which
formalizes the interfacing of a 10/100 Mbps Ethernet Media
Access Controller (MAC) to the underlying physical layer.
The specification is such that different physical media may be
supported (such as 100Base-TX, 100Base-T4 and 100BaseFX) transparently to the MAC.
The MII Data Interface specifies transmit and receive data
paths. Each path is 4-bits wide allowing for transmission of a
data nibble. The transmit data path includes a transmit clock
for synchronous transfer, a transmit enable signal and a transmit
error signal. The receive data path includes a receive data
clock for synchronous transfer, a receive data valid signal and
a receive error signal. Both the transmit clock and receive
clock are sourced by the ICS1890.
The ICS1890 provides the MII signals carrier sense and
collision detect. In half duplex mode, carrier sense indicates
that data is being transmitted or received, and in full duplex
mode it indicates that data is being received. Collision detect
indicates that data has been received while a transmission is
in progress.
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ICS1890
The ICS1890 is designed to allow hot insertion of an MII
cable into a MAC MII port. During the power-up phase, the
ICS1890 will isolate the MII and the Twisted Pair Transmit
signal pair
100M Stream Interface
The 100M Stream Interface is an alternative parallel interface
between the PHY and MAC/Repeater than the standard MII
Data interface. The Stream Interface provides a lower level
interface and, therefore, lower bit delay than the standard MII
Data Interface.
This interface is selected by setting the MII/SI pin to STREAM
INTERFACE mode and by setting the 10/100SEL pin to 100
mode.
The Stream Interface bypasses the Physical Coding Sublayer
(PCS) and provides a direct unscrambled, unframed 5-bit
interface to the Physical Media Access (PMA) layer.
The Stream Interface consists of a 14 signal interface: STCLK,
STD[4:0], SRCLK, SRD[4:0], SCRS, SD.
Data is exchanged between the MAC and PHY using 5-bit
unframed code groups at 25 MHz clock rate.
The Stream Interface provides a CRS signal by continuing to
use the logic that is bypassed by this interface. This gives a
carrier indication faster than is possible from the MAC/Repeater
since the bits are examined serially as soon as they enter the
PHY.
Since only the Stream Interface or the MII Interface is active
at once, it is possible to share the MII Data interface pins for
Stream Interface functionality.
The pins have the following mapping:
MII Stream
TXCLK STCLK
TXEN (1)
TXER STD4
TXD3 STD3
TXD2 STD2
TXD1 STD1
TXD0 STD0
RXCLK SRCLK
RXDV (2)
RXER SRD4
RXD3 SRD3
RXD2 SRD2
RXD1 SRD1
RXD0 SRD0
CRS SCRS
COL (3)
LSTA SD
(1) 100Base-TX is a continuous transmission system and the
MAC/Repeater is responsible for sourcing IDLE symbols
when it is not transmitting data when using the Stream Interface.
(2) Since data is not framed when this interface is used, RXDV
has no meaning.
(3) Since the MAC/Repeater is responsible for sourcing both
active and idle data, the PHY can not tell when it is transmitting
in the traditional sense, so no collisions can be detected.
Other mode configuration pins behave identically regardless
of which data interface is used.
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ICS1890
10M Serial Interface
The 10M Serial Interface is an alternative serial interface
between the PHY and MAC/Repeater than the standard MII
Data interface. The 10M Serial interface provides the same
functionality, but with a serial data stream at a 10 MHz clock
rate.
This interface is selected by setting the MII/SI pin to STREAM
INTERFACE mode and by setting the 10/100SEL pin to 10
mode.
The 10M Serial Interface operation consists of a nine signal
interface: 10TCLK, 10TXEN, 10TD 10RCLK, 10RXDV, 10RD,
10CRS, 10COL, and LSTA.
Data is exchanged between the MAC and PHY serially at a 10
MHz clock rate.
Since only the 10M Serial Interface or the MII Interface is
active at once, it is possible to share the MII Data interface
pins for 10M Serial Interface functionality.
The pins have the following mapping:
MII 10M Serial
TXCLK 10TCLK
TXEN 10TXEN
TXER (1)
TXD3
TXD2
TXD1
TXD0 10TD
RXCLK 10RCLK
RXDV 10RXDV
RXER (1)
RXD3
RXD2
RXD1
RXD0 10RD
CRS 10CRS
COL 10COL
LSTA LSTA
(1) Error generation and detection is not supported by
10Base-T.
Other mode configuration pins behave identically regardless
of which data interface is used.
Link Pulse Interface
The Link Pulse Interface is an alternative control interface
between the PHY and MAC/Repeater than the standard MII
Data interface. The Link Pulse provides detailed control over
the Auto-Negotiation process.
This interface is selected by setting the MII/SI pin to STREAM
INTERFACE mode, by setting the 10/100SEL pin to 10
mode, and by setting the 10/LP pin to LP mode.
The Link Pulse Interface consists of a five signal interface:
LTCLK, LPTX, LRCLK, LPRX, SD.
Since only the Link Pulse Interface or the MII Interface is
active at once, it is possible to share the MII Data interface
pins for Link Pulse Interface functionality.
The pins have the following mapping:
MII Link Pulse
TXCLK LTCLK
TXEN
TXER LPTX
TXD3
TXD2
TXD1
TXD0
RXCLK LRCLK
RXDV
RXER LPRX
RXD3
RXD2
RXD1
RXD0
CRS
COL
LSTA SD
Other mode configuration pins behave identically
regardless of which data interface is used.
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ICS1890
MII Management Interface
The MII also specifies a two-wire management interface and a
protocol between station management and the physical layer.
The ICS1890 implements this interface, providing a
bidirectional data line and a clock input for synchronizing the
data transfers. This interface allows station management to
read from and write to all of the devices registers.
Twisted Pair Interface
The ICS1890 is able to operate in either 10Base-T or 100Base-
TX modes using a shared interface to a universal magnetics
module and single RJ-45 connector jack.
The interface signals consist of a differential pair of transmit
signals and a differential pair of receive signals. The interface
also provides pins for setting the 10 & 100M transmit current.
Clock Reference Interface
The ICS1890 synthesizes all its required clock signals from
a single 25MHz frequency reference supplied to the Clock
Reference Interface (REF_IN & REF_OUT).
Any reference must meet the stringent IEEE standard
requirements for total accuracy under all conditions of ±50
parts per million (ppm), even though the device can easily
function with a less accurate reference.
Three reference configurations are supported.
A simple CMOS level signal may be fed into the REF_IN
input, leaving the REF-output unconnected.
A crystal oscillator module may be used to provide the
frequency reference for the REF_IN input instead of simple
reference.
It is possible to use a high precision crystal between the
REF_IN and REF_OUT pins on the ICS1890 to provide the
25MHz time base for part operation. In addition to the
connection of the crystal between these pins, a capacitor
from REF_IN and REF_OUT to ground is necessary to
neutralize the capacitance of the crystal. Since these capacitors
are nominally in series, the values of each of these components
(plus stray board capacitance) will equal twice the rated
capacitance of the crystal (series combination).
It is imperative that the crystal be cut for accuracy and
temperature coeffieients with the equivalent capacitive loading
of the specific board layout and the chosen neutralizing
capacitors. The overall accuracy for ethernet applications
must be ±50ppm total for accuracy, temperature, and aging.
Therefore the crystal must be cut using a fixture with the
equivalent capacitive loading as in the end application. This
custom cutting of the crystal will be at additional cost, but
in high volume applications this may be cost effective compared
to pretuned crystal oscillator modules. For more information,
contact ICS Datacom Applications.
Configuration and Status Interface
This interface provides a full set of pins to allow the device
to be completely configured by hardware.
The interface also provides dynamic tristate control over
both the Twisted Pair Transmit interface and the MII Receive
interface.
Link Status and Stream Cipher Locking status signals are
provided for use by a MAC or custom logic.
PHY Address & LED Interface
The ICS1890 device uses a unique scheme to multiplex the
PHY Address and the LED outputs onto the same set of five
pins.
Simply connecting the LED from the device pin to either
power or ground sets the address bit to a 1 or 0. The device
then uses the address info to drive the LED correctly
independent of its connection. The Pin Description section
provides detailed connection instructions.
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ICS1890
Functional Blocks
Media Independent Interface (MII) Overview
The MII consists of a data interface, basic register set, and a
serial management interface to the register set.
The data interface is a nibble wide transmit and receive data
interface between the MAC and PHY devices. The interface
supports data transfers at 25 MHz for 100Base-T and 2.5 MHz
for 10Base-T.
The register set consists of basic and extended standard
registers as well as vendor specific registers. There are two
basic registers, a control register to handle basic device
configuration, and a status register to report basic device
abilities and status. The standard extended registers provide
access to an Organizationally Unique Identifier and AutoNegotiation functionality.
The ICS1890 also provides vendor specific registers that
enhance the device operation. Among these is the QuickPoll
Detailed Status register which provides a comprehensive set
of real-time device information with only single register access.
Auto-Negotiation
The auto-negotiation logic of the ICS1890 has three main
purposes. Firstly, to determine the capabilities of the remote
partner (device at the other end of the cable). Secondly, to
advertise its own capabilities to the remote partner. And thirdly,
to establish a connection with the remote partner using the
highest performance common connection technology.
The ICS1890 auto-negotiation logic is designed to operate
with legacy 10Base-T networks or newer systems with multiple
connection technology options. When operating with a legacy
10Base-T remote partner, the ICS1890 will select the 10Base-
T operating mode transparently to the remote partner thus
allowing the preservation of existing legacy network structures
without management intervention.
Auto-negotiation is accomplished using a physical signaling
scheme that is transparent at the packet and higher level
protocols. This scheme builds upon the 10Base-T link test
pulse sequence by using a burst of pulses to signal
configuration information between the two devices.
The Fast Link Pulse Bursts are simultaneously exchanged by
both nodes on a link segment the local node encodes the data
from the Auto-negotiation Advertisement Register (register
4) into the FLP Bursts it transmits. The data received from the
link partners FLP Bursts is placed into the Auto-Negotiation
Link Partner Ability Register (register 5). When Auto-Negotiation
is complete (1:5=1 or 17:4=1), the highest priority technology
from the following table that is common in the two registers is
automatically selected as the operating mode.
Priority Resolution Table
Highest Priority Listed first.
1) 100Base-TX Full Duplex
2) 100Base-T4
3) 100Base-TX
4) 10Base-T Full Duplex
5) 10Base-T
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