ICST AV1889Y Datasheet

Integrated
Circuit
Systems, Inc.

General Description Features

ICS1889

Block Diagram

PHYceiver and QuickPoll are trademarks of Integrated Circuit Systems, Inc.

100Base-FX Integrated PHYceiver

TM

ICS1889RevF092497P

 One chip integrated physical layer
 All CMOS, low power design
 ISO/IEC 8802-3 CSMA/CD compliant
 100Base-FX Half & Full Duplex
 Far end fault detection
 Media Independent Interface (MII)
 Station management interface
 Extended register set including QuickPollTM detailed

status monitoring
 Transmit clock synthesis
 Receive clock and data recovery
 Detailed receive error reporting
 Extended Test Modes
 52-pin MQFP package with 2.0 mil body thickness

The ICS1889 is a fully integrated physical layer device
supporting 100 Megabits per second CSMA/CD Fast
Ethernet fiber optic applications. It is designed to support
the requirements of DTEs (adapter cards), repeaters and
switches. It is compliant with the ISO/IEC 8802 Fast
Ethernet standard for 100Base-FX. It provides a Media
Independent Interface (MII) allowing direct chip-to-chip
connection, motherboard-to-daughter board connection or
connection via a cable in a similar manner to the AUI
approach used with 10Base-Tsystems. A station
management interface is provided to receive command
information and send status information. It transmits and
receives NRZI data and interfaces directly to the optical
transceiver. It can operate in either half duplex or full
duplex.

2

ICS1889

Block Diagram

Introduction

The ICS1889 is a nibble to bit stream and bit stream to nibble
processor. When transmitting, it takes sequential nibbles
presented at the Media Independent Interface (MII) and
translates them to a serial bit stream for transmission on the
media. When receiving, it takes the serial bit stream from the
media and translates it to sequential nibbles for presentation
to the MII. It has no knowledge of the underlying structure of
the MAC frame it is conveying.

When transmitting, the ICS1889 encapsulates the MAC
frame (including the preamble) with the start-of-stream
(SSD) and end-of-stream (ESD) delimiters. When receiving,
it strips off the SSD and substitutes the normal preamble
pattern and then presents this and subsequent preamble
nibbles to the MII. When it encounters the ESD it ends the
presentation of nibbles to the MII. Thus, the MAC
reconciliation layer sees an exact copy of the transmitted
frame.

During periods when no frames are being transmitted or
received, there is a requirement to signal and detect the idle
condition. This allows the higher levels to determine the
integrity of the connection between the node and the hub. A
continuous stream of ones is transmitted to signify the idle
condition, the receive channel includes logic that monitors
the IDLE data stream to look for this pattern and thereby
establish the link integrity.

Functional Description

3

ICS1889

Media Independent Interface (MII)

The ICS1889 implements a fully compliant IEEE 802.3µ
Media Independent Interface for connection to MACs or
repeaters which allows connections between the ICS1889
and MAC on the same board, motherboard/daughter board or
via a cable in a similar manner to AUI connections.

The MII is a specification of signals and protocols which
formalizes the interfacing of a 10/100 Mbps Ethernet Media
Access Controller (MAC) to the underlying physical layer.
The specification is such that different physical media may be
supported (such as 100Base-TX, 100Base-T4 and 100Base­FX) transparently to the MAC.

The MII specifies transmit and receive data paths. Each path
is 4-bits wide allowing for transmission of a nibble or single
symbol. The transmit data path includes a transmit clock for
synchronous transfer, a transmit enable signal and a transmit
error signal. The receive data path includes a receive data

clock for synchronous transfer, a receive data valid signal and
a receive error signal. Both the transmit clock and receive
clock are sourced by the ICS1889. The ICS1889 provides the
MII signals carrier sense and collision detect. In half duplex
mode, carrier sense indicates that data is being transmitted or
received, and in full duplex mode it indicates that data is
being received. Collision detect indicates that data has been
received while a transmission is in progress.

The MII also specifies a two wire interface and a protocol
between station management and the physical layer. The
ICS1889 implements this interface providing a bidirectional
data line and a clock input for synchronizing the data
transfers. This interface allows station management to read
and write all of the ICS1889 registers.

The ICS1889 is designed to allow hot insertion of an MII
cable into the MAC. During the power-up phase, the
ICS1889 will isolate the MII and the transmit pair by
tristating the PHY outputs.

4

ICS1889

Transmit Clock Synthesizer

The ICS1889 synthesizes the transmit clock using a PLL to
produce 25 MHz and 125 MHz clocks. This allows the use of
a low cost 25 MHz crystal or a low jitter reference frequency
source.

Receive Clock Recovery

The receive clock recovery logic monitors the receive line and
detects a receive signal. The logic, which includes a PLL,
extracts data and clock from the 100Base-FX, 125 Mbps,
NRZI bit stream. In the event that the PLL is unable to lock on
to the receive signal, it generates a not locked signal. The
transmit clock synthesizer provides a center frequency
reference for operation of the clock recovery circuit in the
absence of data. The receive signal detected and not
locked signals are both used by the logic which monitors the
receive channel for errors.

Carrier Detector & Framer

The carrier detector examines the receive serial bit stream
looking for the SSD, the JK symbol pair. In the idle state,
IDLE symbols (all logic ones) will be received. If the carrier
detector detects a logic zero in the bit stream, it examines the
following bits looking for the first two non-contiguous zeroes,
confirms that the first 5-bits form the J symbol (11000) and
asserts carrier detect. At this point the serial data is framed
and the second symbol is checked to confirm the K symbol
(10001). If successful, the following framed data (symbols)
are presented to the 4B5B decoder. If the JK pair is not
confirmed, the false carrier detect bit is asserted in the
QuickPoll Register and the idle state is reentered.

5

ICS1889

4B/5B Encoder/Decoder

The ICS1889 uses a 4B5B coding scheme. This maps a 4-bit
nibble to a 5-bit code group called a symbol. Five bits allow
32 possible symbols, 16 are used for data encoding, 6 are used
for control and 10 are not used and are invalid. The control
symbols used are JK as the SSD, TR as the ESD, I as
the IDLE symbol and H to signal an error. All other
symbols are invalid and, if detected, will set the receive error
bit in the status register, and cause the RXER signal to be
asserted (see Table 1 below).

When transmitting, nibbles from the MII are converted to a 5­bit code groups. During transmission, the first 16 nibbles
obtained from the MII are the MAC frame preamble.

The ICS1889 replaces the first two nibbles with the start-of­stream delimiter (the JK symbol pair). Following the last
nibble, the ICS1889 adds the end-of-stream delimiter (the
TR symbol pair).

When receiving, 5-bit code groups are converted to nibbles
and presented to the MII. If the ICS1889 detects one or more
invalid symbols, it sets the Invalid Symbol bit (17:7) in the
QuickPoll Status Register. When receiving a frame, the first
two 5-bit code groups received are the start-of-stream
delimiter (the JK symbol pair), the ICS1889 strips them
and substitutes two nibbles of the normal preamble pattern.
The last two 5-bit code groups are the end-of-stream delimiter
(the TR symbol pair), these are stripped from the nibbles
presented to the MAC.

1. The IDLE symbol is sent continuously between frames.

2. J and K are the SSD and are always sent in pairs.

3. K always follows J.

4. T and R are the ESD and are always sent in pairs.

5. R always follows T.

6. A HALT symbol is used to signal an error condition.

Table 1: 4B5B Encoding

Symbol Meaning

4B Code

3 2 1 0

5B Code

4 3 2 1 0

Symbol Meaning

4B Code

3 2 1 0

5B Code

4 3 2 1 0
0 Data 0 0 0 0 0 1 1 1 1 0 8 Data 8 1 0 0 0 1 0 0 1 0
1 Data 1 0 0 0 1 0 1 0 0 1 9 Data 9 1 0 0 1 1 0 0 1 1
2 Data 2 0 0 1 0 1 0 1 0 0 A Data A 1 0 1 0 1 0 1 1 0
3 Data 3 0 0 1 1 1 0 1 0 1 B Data B 1 0 1 1 1 0 1 1 1
4 Data 4 0 1 0 0 0 1 0 1 0 C Data C 1 1 0 0 1 1 0 1 0
5 Data 5 0 1 0 1 0 1 0 1 1 D Data D 1 1 0 1 1 1 0 1 1
6 Data 6 0 1 1 0 0 1 1 1 0 E Data E 1 1 1 0 1 1 1 0 0
7 Data 7 0 1 1 1 0 1 1 1 1 F Data F 1 1 1 1 1 1 1 0 1

I Idle Undefined 1 1 1 1 1 V Invalid Undefined 0 0 0 1 0

J SSD 0 1 0 1 1 1 0 0 0 V Invalid Undefined 0 0 0 1 1

K SSD 0 1 0 1 1 0 0 0 1 V Invalid Undefined 0 0 1 0 1
T ESD Undefined 0 1 1 0 1 V Invalid Undefined 0 0 1 1 0
R ESD Undefined 0 0 1 1 1 V Invalid Undefined 0 1 0 0 0
H Error Undefined 0 0 1 0 0 V Invalid Undefined 0 1 1 0 0
V Invalid Undefined 0 0 0 0 0 V Invalid Undefined 1 0 0 0 0
V Invalid Undefined 0 0 0 0 1 V Invalid Undefined 1 1 0 0 1

Invalid Error Code Test TXER asserted

I Idle 1 1 1 1 1 1 1 1 1 V Invalid 0 0 1 0 0 0 0 1 0

J SSD 1 1 1 0 1 1 0 0 0 V Invalid 0 0 1 1 0 0 0 1 1

K SSD 1 0 1 1 1 0 0 0 1 V Invalid 0 1 0 1 0 0 1 0 1
T ESD 1 0 0 1 0 1 1 0 1 V Invalid 0 1 1 0 0 0 1 1 0
R ESD 0 1 1 1 0 0 1 1 1 V Invalid 1 0 0 0 0 1 0 0 0
H Error 0 1 0 0 0 0 1 0 0 V Invalid 1 0 1 0 0 1 1 0 0
V Invalid 0 0 0 0 0 0 0 0 0 V Invalid 1 1 0 0 1 0 0 0 0
V Invalid 0 0 0 1 0 0 0 0 1 V Invalid 1 1 0 1 1 1 0 0 1

6

ICS1889

Line Transmitter

The Line Transmitter output pair is a differential positive ECL
(PECL) interface designed to connect directly to a standard
fiber optic transceiver. The differential driver for the transmit
signal is a programmable current source designed for resistive
termination. Using an external resistor connected to the IPRG
pin, the output current may be preset.

The differential driver for the TX ± is current mode and is
designed to drive resistive terminations in a complementary
fashion. The output is current-sinking only, with the amount
of sink current programmable via the IPRG1 pin. The sink
current is equal to four times the IPRG1 current. For most
applications, an 910Ω resistor from VDD to IPRG1 will set
the current to the necessary precision.

The TX± pins are incapable for sourcing current, so V

OH

must
be set by the ratios of the Thevenin termination resistors for
each of the lines. R1 is a pull-up resistor connected from the
PECL output to VDD. R2 is a pull-down resistor connected
from the PECL output to VSS. R1 and R2 are electrically in
parallel from an AC standpoint. If we pick a target impedance
of 50Ω for our transmission line impedance, a value of 62Ω
for R1 and a value of 300Ω for R2 would yield a Thevenin
equivalent characteristic impedance of 49.7Ω and a V

OH

value of VDD -.88 volts, compatible with PECL circuits.
To set a value for VOL, we must determine a value for I

prg

that will cause the output FETs to sink an appropriate current.
We desire VOL to be V

DD

-1.81 or greater. Setting up a sink
current of 19 milliamperes would guarantee this through our
output termination resistors. As this is controlled by
4/1 current mirror, 4.75mA into I

prg

should set this current

properly. A 910Ω resistor from V

DD

to I

prg

should work fine.

Line Receiver

The Line Receiver is a differential input pair designed to
interface directly to a standard fiber optic transceiver. It is a
differential PECL input buffer.

Signal Error Detector

The ICS1889 Signal Error Detector is part of the clock
recovery PLL. It detects a Receive Signal Error if no receive
signal is received and detects a PLL Lock Error if the PLL is
unable to lock on to the receive channel signal. A receive
channel error is defined as the loss of receive signal or the loss
of PLL lock.

Remote Fault Signaling

Remote fault signaling allows a node to indicate receive
channel errors to its Link Partner using its transmit channel.
When used by both nodes on a link segment, the integrity of
both the transmit and receive channels can be verified.

Since 100Base-FX systems do not use auto-negotiation, an
alternative, in-band signaling scheme is used to signal remote
fault conditions. This scheme, Far End Fault Indication, relies
on the characteristics of the quiescent state, (a continuous
IDLE stream). The IDLE stream is a continuous stream of
logic ones and a carrier is defined as the receipt of two
noncontiguous logic zeroes. A Far End Fault is signaled with
84 logic ones followed by one logic zero, with the pattern
repeated at least three times.

A Far End Fault will be signaled under three conditions; the
first is when no activity is received from the Link Partner,
since this can indicate a broken receive wire. The second is
when the clock recovery circuit detects a Receive Signal Error
or PLL Lock Error. The third is when a management entity
sets the Transmit Far End Fault bit (16:3).

Far End Fault signaling continues until the condition causing
the fault ceases.

Far End Fault Detection

The Far End Fault detector monitors the receive data serial bit
stream looking for a repetitive pattern of 84 logic ones
followed by a logic zero. Non-ICS1889 PHYs may have
different definitions of what constitutes a remote fault.
However, an ICS1889 will always respond to the in-band
error signaling scheme. If the ICS1889 detects three
consecutive patterns described above, it will signal a far end
fault to the Link Monitor.

Link Monitor

If the Link Monitor receives a far end fault indication or a
local receive channel error, it causes the ICS1889 to enter the
IDLE mode, isolate the MII and assert the Link Status bit in
the Status Register. Once the far end fault condition is de­asserted, the Link Monitor will return to the Link OK
condition if the local receive channel is clear of errors. Once
detected, a receive channel error signal will be indicated from
330 to 1000 microseconds.

7

ICS1889

Management Interface

The ICS1889 provides a management interface to connect to
a management entity. The two wire serial interface is part of
the MII and is described in the MII section. The interface
allows the transport of status information from the ICS1889
to the management entity and the transport of command
words to the ICS1889. It includes a register set, a frame
format, and a protocol.

Management Register Set

The register set includes the mandatory basic control and
status registers and an extended set. The ICS1889 implements
the following registers.

Control (register 0)
Status (register 1)
PHY Identifier (register 2)
PHY Identifier (register 3)
Extended Control (register 16)
QuickPoll Status (register 17)

Management Frame Structure

The management interface uses a serial bit stream with a
specified frame structure and protocol as defined below.

Preamble 11...11 (32 ones)
SOF 01
Op Code 10 (read), 01 (write)
Address AAAAA (5 bits)
Register RRRRR (5 bits)
TA NN (2 bits)
Data DD...DD (16 bits)
Idle Zo high impedance

Preamble

The ICS1889 looks for a pattern of 32 logic ones followed by
the SOF delimiter before responding to a transaction.

Start of Frame

Following the preamble a start of frame delimiter of zero-one
initiates a transaction.

Operation Code

The valid codes are 10 for a read operation and 01 for a write
operation. Other codes are ignored.

Address

There may be up to 32 PHYs attached to the MII. This 5 bit
address is compared to the internal address of the ICS1889, as
set by the P[0...4]* pins, for a match.

Register Address

The ICS1889 uses this field to select one of the registers
within the set. If a nonexistent register is specified, the
ICS1889 ignores the command.

TA

This 2-bit field is used by the ICS1889 to avoid contention
during read transactions. When writing to the ICS1889, the
TA bits should be set to 10. When reading from the ICS1889,
the device will tristate during this time.

Data

This is a 16-bit field with bit 15 being the first bit sent or
received.

Idle

The ICS1889 is in the high impedance state during the idle
condition.

Register Access Rules

RO  Read Only, writes ignored
CW  Command Override Writable
RW/0  Read/Write only logic zero
RW  Read/Write

Four types of register access are supported by the device.
Read Only (RO) bits may be read, but writes are ignored.
Command Override Writable (CW) bits may be read, but
writes are ignored unless preceded by writing a logic one to
the Command Register Override bit (16:15). Read Write Zero
(RW/0) bits may be read, but must only be written with a logic
zero value. Writing a logic one to this type of bit may prevent
the device from operating normally. Read Write (RW) bits
may be read and may be written to any value.

Default Values

  No default value
0  Default to logic zero
1  Default to logic one
Pin  Default depends on the state of

the named pin

Modifier

SC  Self Clearing
LL  Latching Low
LH  Latching High

Self clearing bits will clear without any further writes after a
specified amount of time. Latching bits are used to capture an
event. To obtain the current status of a latching bit, the bit
must be read twice in succession. If the special condition still
persists, the bit will be the same on the second read;
otherwise, the condition indication will not be present.

8

ICS1889

Control Register (register 0)

The control register is a 16-bit read/write register used to set
the basic configuration modes of the ICS1889. It is accessed
through the management interface of the MII.

Reset (bit 15) default = 0

Setting this bit to a logic 1 will result in the ICS1889 setting
all its status and control registers to their default values.
During this process the ICS1889 may change internal states
and the states of physical links attached to it. While in process,
the bit will remain set and no other write commands to the
control register will be accepted. The reset process will be
completed within 500 ms and the bit will be cleared indicating
that the reset process is complete.

Loop Back (bit 14)

Setting this bit to a logic one causes the ICS1889 to tristate
the transmit circuitry from sending data and the receive
circuitry from receiving data. The collision detection circuitry
is also disabled unless the collision test command bit is set.
Data presented to the MII transmit data path is returned to the
MII receive data path (see ICS1889 Block Diagram, page 2).

Data Rate (bit 13)

This bit is permanently set to a logic one indicating that only
the 100 Mbps mode is supported.

Auto-Negotiation Enable (bit 12)

This feature is not available with fiber optic solutions. This bit
is permanently set to a logic zero indicating that it is not
supported.

Power-Down (bit 11)

Setting it to logic one will cause the ICS1889 to isolate its
transmit data output and its MII interface with the exception
of the management interface. The ICS1889 will then enter a
power-down mode where only the management interface and
logic remain active. Setting this bit to logic zero after it has
been set to a logic one will cause the ICS1889 to power-up its
logic and then reset all error conditions. It then enables
transmit data and the MII interface. This process takes 500 ms
to complete.

Control Register (register 0)

BIT Function Effect when bit = 0 Effect when bit = 1 Access Default

15

Reset No Effect Reset PHY

RW/S C 0

14

Loop Back Disable loop back mode Enable loop back mode

RW 0

13

Data Rate Always set to a logic one 100 Mpbs operation

RO 1

12

Auto-Negotiate Enable No Effect Alwa ys set to logic zero

RO 0

11

Power-Down Normal Mode Reduced power consumption

RW 0

10

Isolate No Effect Isolate PHY from M II

RW 0 if PHY

Address

< >0,

1 if PHY

Address=0

9

Restart Auto-Negotitation No Effect Alwa ys set to logic zero

RO 0

8

Duplex Mode Half Duplex Full Duplex

RW 0

7

Collision Test No Effect Enable collision signal test

RW 0

6

Reserved

RO 0

5

Reserved

RO 0

4

Reserved

If read, bits 0-6 and bits 9 and 12 wi ll return logic
zeroes and bit 13 will return a logic one.

RO 0
3 RO 0
2

Reserved Writes to these bits will have no effect.

RO 0
1

Reserved

RO 0
0

Reserved

RO 0

9

ICS1889

Isolate (bit 10)

Setting this bit to a logic one causes the ICS1889 to isolate its
data paths from the MII. In this mode, sourced signals
(TXCLK, RXCLK, RXDV, RXER, RXD0-3, COL and CRS)
are in a high impedance state and input signals (TXD0-3,
TXEN and TXER) are ignored. The management interface is
unaffected by this command.

When the PHY address is set to 0, the device will power-up in
the isolated mode (bit 10=1). For all other addresses, the
default will be bit 10=0.

Restart Auto-Negotiation (bit 9)

This feature is not available with fiber optic solutions. This
bit is permanently set to a logic zero indicating that it is not
supported.

Duplex Mode (bit 8)

Setting this bit to a logic one causes the ICS1889 to operate in
the full duplex mode and setting this bit to a logic zero causes
it to operate in the half duplex mode. If the ICS1889 is
operating in loop back mode, this bit will have no effect on
the operation.

Collision Test (bit 7)

This command bit is used to test that the collision circuitry is
working when the ICS1889 is operating in the loop back
mode. Setting this bit to a logic one causes the ICS1889 to
assert the collision signal within 512 bit times of TXEN being
asserted and to de-assert it within 4-bit times of TXEN being
de-asserted. Setting this bit to a logic zero causes the
ICS1889 to operate in the normal mode.

Reserved (Bits 6 through 0)

These bits are reserved for future IEEE standards. When read,
logic zeroes are returned. Writing has no effect on ICS1889
operation.

10

ICS1889

Status Register (register 1)

The ICS1889 status register is a 16 bit read only register
used to indicate the basic status of the ICS1889. It is
accessed via the management interface of the MII. It is
initialized during a power-up or reset to predefined default
values. If the ICS1889 is enabled for auto-configuration,
certain bits in the status register may be set to zero as defined
below.

100Base-T4 (bit 15)

This bit is permanently set to a logic zero indicating that the
ICS1889 is not able to support 100Base-T4 operation.

100Base-X Full Duplex (bit 14)

This bit defaults to a logic one indicating that the ICS1889 is
able to support 100Base-X Full Duplex operation.

100Base-X Half Duplex (bit 13)

This bit defaults to a logic one indicating that the ICS1889 is
able to support 100Base-X Half Duplex operation.

10 Mbps Full Duplex (bit 12)

This bit is permanently set to a logic zero indicating that
10Base-T is not supported.

10 Mbps Half Duplex (bit 11)

This bit is permanently set to a logic zero indicating that
10Base-T is not supported.

Reserved (bits 10 through 6)

These bits are reserved for future IEEE standards. When read,
logic zeroes are returned. Writing has no effect on ICS1889
operation.

Auto-Negotiation Complete (bit 5)

This bit is permanently set to a logic zero.

Remote Fault (bit 4)

When set to a logic one, this bit indicates that a remote fault
(Far End Fault) has been detected by the Link Monitor. This
bit remains set to a logic one until it is cleared by reading the
status register or by a reset command

If the link partner is implemented with a non-ICS1889 device,
the causes of a link failure will be specified by that PHY
vendor. If the link partner is implemented with an ICS1889, a
remote fault indication means a receive channel error
occurred.

Auto-Negotiation Ability (bit 3)

This feature is not available with fiber optic solutions. This bit
is permanently set to a logic zero indicating that it is not
supported.

Control Register (register 1)

BIT Definition When bit = 0 When bit = 1 Access Default

15 OUI bit 19 | s CW 0
14 OUI bit 20 | t CW 1
13 OUI bit 21 | u CW 1
12 OUI bit 22 | v CW 0
11 OUI bit 23 | w CW 0
10 OUI bit 24 | x CW 0

9 Manufacturer’s Model Number bit 5 CW 0
8 Manufacturer’s Model Number bit 4 CW 0
7 Manufacturer’s Model Number bit 3 CW 0
6 Manufacturer’s Model Number bit 2 CW 0
5 Manufacturer’s Model Number bit 1 CW 0
4 Manufacturer’s Model Number bit 0 CW 1
3 Revision Number bit 3 CW 0
2 Revision Number bit 2 CW 1
1 Revision Number bit 1 CW 0
0 Revision Number bit 0 CW 1

11

ICS1889

Link Status (bit 2)

When set to a logic one, this bit indicates that the Link
Monitor has established a valid link. If the Link Monitor
detects a link failure, this bit is set to a logic zero and remains
zero through the next read of the status register. A link failure
may be due to an error in the receive channel or an error in the
receive channel of the link partner (that is, a remote fault).

Jabber detect (bit 1)

This bit is permanently set to a logic zero.

Extended Capability (bit 0)

This bit is permanently set to a logic one indicating that the
ICS1889 has an extended register set.