144 MHz FM TRANSCEIVER
iC-t2h
iC-t2e-t
INTRODUCTION
This service manual describes the latest service information for
the IC-T2H/E-T FM TRANSCEIVER at the time of publication.
MODEL VERSION SYMBOL
IC-T2H
U.S.A.
Europe
U.K.
Italy
Asia SEA
C.S. America/-1 CSA/-1
USA
EUR
UK
ITA
Taiwan
Asia-1 ANI
IC-T2E-T
To upgrade quality, all electrical or mechanical parts and internal circuits are subject to change without notice or obligation.
Thailand
TWN
THA
DANGER
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 16 V. Such a connection
could cause a fire hazard and/or electric shock.
DO NOT expose the transceiver to rain, snow or any liq-
uids.
DO NOT reverse the polarities of the power supply when
connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100
mW) to the antenna connector. This could damage the
transceiver’s front end.
ORDERING PARTS
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
1140006560 S.IC HD6433875A45H IC-T2H MAIN UNIT 1 piece
8810009560 Screw B0 2 × 6 ZK IC-T2H CHASSIS 6 pieces
Addresses are provided on the inside back cover for your
convenience.
REPAIR NOTES
1. Make sure a problem is internal before disassembling the transceiver.
2. DO NOT open the transceiver until the transceiver is disconnected from its power source.
3. DO NOT force any of the variable components. Turn them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the transceiver is defective.
6. DO NOT transmit power into a signal generator or a sweep generator.
7. ALWAYS connect a 40 dB or 50 dB attenuator between the transceiver and a deviation meter or spectrum analyser when
using such test equipment.
8. READ the instructions of test equipment thoroughly before connecting equipment to the transciver.
TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASSEMBLY INSTRUCTIONS
SECTION 4 CIRCUIT DESCRIPTION
4 - 1 RECEIVER CIRCUITS ................................................................................................... 4 – 1
4 - 2 TRANSMITTER CIRCUITS ........................................................................................... 4 – 2
4 - 3 PLL CIRCUIT .................................................................................................................. 4 – 3
4 - 4 POWER SUPPLY CIRCUITS ........................................................................................ 4 – 3
4 - 5 CPU PORT ALLOCATIONS ........................................................................................... 4 – 4
SECTION 5 ADJUSTMENT PROCEDURES
5 - 1 PREPARATION............................................................................................................... 5 – 1
5 - 2 PLL AND TRANSMITTER ADJUSTMENTS................................................................... 5 – 2
5 - 3 RECEIVER ADJUSTMENT ............................................................................................ 5 – 3
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS AND DISASSEMBLY
SECTION 8 SEMI-CONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
SECTION 10 BLOCK DIAGRAM
SECTION 11 VOLTAGE DIAGRAM
1 - 1
SECTION 1 SPECIFICATIONS
■ GENERAL
• Frequency coverage :
Guaranteed frequency range: *144–148 MHz
• Mode : FM (F2, F3)
• Current drain
(at 9.6 V DC) : Transmit at 6.0 W 1.6 A(typical)
at 5.0 W 1.5 A(typical) [Thailand]
at 1.0 W 0.7 A(typical)
Receive max. audio 210 mA (typical)
power saved 25 mA (typical)
standby 80 mA (typical)
• Frequency stability : ±10 ppm
(0˚C to +50˚C; 32˚F to 122˚F)
• Usable temperature range : –10˚C to 60˚C; 14˚F to 140˚F
• Antenna connector : BNC (50 Ω)
• No. of memory channels : 43 ch (40 regulator, 2 scan edges and 1 call)
• Acceptable power supply : 9.6 V DC (supplied Ni-Cd cells; negative ground)
• Frequency resolution : 5 kHz and 12.5 kHz
• Dimensions (Projections not included) : 58(W)
× 140.5(H) × 32.3(D) mm; 29⁄32(W) × 517⁄32(H) × 19⁄32(D) inch
• Weight
(with BP-199) : 420 g; 14.8 oz
■ TRANSMITTER
• Output power (9.6 V DC) : 6 W typical (high)
5 W typical (high) [Thailand] only
0.7 W typical
(low)
• Modulation system : Variable reactance frequency modulation
• Max. frequency deviation : ±5 kHz
• Spurious emissions : Less than –60 dB
• External microphone connector : 3-conductor 2.5 (d) mm (
1
⁄10”) ⁄ 2 kΩ
■ RECEIVER
• Receive system : Double conversion superheterodyne
• Intermediate frequencies : 1st 30.85 MHz
2nd 450 kHz
• Sensitivity
(12 dB SINAD) : Less than 0.18 µV (–122 dBm)
• Squelch sensitivity
(threshold) : Less than 0.18 µV (–122 dBm)
• Selectivity : More than 15 kHz/–6 dB
Less than 30 kHz/–60 dB
• Spurious and image refection ratio : 60 dB (typical)
(except 2nd IF image frequency)
• Audio output power (at 9.6 V DC) : 500 mW (typical at 10% distortion with an 8 Ω load)
• External speaker connector : 3-conductor 3.5 (d) mm (1⁄8”) ⁄ 8 Ω
All stated specifications are subject to change without notice or obligation.
U.S.A.
Europe, U.K.
Thailand
Italy, Asia,
ANI, C.S.A.
Taiwan
140.000–150.000 MHz*
144.000–146.000 MHz
136.000–174.000 MHz*
145.000–146.000 MHz
136.000–174.000 MHz*
144.000–146.000 MHz
136.000–174.000 MHz*
145.000–146.000 MHz
Version Transmit Receive
2 - 1
SECTION 2 INSIDE VIEWS
• MAIN UNIT
TOP VIEW BOTTOM VIEW
Low-pass filter circuit
RF amplifier
(Q12: 2SK360IG)
Analog switch*
(IC4: BU4066BCFV)
*below the mic.
PLL IC
(IC1: µPD3140GS)
1st mixer circuit
(Q13: 2SK360IG)
FM IF IC
(IC2: TA31136FN)
Power amplifier
(Q1: 2SK3075)
EEP ROM
(IC7: X25040S1-2.7)
TX/RX switching
(D3, D4: MA77)
Antenna switching circuit
(D8, D32: HVU131TRF)
Crystal filter
(FI1: FL-251 30.85 MHz)
VCO circuit
Current detector circuit
Microphone amplifier IC
(IC3: NJM2902V)
PLL reference oscillator
(X1: CR514 15.2 MHz)
CPU (IC8)
APC control circuit
3 - 1
SECTION 3 DISASSEMBLY INSTRUCTIONS
• Removing the chassis panel
q Unscrew 1 nut, A, and remove 1 nob, B.
w Unscrew 2 screws,
C
.
e Remove the the chassis in the direction of the arrow.
r Unplug J6 to separate front panel and chassis.
• Removing the MAIN unit
q Remove the sealing rubber.
w Unsolder 2 points,
D
, and unscrew 1 nut, E.
e Unscrew 2 screws,
F
, and 6 screws, G(silver, 2 mm), to separate the chassis and MAIN unit.
r Remove the MAIN unit in the direction of the arrow.
Chassis
C
(nickel, 2 mm) × 2
J6 (Speaker connector)
Front panel
A
Nut
B
Nob
F
(black, 2 mm) × 2
G
G
MAIN unit
Sealing rubber
E
Nut
Chassis
G
G
G
D
G
(silver, 2 mm) × 6
MAIN UNIT (Top view)
[chassis panel]
4 - 1
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT
Received signals passed through the low-pass filter (L1–L3,
C1–C7). The filtered signals are applied to the
λ/4 type
antenna switching circuit (D8, D32, L15, L16, C76–C78).
The antenna switching circuit functions as a low-pass filter
while transmitting. However, its impedance becomes very
high while D8 and D32 are turned ON. Thus transmit signals
are blocked from entering the receiver circuits. The antenna
switching circuit employs a
λ/4 type diode switching system.
The passed signals are then applied to the RF amplifier circuit.
4-1-2 RF CIRCUIT
The RF circuit amplifies signals within the range of frequency coverage and filters out-of-band signals.
The signals from the antenna switching circuit pass through
a bandpass filter (D10, L26) after being amplified at the RF
amplifier (Q29). The filtered signals are amplified at another
RF amplifier (Q12), then applied to the 1st mixer circuit after
out-of-band signals are suppressed at the bandpass filter
(D11, D12, L18, L19, C92, C94, C96, C236).
D10–D12 employ varactor diodes that track the bandpass filters and are controlled by the T4/PWR signal from the CPU
(IC8, pins 54–59). These diodes tune the center frequency of
an RF passband for wide bandwidth receiving and good
image response rejection.
4-1-3 1ST MIXER AND 1ST IF CIRCUITS
The 1st mixer circuit converts the received signal to a fixed
frequency of the 1st IF signal with a PLLoutput frequency. By
changing the PLL frequency, only the desired frequency will
pass through a crystal filter at the next stage of the 1st mixer.
The signals from the RF circuit are mixed at the 1st mixer
(Q13) with a 1st LO signal coming from the VCO circuit to
produce a 30.85 MHz 1st IF signal.
The 1st IF signal is applied to a crystal filter (FI1) to suppress
out-of-band signals. The filtered 1st IF signal is applied to the
IF amplifier (Q14), then applied to the 2nd mixer circuit (IC2,
pin 16).
4-1-4 2ND IF AND DEMODULATOR CIRCUITS
The 2nd mixer circuit converts the 1st IF signal to a 2nd IF
signal. A double conversion superheterodyne system (which
converts receive signal twice) improves the image rejection
ratio and obtains stable receiver gain.
The 1st IF signal from the IF amplifier is applied to the 2nd
mixer section of the FM IF IC (IC2, pin 16), and is mixed with
the 2nd LO signal to be converted to a 450 kHz 2nd IF signal.
The FM IF IC contains the 2nd mixer, limiter amplifier, quadrature detector and active filter circuits. A 30.4 MHz 2nd LO
signal is produced at the PLLcircuit by doubling it’s reference
frequency.
The 2nd IF signal from the 2nd mixer (IC2, pin 3) passes
through a ceramic filter (FI2) to remove unwanted heterodyned frequencies. It is then amplified at the limiter amplifier
(IC2, pin 5) and applied to the quadrature detector (IC2, pins
10, 11) to demodulate the 2nd IF signal into AF signals.
4-1-5 AF CIRCUIT
The AF amplifier circuit amplifies the demodulated AF signals
to drive a speaker.
AF signals from the FM IF IC (IC2, pin 9) are applied to the
analog switch (IC4, pin 1) via the AF filter circuit (IC3b, pins
6, 7). The output signals from pin 11 are applied to the AF
power amplifier (IC5, pin 4) after passing through the [VOL]
control (VR board, R1).
• 2nd IF AND DEMODULATOR CIRCUITS
Mixer
16
Limiter
amp.
2nd IF filter
450 kHz
PLL IC
IC1
X1
15.2 MHz
IC2 TA31136F
13
1st IF from the IF amp.
"NOIS" signal to the CPU pin 19
11109
87 5 3
AF signal "DET"
R5
"SD" signal to the CPU pin 98
X3
Squelch level
adjustment pot
R92
2
17 16
Active
filter
FI2
Noise
detector
RSSI
Trigger
FM
detector
12
✕2
4 - 2
The AF signals from the [VOL] control are applied to the AF
power amplifier circuit (IC5, pin 4) to obtain the specified
audio level. The amplified AF signals, output from pin 10, are
applied to the internal speaker (SP1) via the [SP] jack when
no plug is connected to the jack.
4-1-6 SQUELCH CIRCUIT
A squelch circuit cuts out AF signals when no RF signals are
received. By detecting noise components in the AF signals,
the squelch switches the analog switch.
A portion of the AF signals from the FM IF IC (IC2, pin 9) are
applied to the active filter section (IC2, pin 8) where noise
components are amplified and detected with an internal
noise detector. The squelch input level adjustment pot (R92)
is connected in parallel to the active filter input (pin 8) to control the input noise level.
The trigger circuit converts the detected signals to a HIGH or
LOW signal and applies this (from pin 13) to the CPU (IC8,
pin 19) as the NOIS signal. When the CPU receives a HIGH
level NOIS signal, the CPU controls the RMUT line to cut the
AF signals at the analog switch IC (IC4). At the same time,
the AFON line controls the AF regulator circuit (Q15, Q16) to
cut out the VCC power source for the AF power amplifier
(IC5).
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT
The microphone amplifier circuit amplifies audio signals with
+6 dB/octave pre-emphasis characteristics from the microphone to a level needed for the modulation circuit.
The AF signals from the microphone are applied to the microphone amplifier circuit (IC3c, pin 10). The amplified AF signals are passed through the low-pass filter circuit (IC3d, pins
13, 14) via the analog switch (IC4, pins 2, 3). The filtered AF
signals are applied to the modulator circuit after passing
through the analog switch (IC4, pins 8, 9) and the deviation
adjustment pot (R119).
4-2-2 MODULATION CIRCUIT
The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone audio signal.
The audio signals (SHIFT) change the reactance of D6 to
modulate an oscillated signal at the VCO (Q7, Q8). The oscillated signal is amplified at the buffer-amplifiers (Q4, Q6),
then applied to the T/R switching circuit (D3, D4).
4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS
The signal from the VCO circuit passes through the T/R
switching circuit (D3) and is amplified at the buffer (Q3), drive
(Q2) and power (Q1) amplifiers to obtain 5.5 W (4.5 W:
Thailand only) of RF power (at 9.6 V DC/typical). The amplified signal passes through the antenna switching circuit (D1),
and low-pass filter (L1–L3, C1–C7) and is then applied to the
antenna connector (J1).
The bias current of the drive (Q2) and power (Q1) amplifiers
is controlled by the APC circuit to stabilize the output power.
4-2-4 CURRENT DETECTOR CIRCUIT
The current detector circuit (Q9, Q28, R161) detects total driving current of the drive and the power amplifiers, using the
current sensor (R161). The differential amplifier (Q9) detects
voltage differences between the current sensor input and
output voltages, then outputs control voltage to the APC circuit.
• APC circuit
Q1
Power
amp.
Q2
Driver
amp.
IC3a
3
1
2
T5
VCC
Q9Q28
R161
RF signal
from PLL
to antenna
T4
TXC
Q37
S5
Current detector circuit
APC control circuit
• Analog switch (IC4)
MIC signal
DET signal
to the VCO circuit
for modulation
R5C
R5
MMUT signal
RMUT signal
to the [VOL]
control
1
2
3
4
5
68
9
10
11
12
13
to pins 9, 10
via IC3d
from IC3d
4 - 3
4-2-5 APC CIRCUIT
The APC circuit (IC3a, Q37) protects drive and power amplifiers from excessive currents and selects HIGH or LOW output power.
The output voltage from the current detector circuit is applied
to the inverting amplifier (IC3a, pin 2), and the T4/PWR signal from the CPU (IC8, pins 54–59) is applied to the other
input for reference.
When the driving current increases, the input voltage of the
differential amplifier (Q9, pin 1) will be decreased. In such
cases, input voltage of the inverting amplifier (pin 2) is
increased to decrease the output power.
Q37 is controlled by the TXC signal from the CPU (IC8, pin
50) to select HIGH or LOW output power.
4-3 PLL CIRCUIT
A PLL circuit provides stable oscillation of the transmit frequency and receive 1st LO frequency. The PLL output compares the phase of the divided VCO frequency to the reference frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the VCO circuit (Q7, Q8, D6). The
oscillated signal is amplified at the buffer-amplifiers (Q5, Q6)
and then applied to the PLL IC (IC1, pin 2).
The PLLIC contains a prescaler, programmable counter, programmable divider, phase detector and charge pump, etc.
The entered signal is divided at the prescaler and programmable counter section by the N-data ratio from the CPU. The
divided signal is detected on phase at the phase detector
using the reference frequency.
If the oscillated signal drifts, its phase changes from the reference frequency, causing a lock voltage change to compensate for the drift in the oscillated frequency.
A portion of the VCO signal is amplified at the buffer-amplifier (Q4, Q6) and is then applied to the receive 1st mixer or
transmit buffer-amplifier circuit via the T/R switching diode
(D3, D4).
4-4 POWER SUPPLY CIRCUITS
VOLTAGE LINE
Description
The voltage from the attached battery pack/case.
The same voltage as the BATT line controlled by
the [PWR/VOL] control.
Common 5 V converted from the VCC line by the
reference regulator circuit (IC6). The output voltage is applied to the CPU (IC8) and the 5V regulator circuit, etc.
Common 5 V converted from the VCC line at the
5 V regulator circuit (Q18, Q19) using the CPU5
line voltage for reference.
Transmit 5 V converted from the VCC line at the
T5 regulator circuit (Q22, Q40).
Receive 5 V converted from the 5 V line at the R5
regulator circuit (Q21). The regulated voltage is
applied to the receiver circuits.
Common 5 V converted from the 5V line by the S5
regulator circuit (Q20).
The same voltage as the 5V line for the optional
HM-75A or HS-51 through a resistor (R132).
Line
BATT
VCC
CPU5
5V
T5
R5
S5
OPT
• PLL circuit
Shift register
2
Prescaler
Phase
detector
Loop
filter
Programmable
counter
Programmable
divider
X1
15.2 MHz
30.4 MHz signal
to the FM IF IC
16
Q7, Q8
VCO board
Buffer
Q6
Buffer
Q4
Buffer
Q5
3
4
5
PLST
SCK
SO
to transmitter circuit
to 1st mixer circuit
D4
D3
17
8
2