Icom IC-F510, IC-F520 Service manual

SERVICE
MANUAL

UHF TRANSCEIVER

iF510
iF520

VERSION

Europe

General

U.S.A.

SYMBOL

EUR

GEN

USA

INTRODUCTION

This service manual describes the latest service information
for the IC-F510 and IC-F520 VHF TRANSCEIVERS at the
time of publication.

DANGER

NEVER connect the transceiver to an AC outlet or to a DC

power supply that uses more than 16 V. This will ruin the
transceiver.

DO NOT expose the transceiver to rain, snow or any liquids.

DO NOT reverse the polarities of the power supply when

connecting the transceiver.

DO NOT apply an RF signal of more than 20 dBm (100 mW)
to the antenna connector. This could damage the transceiv­er’s front end.

ORDERING PARTS

Be sure to include the following four points when ordering
replacement parts:

1. 10-digit order numbers

2. Component part number and name

3. Equipment model name and unit name

4. Quantity required

<SAMPLE ORDER>

1110003490 S.IC TA31136FN IC-F510 MAIN UNIT 5 pieces

8810009990 Screw PH BT M3

×8 ZK IC-F520 Bottom cover 10 pieces

Addresses are provided on the inside back cover for your
convenience.

REPAIR NOTES

1. Make sure a problem is internal before disassembling the
transceiver.

2. DO NOT open the transceiver until the transceiver is
disconnected from its power source.

3. DO NOT force any of the variable components. Turn
them slowly and smoothly.

4. DO NOT short any circuits or electronic parts. An insu­lated tuning tool MUST be used for all adjustments.

5. DO NOT keep power ON for a long time when the trans­ceiver is defective.

6.

DO NOT transmit power into a signal generator or a
sweep generator.

7.

ALWAYS connect a 40 dB to 50 dB attenuator between
the transceiver and a deviation meter or spectrum ana­lyzer when using such test equipment.

8.

READ the instructions of test equipment thoroughly
before connecting equipment to the transceiver.

MODEL

IC-F510

IC-F520

To upgrade quality, any electrical or mechanical parts and
internal circuits are subject to change without notice or
obligation.

TABLE OF CONTENTS

SECTION 1 SPECIFICATIONS

SECTION 2 INSIDE VIEW

SECTION 3 DISASSEMBLY INSTRUCTIONS

SECTION 4 CIRCUIT DESCRIPTION

4 - 1 RECEIVER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1

4 - 2 TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2

4 - 3 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 3

4 - 4 POWER SUPPLY CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 4

4 - 5 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 4

SECTION 5 ADJUSTMENT PROCEDURES

5 - 1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1

5 - 2 PLL ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 3

5 - 3 SOFTWARE ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 4

SECTION 6 PARTS LIST

SECTION 7 MECHANICAL PARTS

SECTION 8 SEMI-CONDUCTOR INFORMATION

SECTION 9 BOARD LAYOUTS

9 - 1 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 1

9 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 3

SECTION 10 BLOCK DIAGRAM

SECTION 11 VOLTAGE DIAGRAMS

11 - 1 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 1

11 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 2

EXPLICIT DEFINITIONS

136 – 174 MHz

FREQUENCY COVERAGE

12.5 kHz / 25.0 kHz

15.0 kHz / 30.0 kHz

12.5 kHz / 20.0 kHz

Narrow/Wide-type

Narrow/Middle-type

CHANNEL SPACING

1 - 1

All stated specifications are subject to change without notice or obligation.

SECTION 1 SPECIFICATIONS

Measurement method

Frequency coverage

Type of emission

Number of conventional channels

Power supply voltage (negative ground)

Current drain (approx.)

Frequency error

Usable temperature range

Dimensions (proj. not included)

Weight

RF output power

Modulation system

Maximum permissible deviation

Spurious emissions

Adjacent channel power

Audio frequency response

Audio hormonic distortion

FM hum and noise (typical)
(without CCICT filter)

Residual modulation (typical)
(with CCICT filter)

Limitting charact of modulator

Microphone connector

Receive system

Intermediate frequencies

Sensitivity (typical)

Squelch sencitivity (at threshold) (typical)

Adjcent channel selectivity (typical)

Spurious response

Intermoduration (typical)

Hum and noise

(without CCITT filter)

(typical)

(with CCITT filter)

Audio output power

External SP connector

USA/GEN EUR

RECEIVER TRANSMITTER GENERAL

EIA-152-C/204D or TIA-603 ETS 300 086

136.000–174.000 MHz

N/W (15 kHz; Narrow/30 kHz; Wide): 8K50F3E/16K0F3E [USA],
N/W (12.5 kHz; Narrow/25 kHz; Wide): 8K50F3E/16K0F3E [EUR/GEN],
N/M (12.5 kHz; Narrow/20 kHz; Middle): 8K50F3E/14K0F3E [EUR]

Max. 256 ch (16 channels

× 16 banks)

13.6 V DC nominal 13.2 V DC nominal

TX at 25 W 7.0 A
Rx max. audio 1200 mA

stand-by 300 mA

5.0 ppm ±1.5 kHz

–30˚C to +60˚C (–22˚F to +140˚F) –25˚C to +55˚C (–13˚F to +131˚F)

140(W)

× 40(H) × 170(D) mm; 5

1

⁄2(W) × 19⁄16(H) × 611⁄16(D) inch

1.2 kg; 2 lb 10 oz

25 W / 10 W / 2.5 W (High/Low2/Low1)

Variable reactance frequency modulation

±2.5 kHz [Narrow], ±4.0 kHz [Middle], ±5.0 kHz [Wide]

70 dBc typical 0.25 µW ≤ 1GHz, 1.0 µW > 1 GHz

60 dB [Narrow], 70 dB [Middle/Wide]

+2 dB to –5 dB of 6 dB/octarve
range from 300 Hz to 2550 Hz [Narrow]/3000 Hz [Middle/Wide]

3% typical at 1 kHz, 40% deviation

40 dB [Narrow], 46 dB [Wide] ——

——

50 dB [Narrow], 53 dB [Middle],
55 dB [Wide]

70–100% of max. deviation

8-pin modular (600 Ω)

Double-conversion superheterodyne system

1st: 46.35 MHz, 2nd: 450 kHz

0.25 µV at 12 dB SINAD –4 dBµV (emf) at 20 dB SINAD

0.25 µV –4 dBµV (emf)

65 dB [Narrow], 75 dB [Middle/Wide]

75 dB

74 dB 67 dB

40 dB [Narrow], 45 dB [Wide] ——

——

50 dB [Narrow], 53 dB [Middle], 55 dB [Wide]

4 W typical at 10% distortion with a 4 Ω load

2-conductor 3.5 (d) mm (

1

⁄8")/4 Ω

SECTION 2 INSIDE VIEW

2 - 1

Power module
(IC3: RA30H1317)

8V regurator
(IC9: TA7808F)

AF amplifier
(IC8: LA4425A)

CPU 5V regurator*
(IC10: AN78L05M)

VCO circuit

CPU*
(IC20: HD64F2268TF)

Antenna switch/
Low-pass filter circuits

1st mixer*
(Q3: 3SK272)

2nd IF filter
(FI2: ALFYM450F=K [N/W]

CFWM450G [N/M])

FM IF IC
(IC1: TA31136FN)

D/A converter
(IC6: M62364FP)

Referance crystal osillator
(X2: CR-664A 15.3 MHz)

PLL IC
(IC4: TB31256FL)

*Located under side of the point.

1st IF filter
FI1: FL-335

SECTION 3 DISASSEMBLY INSTRUCTIONS

3 - 1

• Opening case

➀ Unscrew 4 screws A, and remove the bottom cover.
➁ Disconnect the flat cable B from J2.
➂ Unscrew 2 screws c, and remove the front unit.

A

B

C

J2

➃ Unsolder 3 points D from the antenna connector.
➄ Remove the clip E.
➅ Disconnect the cable F from J5.
➆ Unscrew 11 screws G.

G

F

E

J5

D

➇ Lift up the front portion of the main unit and remove it.

• Instllation location

UT-105 SmarTrank2 Logic Board
UT-108 DTMF decoder unit
UT-109

Voice scrambler unit

UT-110
UT-111 Trunking unit

UT-105
UT-108
UT-109
UT-110
UT-111

J1

SECTION 4 CIRCUIT DESCRIPTION

4 - 1

4-1 RECEIVER CIRCUITS

4-1-1 ANTENNA SWITCHING CIRCUIT (MAIN unit)

The antenna switching circuit functions as a low-pass filter
while receiving and as resonator circuit while transmitting.
The circuit does not allow transmit signals to enter receiver
circuits.

Received signals enter the antenna connector and pass
through the low-pass filter (L1–L3, C1, C2, C6–8). The fil-
tered signals are then applied to the RF circuit passed
through the λ⁄4 type antenna switching circuit (D5, D6, L6).

4-1-2 RF CIRCUIT (MAIN unit)

The RF circuit amplifies signals within the range of frequen­cy coverage and filters out-of-band signals.

The signals from the antenna switching circuit pass through
the two-stage tunable bandpass filters (D8, D4). The filtered
signals are amplified at the RF amplifier (Q2) and then enter
other two-stage bandpass filters (D9, D10) to suppress
unwanted signals. The filtered signals are applied to the 1st
mixer circuit (Q3).

The tunable bandpass filters (D4, D8–D10) employ varactor
diodes to tune the center frequency of the RF passband for
wide bandwidth receiving and good image response rejec­tion. These diodes are controlled by the CPU (IC20) via the
D/A converter (IC7).

The gate control circuit reduces RF amplifier gain and atten­uates RF signal to keep the audio output at a constant level.

The receiver gain is determined by the voltage on the “RSSI”
line from the FM IF IC (IC1, pin 12). The gate control circuit
supplies control voltage to the RF amplifier (Q2) and sets
the receiver gain.

When receiving strong signals, the “RSSI” voltage increases
and the gate control voltage decreases. As the gate control
voltage is used for the bias voltage of the RF amplifier (Q2),
then the RF amplifier gain is decreased.

4-1-3 1ST MIXER AND 1ST IF CIRCUITS

(MAIN unit)

The 1st mixer circuit converts the received signals to a fixed
frequency of the 1st IF signal with the PLL output frequency.
By changing the PLL frequency, only the desired frequency
will pass through a MCF (Monolithic Crystal Filter; FI1) at the
next stage of the 1st mixer.

The RF signals from the bandpass filter are applied to the
1st mixer circuit (Q3). The applied signals are mixed with the
1st LO signal coming from the RX VCO circuit (Q13) to pro­duce a 46.35 MHz 1st IF signal. The 1st IF signal passes
through a MCF (Monolithic Crystal Filter; FI1) to suppress
out-of-band signals. The filtered signal is amplified at the 1st
IF amplifier (Q4) and applied to the 2nd IF circuit.

4-1-4 2ND IF AND DEMODULATOR CIRCUITS

(MAIN unit)

The 2nd mixer circuit converts the 1st IF signal to a 2nd IF
signal. A double-conversion superheterodyne system
improves the image rejection ratio and obtains stable receiv­er gain.

The 1st IF signal from the 1st IF amplifier (Q4) is applied to
the 2nd mixer section of the FM IF IC (IC1, pin 16) and is
then mixed with the 2nd LO signal for conversion to a 450
kHz 2nd IF signal.

IC1 contains the 2nd mixer, limiter amplifier, quadrature
detector, active filter and noise amplifier circuits, etc. A
tripled frequency from the PLL reference oscillator is used
for the 2nd LO signal (45.9 MHz).

The 2nd IF signal from the 2nd mixer (IC1, pin 3) passes
through a ceramic filter (FI2) to remove unwanted hetero­dyned frequencies. It is then amplified at the limiter amplifi­er section (IC1, pin 5) and applied to the quadrature detec­tor section (IC1, pins 10, 11 and X1) to demodulate the 2nd
IF signal into AF signals.

The AF signals are output from pin 9 (IC1) and are then
applied to the AF amplifier circuit.

• 2nd IF and demodulator circuits

FI2

2nd IF filter
450 kHz

Noise

detector

Q34

Limiter
amp.

FM

detector

Active
filter

AF signals

5V

X1 Discriminator

IC6

RSSI

Mixer

X2

15.3 MHz

45.9 MHz

1st IF from the IF amplifier (Q4)

NOIS signal to the CPU (IC20)

8

24

23

7

5

BPF

32

3

161311109

IC1
TA31136FN

4 - 2

4-1-5 AF AMPLIFIER CIRCUIT (MAIN unit)

The AF amplifier circuit amplifies the demodulated AF sig­nals to drive a speaker.

The AF signals from the FM IF IC (IC1, pin 9) are amplified
at the AF amplifier section of the compander IC (IC14, pins
5, 4) and are then applied to the high-pass filter circuit
(IC21b).

The high-pass filter characteristics are controlled by the
FSW signal from the LCD driver IC (FRONT unit; IC1, pin 6).
When FSW signal is high, the cut-off frequency is shifted
higher to remove CTCSS or DTCS signals.

The filtered AF signals from the high-pass filter (IC21b,
pin 7) are applied to the de-emphasis section of compander
IC (IC14, pin 3) with frequency characteristics of –6
dB/octave, and are then passed through the low-pass filter,
high-pass filter, expander sections of compander IC (IC14).
The output signal from IC14 (pin 38) is applied to the elec­tronic volume controller (IC6, pin 1).

The output AF signals from the electronic volume controller
(IC6, pin 2) are applied to the AF power amplifier (IC8) to
drive the speaker.

4-1-6 RECEIVER MUTE CIRCUITS (MAIN unit)

• NOISE SQUELCH

The noise squelch circuit cuts out AF signals when no RF
signals are received. By detecting noise components in the
AF signals, the squelch circuit switches the AF mute switch.

Some noise components in the AF signals from the FM IF IC
(IC1, pin 9) are passed through the level controller (IC6, pins
24, 23). The level controlled signals are applied to the active
filter section in the FM IF IC (IC1, pin 8). Noise components
about 10 kHz are amplified and output from pin 7.

The filtered signals are converted into the pulse-type signals
at the noise detector section and output from pin 13 (NOIS).

The NOIS signal from the FM IF IC is applied to the CPU
(IC20, pin 37). The CPU then analyzes the noise condition
and controls the AF mute signal via “AFON” line (IC20, pin

18) to the AF regulator (Q39, Q40, D31).

• CTCSS AND DTCS

The tone squelch circuit detects AF signals and opens the
squelch only when receiving a signal containing a matching
subaudible tone (CTCSS or DTCS). When tone squelch is in
use, and a signal with a mismatched or no subaudible tone
is received, the tone squelch circuit mutes the AF signals
even when noise squelch is open.

A portion of the AF signals from the FM IF IC (IC1, pin 9)
passes through the low-pass filter (IC5) to remove AF
(voice) signals and is applied to the CTCSS or DTCS
decoder inside the CPU (IC20, pin 46) via the “CDEC” line
to control the AF mute switch.

4-2 TRANSMITTER CIRCUIT

4-2-1 MICROPHONE AMPLIFIER CIRCUIT

(MAIN unit)

The microphone amplifier circuit amplifies audio signals
within +6 dB/octave pre-emphasis characteristics from the
microphone to a level needed for the modulation circuit.

The AF signals (MIC) from the FRONT unit via J2 (pin 1) are
passed through the level controller (IC6, pins 9, 10) to the
microphone amplifier circuit.

The AF signals from the level controller (IC6) are applied to
the microphone amplifier section of compander IC (IC14, pin

12). The amplified signals are passed through the compres-

sor, low-pass filter and high-pass filter sections of IC14.

The filtered AF signals are amplified at the buffer amplifier
(Q21) and pre-emphasized with +6dB/octave at the pre­emphasis circuit (R122, C187), and are then applied to the
IDC amplifier section of IC14 (pin 8).

The amplified AF signals are passed through the limitter
amplifier, low-pass filter and smoothing filter sections of
IC14 after being passed through the AF mute switch inside
of IC14.

The output signals from pin 6 are passed through the ana­log switch (IC15), splatter filter (IC21d) and applied to the
level controller (IC6, pins 21, 22). The deviation level con­trolled signals are then applied to modulation circuit as the
“MOD” signal.

The narrow/wide switch (Q22) is connected to the input of
the splatter filter (IC21d) and switched by the “NWC” signal
coming from the CPU (IC20, pin 19). When “NWC” is at a
high level, the narrow/wide switch (Q22) shifts the filter cut­off frequency for narrow deviation selection.

4-2-2 MODULATION CIRCUIT

The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone audio signals.

The AF signals from the level controller (IC6, pin 22) change
the reactance of varactor diode (D18) to modulate the oscil­lated signal at the TX VCO circuit (Q14, D17, D53–D55).
The modulated VCO signal is amplified at the buffer ampli­fiers (Q11, Q10) and is then applied to the drive amplifier cir­cuit via the T/R switch (D14).

The CTCSS/DTCS signals from the CPU (IC20, pins 89–91)
are passed through the low-pass filter (Q37), level controller
(IC6, pins 12, 11) and mixer (IC21a), and are then applied to
the VCO circuit via the splatter filter (IC21d).

4-2-3 DRIVE AMPLIFIER CIRCUIT (MAIN unit)

The drive amplifier circuit amplifies the VCO oscillating sig­nal to the level needed at the power amplifier.

The RF signal from the buffer amplifier (Q10) passes
through the T/R switch (D14) and is amplified at the YGR
(Q9) and pre-drive (Q8) amplifiers. The amplified signal is
applied to the power amplifier circuit.

4 - 3

4-2-4 POWER AMPLIFIER CIRCUIT (MAIN unit)

The power amplifier circuit amplifies the driver signal to an
output power level.

The RF signal from the pre-drive amplifier (Q8) is applied to
the power module (IC3) to obtain 25 W of RF power.

The amplified signal is passed through the antenna switch­ing circuit (D2), low-pass filter and APC detector, and is then
applied to the antenna connector.

Control voltage for the power amplifier (IC3, pin 3) comes
from the APC amplifier (IC2) to stabilize the output power.
The transmit mute switch (D32) controls the APC amplifier
when transmit mute is necessary.

4-2-5 APC CIRCUIT (MAIN unit)

The APC circuit protects the power amplifier from a mis­matched output load and stabilizes the output power.

The APC detector circuit detects forward signals and reflec­tion signals at D11 and D1 respectively. The combined volt­age is at minimum level when the antenna impedance is
matched at 50 Ω, and is increased when it is mismatched.

The detected voltage is applied to the APC amplifier (IC2,
pin 3), and the power setting “T4” signal from the D/A con­verter (IC7, pin 4), controlled by the CPU (IC20), is applied
to the other input for reference. When antenna impedance is
mismatched, the detected voltage exceeds the power set­ting voltage. Then the output voltage of the APC amplifier
(IC2, pin 4) controls the input current of the power module
(IC3) to reduce the output power.

4-3 PLL CIRCUITS

4-3-1 PLL CIRCUIT

A PLL circuit provides stable oscillation of the transmit fre­quency and receive 1st LO frequency. The PLL output com­pares the phase of the divided VCO frequency to the refer­ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programable divider.

The PLL circuit contains the TX/RX VCO circuit (Q14, Q13).
The oscillated signal is amplified at the buffer amplifiers
(Q11, Q12) and then applied to the PLL IC (IC4, pin 17) via
the low-pass filter (L32, C298, C299, C509).

The PLL IC contains a prescaler, programable counter, pro­gramable divider and phase detector, etc. The entered sig­nal is divided at the prescaler and programable counter sec­tion by the N-data ratio from the CPU. The reference signal
is generated at the reference oscillator (X2) and is also
applied to the PLL IC. The PLL IC detects the out-of-step
phase using the reference frequency, and outputs it from
pin 13. The output signal is passed thorough the charge
pump (Q50, Q51, Q54, Q55) and active loop filter (Q52,
Q53), and is then applied to the VCO circuit as the lock volt­age.

If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.

4-3-2 VCO CIRCUIT

The VCO circuit contains a separate RX VCO (Q13, D16,
D50–D52) and TX VCO (Q14, D17, D18, D53–D55). The
oscillated signal is amplified at the buffer amplifiers (Q11,
Q10) and is then applied to the T/R switch circuit (D14,
D15). Then the receive 1st LO (Rx) signal is applied to the
1st mixer (Q3) and the transmit (Tx) signal to the YGR
amplifier circuit (Q9).

A portion of the signal from the buffer amplifier (Q11) is fed
back to the PLL IC (IC4, pin 5) via the buffer amplifier (Q12)
and low-pass filter (L32, C298, C299, C509) as the compar­ison signal.

• PLL circuit

Controller

×3

16/17

Phase
detector

Loop

filter

Charge

pump

LPF

PLL2

32/33

Phase
detector

PLL1

X2

15.3 MHz

45.9 MHz signal
to the FM IF IC

10

Q13, D16,

D50–D52

RX VCO

TX VCO

Buffer

Buffer

Buffer

Q10

Q12

Q11

Q34

20
21
22

SCK

19

FSW2

IC4 (PLL IC)

SO
PLST

to transmitter circuit

to 1st mixer circuit

D15

D14

13

17

Q14, D17, D18,

D53–D55

4-4 POWER SUPPLY CIRCUITS

4-4-1 VOLTAGE LINES (MAIN unit)

4-5 PORT ALLOCATIONS

4-5-1 OUTPUT EXPANDER (FRONT unit; IC1)

4-5-2 OUTPUT EXPANDER (MAIN unit; IC7)

4-5-3 CPU (MAIN unit; IC20)

Description

The voltage from a DC power supply.

The same voltage as the HV line which is con­trolled by the power switching circuit (Q23, Q24).
When the [POWER] switch is pushed, the CPU
outputs the “PWON” control signal to the power
switching circuit to turn the circuit ON.

Common 5 V for the CPU converted from the HV
line by the CPU5V regulator circuit (IC10). The
circuit outputs the voltage regardless of the
power ON/OFF condition.

Common 8 V converted from the VCC line by the
8V regulator circuit (IC9).

Common 5 V converted from the VCC line by the
5V regulator circuit (Q27, Q28).

Receive 8 V controlled by the R8 regulator circuit
(Q26, Q30, D24) using the “TXC” signal from the
CPU (IC20, pin 16).

Transmit 8 V controlled by the T8 regulator circuit
(Q25, Q29, D23) using the “TMUT” signal from
the CPU (IC20, pin 17).

Line

HV

VCC

CPU5V

8V

5V

R8V

T8V

I/O port for data signals from/to the D/A
converter (IC7).

Outputs strobe signals for the level
controller (or D/A converter) (IC6).

Output ports for LCD control signals to
the LCD driver (FRONT unit; IC1)

Outputs clock signal for the LCD driver
(FRONT unit; IC1)

Outputs data signals for the LCD driver
(FRONT unit; IC1)

Outputs strobe signals for the PLL IC
(IC4).

Outputs control signal for the PLL IC
(IC4).

Outputs R8 regulator circuit (Q26, Q30,
D24) control signal.

Outputs T8 regulator circuit (Q25, Q29,
D23) control signal.

Outputs control signal for the AF mute
circuit (Q39, Q40, D31).

High : While AF amplifier (IC8) is acti-

vated.

Outputs IF bandwidth control signal.

High : While IF bandwidth is narrow.

Input port for the data signals from the
DTMF decoder (IC19).

Outputs clock signal to the DTMF
decoder (IC19).

Outputs data signals to the PLL IC
(IC4), level controller (or D/A converter)
(IC6), compander IC (IC14) and option­al board (connect to J1).

Input port for the clock signal from the
optional board via J1.

Outputs clock signal to the PLL IC
(IC4), level controller (or D/A converter)
(IC6), D/A converter (IC7), compander
IC (IC14) and optional board (connect
to J1).

Outputs chip select signal for the
optional board via J1.

Input ports for the key matrix.

Input port for the PTT switch from the
optional board via J1.

Low : External PTT switch is ON.

Input port for the microphone hanger
detection signal.

Low : Microphone on hook

Outputs BUSY detection signal for the
optional board via J1.

1

2

8,

9

10

11

13

15

16

17

18

19

20

21

22

23

24

25

26–28

29

30

31

DSDA

DAST

LINH,

LCS

LCK

LSO

PLST

FSW2

TXC

TMUT

AFON

NWC

DDSD

DDAC

SO

SI

SCK

CCS

KR2–

KR0

PTTO

HANG

BUSY

Pin Port

Description

number name

4 - 4

Output tunable band pass filter control
signals.

Output port for

tunable band pass filter control signal
while receiving.
output power control signal while
transmitting.

1–34T1–T3

T4

Pin Port

Description

number name

Output ports for key matrix.

Outputs LCD backlight control signal.

Low : While LCD backlight is dim.

Outputs LCD backlight control signal.

Low : While LCD backlight is OFF.

Outputs high-pass filter’s characteris-
tics select signal.

Outputs external device control signal.

High :

When matched 2/5-tone signals
are received.

Output ports for LCD control signal.

1–3

4

5

6

7

12–55

KS0–KS2

DIM1

DIM2

FSW

HORN

SEG1–SEG40,
COM1–COM4

Pin Port

Description

number name

4 - 5

CPU (IC20)—continued CPU (IC20)—continued

Input port for AF mute signal from the
optional board via J1.

Input port for MIC mute signal from the
optional board via J1.

I/O ports for the optional board control
signals.

NOIS signal input port from the FM IF
IC (MAIN unit; IC1) for noise squelch
operation.

Input for the POWER switch.

Low : While POWER switch pushed.

Input port for DTMF detection signal
from the DTMF decoder (IC19).

Remote power control signal input port
from the external connector (J6).

Outputs control signal for the power
switching circuit (Q24, Q23) via D28.

Outputs single tone signal.

Outputs beep audio signals.

Single tone signal input port for decod­ing.

CTCSS/DTCS signals input port for
decoding.

Input port for the PLL unlock signal
from the PLL IC (IC4).

Input port for the overvoltage detection
from the connected power supply.

Input port for the PLL lock voltage.

Input port for receiving signal strength
level detection.

Input port for the transceiver’s internal
temperature.

Input port for the AF volume control
(FRONT unit; R12).

High : [VOL] is maximum clockwise.

Input port for the PTT switch from the
external connector (J6).

Low : External PTT switch is ON.

Input port for the reset signal.

Output port for the cloning signal.

Input port for the cloning signal.

Outputs CPU clock shift signal.

Outputs cut-off frequency control signal
to the low-pass filter (IC5) for
CTCSS/DTCS switching.

Input port for the connected modem
unit via external connector (J9).

32

33

34–36

37

38

39

40

41

43

44

45

46

47

48

49

50

51

52

55

59

68

69

70

71

74

RMUT

MMUT

OPT1–

OPT3

NOIS

POSW

DDST

IGSW

PWON

SENC

BEEP

SDEC

CDEC

ULCK

BATV

LVIN

RSSI

TEMP

AFVI

EPTT

RES

CLO

CLI

CSFT

DUSE

XCTS

Pin Port

Description

number name

Output port for the connected modem
unit via external connector (J9).

Input port for serial data signals from
the connected MAP27 unit via external
connector (J9).

Outputs serial data signals for the con­nected MAP27 unit via external con­nector (J9).

Output serial data signals (data format
is in accordance with NMEA0183) for
the connected unit via external connec­tor (J8).

Input port for serial data signals (data
format is in accordance with
NMEA0183) from the connected unit
via external connector (J8).

Input port for interruption signal from
the optional board via J1

Input port for the LCD backlight control
signal from the external connector (J6).

Output ports for the CTCSS/ DTCS sig­nals.

Outputs reset signal for the compander
IC (IC14).

Output control signals for the compan­der IC (IC14).

Outputs strobe signals to the compan­der IC (IC14).

Outputs control signal for the MSK
PM/FM switching circuit (IC15).

I/O port for the data signals from the
EEPROM (IC23).

Outputs clock signal for the EEPROM
(IC23).

Outputs MIC audio select signal for the
analog switch (IC25).

Low :

While

“Public-address” function

is ON.

75

76

77

79

80

81

88

89–91

92

94,

95

96

97

98

99

100

XRTS

XTXD

XRXD

NTXD

NRXD

CIRQ

DIM

CENC2–

CENC0

AFCL

AMSK,

ADIN

APST

PMFM

ESDA

ESCL

PA

Pin Port

Description

number name