Icom IC-F4101D, IC-F4102D, IC-F4103D, IC-F4106D Service Manual

S-14801XZ-C1 Apr. 2011
UHF TRANSCEIVERS
This service manual describes the latest technical information for the IC-F4101D, IC-F4102D, IC-F4103D and
IC-F4106D
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than the specified voltage. This will ruin the transceiver.
DO NOT expose the transceiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when
connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100 mW) to the antenna connector. This could damage the transceiver’s front-end.
To upgrade quality, any electrical or mechanical parts and internal circuits are subject to change without notice or obligation.
MODEL VERSION
FREQUENCY
RANGE (MHz)
CHANNEL
SPACING (kHz)
IC-F4101D USA-01
400–470
6.25/12.5
IC-F4102D
EUR-01 6.25/12.5/20.0/25.0
UK-01
6.25/12.5/25.0IC-F4103D
EXP-01
EXP-02
EXP-03
EXP-07
350–400
EXP-08
AUS-01
400–470
IC-F4106D RUS-01
Be sure to include the following four points when ordering replacement parts:
1. 10-digit Icom part number
2. Component name
3. Equipment model name and unit name
4. Quantity required
<ORDER EXAMPLE>
1110003491 S.IC TA31136FNG IC-F4101D MAIN UNIT 5 pieces
8820001210 Screw 2438 screw IC-F4101D Top cover 10 pieces
Addresses are provided on the inside back cover for your convenience.
ORDERING PARTS
1. Make sure that the problem is internal before dis­assembling the transceiver.
2. DO NOT open the transceiver until the transceiver is disconnected from its power source.
3. DO NOT force any of the variable components. Turn them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the transceiver is defective.
6. DO NOT transmit power into a Standard Signal Generator or a Sweep Generator.
7. ALWAYS connect a 30 dB to 40 dB attenuator between the transceiver and a Deviation Meter or Spectrum Analyzer, when using such test equipment.
8. READ the instructions of the test equipment throughly before connecting it to the transceiver.
REPAIR NOTES
INTRODUCTION
CAUTION
Icom, Icom Inc. and the Icom logo are registered trademarks of Icom Incorporated (Japan) in Japan, the United States, the United Kingdom, Germany, France, Spain, Russia and/or other countries.
TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASSEMBLY INSTRUCTION
SECTION 4 CIRCUIT DESCRIPITON
4-1 RECEIVER CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4-2 TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4-3 FREQUENCY SYNTHESIZER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4-4 VOLTAGE DIAGRAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4-5 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
SECTION 5 ADJUSTMENT PROCEDURES
5-1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5-2 FREQUENCY ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5-3 TRANSMIT ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5-4 RECEIVE ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS
SECTION 8 BOARD LAYOUTS
SECTION 9 BLOCK DIAGRAM
SECTION 10 VOLTAGE DIAGRAM
1 - 1
SECTION 1. SPECIFICATIONS
M GENERAL
• Frequency range : 400–470 MHz [USA-01], [EUR-01], [UK-01], [EXP-01], [EXP-02], [EXP-03], [AUS-01], [RUS-01]
350–400 MHz [EXP-07], [EXP-08]
• Number of conventional channels : 16
• Type of emission : Wide 16K0F3E (30.0 kHz) Except [USA], [EUR], [UK]
16K0F3E (25.0 KHz) Except [USA] Middle 14K0F3E (20.0 kHz) [EUR], [UK] only Narrow 11K0F3E (15.0 kHz) Except [EUR], [UK] 8K50F3E (12.5 kHz) Digital 4K00F1E, D (6.25 kHz)
• Antenna impedance : 50 Ω (nominal)
• Operating temperature range : –30˚C to +60˚C; –22˚F to +140˚F Except [EUR], [UK]
–25˚C to +55˚C [EUR], [UK]
• Power supply voltage : Specifi ed Icom's battery packs only (7.5 V DC; negative ground)
• Current drain (approximately) : Receiving 100 mA (in digital mode, stand-by)
400 mA (max. audio, with the internal speaker) Transmitting 1.3 A (4 W)
• Dimensions
(projections not included)
: 58.0 (W)×111.0 (H)×36.5 (D) mm; 2.3 (W)×4.4 (H)×1.4 (D) in. (with BP-265)
• Weight (approximately) : 150 g; 5.3 oz.
310 g; 10.9 oz. (including MB-124, BP-265, FA-SC57U)
M TRANSMITTER
• Output power : 4 W
• Modulation : Variable reactance frequency modulation
• Maximum frequency deviation : Narrow ±2.5 kHz
Middle ±4.0 kHz [EUR], [UK] only Wide ±5.0 kHz Except [USA]
• Frequency stability : ±1.0 ppm
• Spurious emissions : 70 dB min. Except [EUR], [UK]
0.25 µW (
1 GHz)
[EUR], [UK]
1.00 µW (
>
1 GHz)
[EUR], [UK]
• Adjacent channel power : Narrow 60 dB min., 70 dB typ.
Middle 70 dB min., [EUR], [UK] only Wide 70 dB min., 74 dB typ. Except [USA] Digital 60 dB min., 66 dB typ.
• Audio harmonic distortion : 1.0% typ. (at AF 1 kHz, 40% deviation)
• FSK error : 5% max.
• FM hum and Noise (Except [EUR], [UK])
(without CCITT Filter)
: Narrow 34 dB min., 44 dB typ.
Wide 40 dB min., 50 dB typ. Except [USA]
• Rasidual modulation ([EUR], [UK] only)
(with CCITT Filter)
: Narrow 40 dB min.
Middle 43 dB min. Wide 45 dB min.
• Limitting charact of modulator : 60–100% of max. deviation
• Input impedance (MIC) : 2.2 k
Ω
1 - 2
M RECEIVER
• Sensitivity : 0.24 µV typ. at 12 dB SINAD Except [EUR], [UK]
–4 dBµV (EMF) typ. at 20 dB SINAD [EUR], [UK] –8 dBµV (EMF) typ. at 5% BER [Digital mode]
• Squelch sensitivity (at threshold) : 0.20 µV typ. Except [EUR], [UK]
–8 dBµV (EMF) typ. [EUR], [UK]
• Intermediate frequency : 1st IF; 46.35 MHz, 2nd IF; 450 kHz
• Adjacent channel selectivity : Narrow 60 dB min., 67 dB typ.
Middle 70 dB min. [EUR], [UK] only Wide 70 dB min., 74 dB typ. Except [USA] Digital 50 dB min., 58 dB typ.
• Spurious response : 70 dB min., 80 dB typ.
• Intermodulation : Narrow 70 dB min., 75 dB typ. Except [EUR], [UK]
Wide 70 dB min., 75 dB typ. Except [EUR], [UK], [USA] Digital 65 dB min., 70 dB typ. Except [EUR], [UK] 65 dB min. [EUR], [UK]
• FM hum and Noise (Except [EUR], [UK])
(without CCITT Filter)
: Narrow 34 dB min., 42 dB typ.
Wide 40 dB min., 47 dB typ. Except [USA]
• FM hum and Noise ([EUR], [UK])
(with CCITT Filter)
: Narrow 40 dB min.
Middle 43 dB min. Wide 45 dB min.
• Audio output power : 0.8 W typ. at 5% distorsion with a12 Ω load (internal speaker)
0.4 W typ. at 5% distorsion With an 8 Ω (external speaker)
• Audio output impedance : 8
Ω
Measurements made in accordance with TIA-603, EN 300 086 or EN 301 166.
All stated specifi cations are subject to change without notice or obligation.
2 - 1
SECTION 2. INSIDE VIEWS
• MAIN-A/MAIN-C UNIT (TOP VIEW)
VCO
5 V REGULATOR (IC54)
PLL CIRCUIT
APC AMP
(IC1)
TCXO
(X2)
3.3 V DC-DC CONVERTER (IC65)
MIC AMP
(IC64)
2ND IF FILTER (For wide) (FI3)
1ST IF FILTER (FI2)
DISCRIMINATOR (X1)
2ND IF FILTER (For narrow) (FI4)
2ND IF FILTER (For digital) (FI5)
AF AMP (IC21)
AF AMP (IC58)
2 - 2
• MAIN-A/MAIN-C UNIT (BOTTOM VIEW)
TX POWER AMP (Q1)
BUFFER
(Q28)
PLL LOCK VOLTAGE SW
(IC6)
CLOCK AMP
(IC905)
2ND IF AMP (For digital)
(IC5)
AF POWER AMP SW
(Q64)
DRIVE AMP (Q2)
PRE-DRIVE AMP (Q3)
PRE AMP (Q4)
RF AMP (Q22)
RF AMP GATE BIAS CONTROL (Q21)
AF AMP
(IC55)
IF DEMODULATOR IC
(IC3)
BUFFER
(Q17)
1ST IF FILTER
(FI1)
R5 LINE REGULATOR
(Q72)
RIPPLE FILTER (Q15)
1ST IF MIXER
(Q23)
AF POWER AMP
CONTROLLER
(Q63)
LINEAR CODEC
(IC902)
LINEAR CODEC/DSP CLOCK
(X900)
D/A CONVERTER (IC57)
LPF/BUFFER/VOX AMP (IC60)
CPU (IC51)
PLL BUFFER (Q9)
VCC LINE SW (Q92)
3 - 1
SECTION 3. DISASSEMBLY INSTRUCTION
3 - 1
BE CAREFUL to not pull out the speaker wire when separating the CHASSIS and the FRONT PANEL.
For easy separation of the CHASSIS
Use a suction lifter to lift the bottom of the CHASSIS up.
1. REMOVING THE CHASSIS
1) Remove the ANT connector nut and 2 knobs.
2. REMOVING THE MAIN UNIT
1) Remove the 9 screws and the side plate from the MAIN UNIT.
2) Unsolder the 2 points shown, and then remove the MAIN UNIT.
2) Remove 2 screws from the bottom of the CHASSIS.
3) Lift the bottom of the CHASSIS up in the direction of the arrow.
4)
CAREFULLY lift the chassis out of the FRONT PANEL and turn it over in order to unplug the speaker wire.
(Continued on the right above)
5) Remove the seals and nuts from the CHASSIS.
ANT CONNECTOR NUT
KNOB
FRONT PANEL
Remove with;
“ICOM Driver (K)”
(8960000110)
FRONT PANEL
CHASSIS
SCREW×2
SPEAKER
WIRE
CHASSIS
FRONT PANEL
TOP SEAL
NUT×2
SIDE SEAL
CHASSIS
Remove with;
“ICOM Driver (AG)”
(8960000560)
UNSOLDER
Solder remover
CHASSIS
SCREW×9
PCB
MAIN UNIT
SIDE PLATE
Suction lifter
Suction lifter
• Part name : EA950R-2
• Manufacture : ESCO CO.LTD
4 - 1
SECTION 4. CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS
RF CIRCUITS
The RX signal from the antenna is passed through the LPF and antenna SW (D3, D22), then filtered by the 2-staged tuned BPF (D24 and D26) to eliminate unwanted out-of­band signals. The filtered RX signal is amplified by the RF AMP (Q22), and filtered by another 2-staged tuned BPF (D28) to obtain a good image response, then applied to the 1st IF circuits.
The BPFs are tuned to the RX frequency by applying ad­equate tuning voltages: “T1” and “T2” to the variable capaci­tors.
1ST IF CIRCUITS
The RX signal from the RF circuits is applied to the 1st IF mixer (Q23) and mixed with the 1st LO signal from the RX VCO, resulting in the 46.35 MHz 1st IF signal. The 1st IF sig­nal is passed through the IF SWs (D31–D34) and the crystal fi lter (FI1: analog mode, FI2: digital mode) to be fi ltered, am­plified by the 1st IF AMP (Q24), then applied to the 2nd IF circuits.
2ND IF AND DEMODULATOR CIRCUITS
The signal from the 1st IF circuits is applied to the IF demod­ulator IC (IC3) which contains the 2nd IF mixer, 2nd IF AMP, FM detector, squelch circuit and AF AMP in its package.
The 1st IF signal is applied to the 2nd IF mixer and mixed with the 2nd LO signal resulting in the 450 kHz 2nd IF signal.
The 2nd LO signal is generated by tripling the 15.3 MHz reference frequency signal generated by the reference fre­quency oscillator (TCXO; X2).
• WHILE OPERATING IN THE ANALOG MODE
The 2nd IF signal is filtered by the 2nd IF filter (FI3: wide/ middle mode) or fi lters (FI3 and FI4: narrow) to eliminate un­wanted signals. It is amplifi ed by the 2nd IF AMP, and then demodulated by the detector circuit, which employs the dis­criminator (X1) as the phase shifter.
The demodulated AF signal is amplified by the AF AMP (IC21), and then applied to the linear codec (IC902) through the fi lter SW (Q901). The fi lter SW toggles the frequency re­sponse of the AF fi lter (R904, R908, C924), according to the type of reception; Wide, Mid or Narrow.
The AF signal is converted into a digital audio signal by the linear codec (IC902), processed by the DSP (IC903), and then decoded into an analog audio signal.
• WHILE OPERATING IN THE DIGITAL MODE
The 2nd IF signal is fi ltered by the 2nd IF fi lters (FI3 and FI4) to eliminate unwanted signals and applied to the IF AMP (IC5) through the buffer (Q28). The amplifi ed 2nd IF signal is passed through the ceramic fi lter (FI5), and then directly ap­plied to the DSP (IC903).
The 2nd IF signal is demodulated by the DSP (IC903), and then applied to the linear codec (IC902) to be decoded into an analog audio signal.
The AF signal is applied to the RX AF circuits.
LPF
ANT
SW
D1,D22
RF AMP
Q22
BPF
D28 D24,D26
BPF
T2
T1
From the TX circuits
To the 1st IF circuits
ANT
LO SW
D5,D6
D31,D32D33,D34
Q23
BPF
XTAL
FI1
IF AMP
Q24
BUFF
Q8
BUFF
Q10
ATT
IF SW
IF SW
RX VCO
To the TX circuits
From the RF circuits
2nd IF circuits
46.35MHz
BPF
XTAL
FI2
46.35MHz 1st IF mixer
PLL
IC
IC2
X3
Q26
BPF
X2
TCXO
W/N
SW
D38,D39
X1
Discriminator
BPF
CERAMIC
FI3
BPF
CERAMIC
FI4
W/N SW
D36,D37
D/A
converter
IF IC
From the 1st IF
circuits
(Analog path)
To the RX AF circuit
(Digitalpath)
IC3
15.3MHz
45.9MHz
DISC
SQIN
IC57
450kHz
450kHz
NOIS
CERAMIC
BPF
FI5
DIF
BUFF
IC5
BUFF
Q28
A/D
IC901
FILTER
SW
Q901
DSP
LINEAR
DISC
CODEC
IC902
IC903
DAFO
AF
FILTER
R904,R908,C924
• 1ST IF CIRCUITS
• 2ND IF AND DEMODULATOR CIRCUITS
• RF CIRCUITS
4 - 2
RX AF CIRCUITS
The demodulated AF signal from the linear codec (IC902) is passed through the LPF (IC60C), and then adjusted in level by the D/A converter (IC57). The level-adjusted AF signal is then amplifi ed by AF AMPs (IC58 and IC55).
The amplifi ed AF signal is applied to the internal or external speaker.
SQUELCH CIRCUITS (Analog mode only)
The squelch circuit cuts off the AF output signals when no RF signals are received. Detecting noise components in the demodulated AF signals, the squelch circuit stops audio sig­nals being emitted.
A portion of demodulated AF signal from the IF IC (IC3) is passed through the D/A converter (IC57) for level (=thresh­old) adjustment. The level-adjusted AF signals are passed through the noise filter (IC3, pins 7, 8 and R139–R142, C241–C243) to fi lter the noise components (approx. 30 kHz signals) only. The noise components are rectified, resulting in DC voltage corresponding to the noise level.
If the noise level is higher than the preset one, the internal comparator set the “NOISE” signal to the CPU to “High”, then the CPU turns the “AFON” signal which controlls the AF power AMP (IC55) to “Low,” to inactivate it.
• RX AF CIRCUITS
• SQUELCH CIRCUITS
AF
AM P
AF
AMP
IC55 TPA0211DGN
J52
SP1
AF
AM P
J53
Int.speaker
Ext.speaker
1 2
LPF
IC60C
From the linear codec
IC58
AFON
AFO
DAFO
D/A
converter
IC57
DAC
Noise AMP
Noise filter
From IF IC
(IC3, Pin16)
To RX AF circuits
Noise
detector
Com-
parator
NOISE SQUELCH DIAGRAM
“NOIS”
IC57
IC3
14
8
7
13
15
4-2 TRANSMITTER CIRCUITS
TX AF CIRCUITS
The audio signal from the internal or external microphone (MIC signal) is passed through the MIC gain SW (IC62), and then applied to the MIC AMP (IC64).
• WHILE OPERATING IN THE ANALOG MODE
The amplifi ed MIC signal is passed through the HPF (IC63A), which attenuates frequencies 300 Hz and below, and then applied to the limiter AMP (IC60A), through the mute SW (Q66).
The amplitude-limited MIC signal is applied to the lin-
ear codec (IC902), through the MIC line SW (IC66).
The MIC signal is converted into a digital audio signal by the linear codec (IC902), processed by the DSP (IC903), and then converted into an analog baseband signal (modulation signal).
• WHILE OPERATING IN THE DIGITAL MODE
The amplifi ed MIC signal is applied to the ALC (IC63B) which keeps the signal level fi xed.
The level-adjusted MIC signal is
applied to the linear codec
(IC902) through the MIC line SW (IC66).
The MIC signal is converted into a digital audio signal by the linear codec (IC902), processed by the DSP (IC903), and then converted into the digital baseband signal (modulation signal).
The signal from the linear codec (IC902) is passed through the LPF (IC60B), and then applied to the D/A converter (IC57)
which adjusts its level (=deviation)
. The level-adjusted
modulation signal is applied to the modulation circuit.
• TX AF CIRCUITS
MC51
[Ext. MIC]
[Int. MIC]
J51
MIC
GAIN
SW
IC62
AMP
IC64
ALC AMP
IC63B
HPF
IC63A
LIMIT AMP
IC60A
MIC
LINE
IC66
SW
MUTE
SW
Q66
DMI
To the modulation circuit
DSP
LINEAR
CODEC
IC902
IC903
LPF
IC60B
MOD DMO
D/A
IC57
4 - 3
MODULATION CIRCUIT
The modulation signal from the TX AF circuits is applied to D15 of the TX VCO (Q14, D14–D16) to modulate it (FM for the analog mode, 4FSK for the digital mode). The modulated signal from the TX VCO is buffer-amplified by two buffers (Q8, Q10), and applied to the TX AMP circuits through the LO SW (D5).
TX AMPLIFIERS
The buffer amplifi ed signal from the LO SW (D5) is sequen­tially amplified by the pre-AMP (Q4), pre-drive AMP (Q3), drive AMP (Q2), and power AMP (Q1), to obtain TX power. The amplifi ed TX signal is passed through the antenna SW (D3, D22) and the LPF, which eliminates harmonics, and then fed to the antenna.
APC CIRCUITS
D1 and D2 rectify a portion of the TX signal to direct voltage, and the APC AMP (IC1) compares the voltage and the TX power control reference voltage, “T1.” The resulting voltage controls the gain of the power and drive AMPs to keep the TX power constant.
• FREQUENCY SYNTHESIZER CIRCUITS
• TX AMPLIFIERS AND APC CIRCUITS
5-4 VOLTAGE DIAGRAMS
LO SW
D5
Q14, D14,D16,D17
MODULATION
FM:Analog 4-FSK: Digital
D15
BUFF
Q8
BUFF
Q10
TX VCO
From the TX AF circuits
To the TX AMP circuits
MOD
LPF
PWR
DET
D1,D2
MUTE
SW
Q6
ANT SW
D1,D22
PWR AMP
Q1
APC AMP
IC1
DRIVE AMP
Q2
AMP
PRE
Q4
DRIVE
PRE
Q3
T1
TMUT
ANT
From the
TX VCO
To the RX circuits
• MODULATION CIRCUIT
LPF
LPF
LO SW
D5,D6
Q13,D12
Q14,D16
FILTER
LOOP
PLL
IC
SO,SCL,PLST
IC4
X3
Q26
Q23
To the TX AMPs
BPF
BUFF
Q8
BUFF
Q10
BUFF
Q9
X2
TCXO
LV
ADJ
D14
LV
ADJ
D11
BUFF
IC60
IF IC
RX VCO
TX VCO
IC3
REF
BAL
15.3MHz
45.9MHz
1st IF mixer
LV
LVA
S5 REG
Q71
,Q86
REG
R5
Q72
,Q87
REG
T5
Q73
,Q88
F51
R1(CHASSIS)
12
BT1
REG
+5V
IC54
DC-DC
1.6V
IC900
DC-DC
3.3V
IC65
REG
+3.3V
Q90
,Q91
Q92, Q93, D59
POWER
SW
LINE
FILTER
LINE FILTER
LINE FILTER
LINE
FILTER
VCC
+5V
T5V
Transmit circuits
Receive circuits
TX/RX common circuits
TX/RX common circuits
Logic circuits
R5V
S5V
TXC
RXC
S5C
VCC CPUV
CVDD_1.6 V
3.3V_VD D
+3.3V
+3.3V_A
+3.3V
PWON
POSWH
DVDD_3.3V
DSP
DSP flash
Liner codec
DSP reference voltage
CPUV
4-3
FREQUENCY SYNTHESIZER CIRCUITS
The RX VCO is composed of Q13, and D11, D12. The VCO output signal is buffer-amplifi ed by two buffers (Q8 and Q10) and applied to the 1st IF mixer, through the LO SW (D6) and the LPF (L18, C208, C209).
The TX VCO is composed of Q14 and D14–D17. The VCO output signal is buffer-amplifi ed by two buffers (Q8 and Q10) and applied to the pre-AMP (Q4), through the LO SW (D5) and the LPF.
A portion of signal generated by each VCO is fed back to the PLL IC (IC4, pin 17) through the buffer (Q9) and the LPF (L46, C167, C168).
The applied VCO output signal is divided and phase-com­pared with a 15.3 MHz reference frequency signal from the TCXO (X2), which is also divided. The resulting signal is output from the PLL IC (IC4), and DC-converted by the loop fi lter, and then applied to the VCO as the lock voltage.
When the oscillation frequency drifts, its phase changes from that of the reference frequency, causing a lock voltage change to compensate for the drift in the VCO oscillating fre­quency.
4 - 4
4-5 PORT ALLOCATIONS
• CPU (IC51)
• D/A CONVERTER (IC57)
PIN No.
LINE
NAME
DESCRIPTION
3 BAL DTCS balance adjustment.
4 AFVO AF volume adjustment.
12 TENC Outputs CTCSS deviation adjustment.
15 SQLC Squelch threshold setting.
16 T1
During RX: Outputs BPF tuning voltage. During TX: Outputs TX power reference
voltage.
19 T2 Outputs BPF tuning voltage.
20 REF Outputs reference frequency adjust voltage.
23 LVA Outputs additional lock voltage adjustment.
24 MOD Max. deviation/AF volume adjustment.
BALL
No.
LINE
NAME
DESCRIPTION
I/O
A5 RXC
Power supply switching control. H= During receive or stand-by.
O
A6 RMUTE
RX AF mute switch control. L= During the squelch circuit is
activated.
O
A7 DMOSI Serial data to the DSP (IC903). O
A15 PWON
Power supply switching control. H= The transceiver's power is ON.
O
B12 NOIS
Noise level detect. H= Squelch close.
I
B15 AFON
AF power AMP control. H= AF power AMP (IC55) is activated.
O
C1, C2CBI2,
CBI0
[ROTARY SELECTOR] input. I
C5 TXC
Power supply switching control. H= While transmitting.
O
C8 ESDA EEPROM (IC52) serial data. I/O
C13 POSW [POWER] input. I
C14 ADS
1st IF filters (FI1 and FI2) switching control. L= During digital mode.
O
C15 NWC
Receive bandwidth switching. L= During narrow mode.
O
D2, D3CBI3,
CBI1
[ROTARY SELECTOR] input. I
D6 DSCK DSP (IC903) clock. O D8 ESCL EEPROM (IC52) clock. O
D13 DPDN
DSP (IC903) power control. H= DSP is inactivated.
O
D14 DRES
DSP (IC903) reset. L= Reset.
O
D15 CSFT
Clock frequency shift. H= Clock frequency is shifted.
O
E13 RES CPU reset. I
H1 SIDE1
[UPPER] key input. L= Pushed.
I
H2 SIDE2
[LOWER] key input. L= Pushed.
I
J1 IPTT
Internal [PTT] input. L= Pushed.
I
J2 XPTT
External PTT input. H= An external PTT is pushed.
I
L1, L2
MCG0,
MCG1
MIC gain control. O
L12 TLED
Busy LED (Red) control. L= LED lights
. (While transmitting)
O
L13 RLED
Busy LED (Green) control. L= LED lights. (While receiving a signal)
O
L14 SSO Common serial data. O L15 SCK Common clock. O
M1 TMUT
Transmission mute. L= TX inhibit.
O
M2 ATX
Automatic TX control for VOX mode. H= While MIC audio from the
connected headset is detected.
O
M8 BEEP Beep audio. (Square waves) O
M11 MDET External connection detect. I
M14 DAST
D/A converter (IC57) strobe. H= Load enable.
O
BALL
No.
LINE
NAME
DESCRIPTION
I/O
N11 VOXV Microphone input sensing voltage. I N12 BATV Battery voltage sensing. I N14 DMISO DSP (IC903) serial data. O
P4 PLSW
PLL lock up time control. L= Fast lock up.
O
P10 TEMP Temperature sensing voltage. I P11 RSSI RSSI sensing voltage. I P12 AFVI [VOLUME CONTROL] input. I P15 DSS DSP (IC903) chip select. O
R3 S5C
Power supply line "S5C" switching control. H= Supplying current to the TX/RX
common circuits.
O
R4 PLST PLL strobe. O
R10 LVIN Lock voltage input. I
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