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IC-446S
User Manual
32 pgs734.14 Kb0
Service Manual
27 pgs968.76 Kb0
Table of contents
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Icom IC-446S Service Manual

SERVICE MANUAL
PMR446 FM TRANSCEIVER

TABLE OF CONTENTS

SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASEMBLY INSTRUCTION
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4-2 TRANSMITER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4-3 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4-4 POWER SUPPLY CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4-5 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
SECTION 5 ADJUSTMENT PROCEDURES
5-1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5-2 PLL AND TRANSMITTER ADJUSTMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
5-3 RECEIVER ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS AND DISASSEMBLY
SECTION 8 SEMI-CONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
9-1 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
9-2 RF UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
SECTION 10 BLOCK DIAGRAM
SECTION 11 VOLTAGE DIAGRAM
11-1 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
11-2 RF UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2
All stated specifications are subject to change without notice or obligation.
‘‘
GENERAL
Number of channels : 8 ch Type of emission : 8K50F3E Frequency stability : ±2.5 kHz Frequency resolution : 12.5 kHz Power supply requirements : 3
× AA(R6) dry, alkaline;
(negative ground) or optional BP-202 Current drain : Less than 500 mA Operating temperature range : –20˚C to +55˚C Number of CTCSS frequency: 38 (67.0–250.3 Hz) Dimensions (mm) : 55.5(W)
×102.5(H)×26.5(D)
(proj. not included) Weight (included 3 cells) : 180 g
‘‘
TRNSMITTER
Output power : 500 mW Modulation system : Variable reactance
frequency modulation Max. freqequency deviation : ±2.5 kHz Spurious emissions : Less than 0.25 µW Adjacent channel power : More than 60 dB External mic.connector : 3-conductor
2.5(d) mm/2.2 kΩ
‘‘
RECEIVER
Receiving system : Double conversion
superheterodyne Intermediate frequency : 1st 21.7 MHz
2nd 450 kHz Sensitivity (12 dB SINAD) :
Less than 0.25 µV; –12 dBµV Adjcent chnnel selectivity : 55 dB Spurious response : 65 dB Intermoduration : 60 dB Audio output power : 100 mW at 10% distortion
(at 4.5 V DC) with an 8 Ω load External SP connector : 2-conductor
3.5 (d) mm (
1
⁄8")/8 Ω
‘‘
CHANNEL FREQUENCY LIST
‘‘
CTCSS FREQUENCY LIST

SECTION 1 SPECIFICATIONS

1 - 1
Channel Frequency Channel Frequency
No. (MHz) No. (MHz)
1 2 3 4
446.00625
446.01875
446.03125
446.04375
5 6 7 8
446.05625
446.06875
446.08125
446.09375
Channel Frequency Channel Frequency
No. (Hz) No. (Hz)
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20
67.0
71.9
74.4
77.0
79.7
82.5
85.4
88.5
91.5
94.8
97.4
100.0
103.5
107.2
110.9
114.8
118.8
123.0
127.3
131.8
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
---
136.5
141.3
146.2
151.4
156.7
162.2
167.9
173.8
179.9
186.2
192.8
203.5
210.7
218.1
225.7
233.6
241.8
250.3 OFF

SECTION 2 INSIDE VIEWS

•
MAIN UNIT
2 - 1
•
RF UNIT
T+3 Current amplifier Q27: 2SC4081 Q28: 2SB798 Q101: UMZ1N D5: 1SS355
R+3 Current amplifier (Q18: 2SA1586)
AF amplifier (IC9: NJM2070M)
EEPROM (IC3: AT24C02N)
CPU (IC1: µPD753036GK)
+3 Regurator (IC6: S-81230SG)
TOP VIEW BOTT OM VIEW
1st mixer (Q2: 3SK284)
Reference oscilletor (X1: CR-669 21.25MHz)
PLL IC (IC1: µPD3140GS)
TOP VIEW BOTT OM VIEW
VCO circuit
FM IF IC (IC2: TA31136FN)
1st IF filter (FI2: FL-297)
1st IF amplifier (Q1: 2SC4215)
2nd IF filter (FI3: CFWN450G)
RF amplifier (Q3: 2SC4226)
SECTION 3 DISASEMBLY INSTRUCTION
3 - 1
A
B
B
MAIN unit
RF unit
C
D
E
G
F
•
REMOVING THE REAR PANEL
1 Unscrew 1 screw A , and 4 screws B. 2 Remove the rear panel in the direction of the arrow.
•
REMOVING THE RF UNIT
1 Remove 1 knob C, and unscrew 1 nut D. 2 Then remove the RF unit.
•
REMOVING THE MAIN UNIT
1 Unscrew 2 screws, E. 2 Remove the PTT rubber, F. 3 Unsolder 2 points, G, and remove the MAIN unit.
4 - 1

SECTION 4 CIRCUIT DESCRIPTION

4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT (RF UNIT)
Received signals from the antenna connector are passed through the low-pass filter (L5, L6, C8–C12). The filtered sig­nals are applied to the λ⁄4 type antenna switching circuit (D101, D102, L4, L206, C209, C210). The passed signals are then applied to the RF amplifier circuit.
The antenna switching circuit functions as a low-pass filter while receiving. However, its impedance becomes very high while D101 and D102 are turned ON (while transmitting). Thus transmit signals are blocked from entering the receiv­er circuits. The passed signals are then applied to the RF amplifier circuit.
4-1-2 RF CIRCUIT (RF UNIT)
The RF circuit amplifies signals within the range of frequen­cy coverage and filters out-of-band signals.
The signals from the antenna switching circuit are amplified at the RF amplifier (Q3) and passed through the bandpass filter (FI1) to suppress out-of-band signals. The filtered sig­nals are applied to the 1st mixer circuit.
4-1-3 1ST MIXER AND 1ST IF CIRCUITS (RF UNIT)
The 1st mixer circuit converts the received signals to a fixed frequency of the 1st IF signal with a PLL output frequency. By changing the PLL frequency, only desired signals will pass through a crystal filter at the next stage of the 1st mixer.
The signals from the bandpass filter (FI1) are mixed at the 1st mixer circuit (Q2) with a 1st LO signal coming from the VCO circuit to produce a 21.7 MHz 1st IF signal.
The 1st IF signal is applied to a crystal filter (FI2) to sup­press out-of-band signals. The filtered 1st IF signal is applied to the IF amplifier (Q1), then applied to the 2nd mixer circuit.
4-1-4 2ND MIXER AND DEMODULATOR CIRCUITS
(RF UNIT)
The 2nd mixer circuit converts the 1st IF signal into a 2nd IF signal. Adouble conversion superheterodyne system (which converts receive signals twice) improves the image rejection ratio and obtains stable receiver gain.
The 1st IF signal from the IF amplifier (Q1) is applied to the 2nd mixer section in the FM IF IC (IC2, pin 16), and is mixed with the 2nd LO signal to be converted into a 450 kHz 2nd IF signal.
The FM IF IC contains a 2nd mixer, quadrature detector, noise amplifier and a limiter amplifier, etc. The PLL refer­ence oscillator (X1) is used for the 2nd LO signal via the PLL IC (IC1, pins 16, 17), and is applied to pin 1 of the FM IF IC (IC2).
The mixed 2nd IF signal is output from pin 3 (IC2) and passed through the ceramic bandpass filter (FI3) to remove unwanted heterodyne frequencies. It is then amplified at the limiter amplifier section (IC2, pin 5) and applied to the quad­rature detector section (IC2, pins 10, 11) to demodulate the 2nd IF signal into AF signals.
4-1-5 AF CIRCUIT (RF AND MAIN UNITS)
AF signals from the FM IF IC (RF unit; IC2, pin 9) are passed through the high-pass filter (RF unit; Q15, Q16) to remove CTCSS signals then applied to the MAIN unit via J2 (pin 10) as the “VOL” signal.
The “VOL” signal (AF signals) from the RF unit is applied to the [VOL] control (MAIN unit; R58) to control the audio level via the volume mute switch (Q23). The level controlled AF signals are applied to the AF power amplifier (IC9, pin 2) to drive an internal speaker (SP1) via the [SP] jack (J1).
• 2nd IF and demodulator circuits
Mixer
16
Limiter amp.
2nd IF filter 450 kHz
PLL IC
IC1
X1
21.25 MHz
X2
(21.25 MHz)
RSSI
IC2 TA31136FN
14
1st IF (21.7 MHz) from Q1
"SQL" signal to the CPU pin 59
11109
87 5 3
AF signal "AF"
R+3
1
17
16
Active filter
FI3
Noise
detector
FM
detector
4 - 2
4-1-6 SQUELCH CIRCUIT (RF AND MAIN UNITS)
• NOISE SQUELCH
The noise squelch circuit cuts out AF signals when no RF signals are received. By detecting noise components in the AF signals, the squelch circuit switches the AF mute switch.
A portion of the AF signals from the FM IF IC (RF unit; IC2, pin 9) are applied to the active filter section (RF unit; IC2, pin 8). The active filter section amplifies and filters noise components. The filtered signals are applied to the noise detector section and output from pin 14 as the “SQL” signal.
The “SQL” signal from IC2 (pin14) is applied to the CPU (MAIN unit; IC1, pin 59). The CPU analyzes the noise con­dition and outputs the “RMUT” and “AFON” signals to toggle the volume mute (MAIN unit; Q23) and AF mute (MAIN unit; Q5, Q10, Q11) switches.
• TONE SQUELCH
The tone squelch circuit detects AF signals and opens the squelch only when receiving signal containing a matching subaudible tone (CTCSS). When tone squelch is in use, and a signal with a mismatched or no subaudible tone is received, the tone squelch circuit mutes the AF signals even when noise squelch is open.
A portion of the AF signals from the FM IF IC (RF unit; IC2, pin 9) passes through the tone low-pass filter (MAIN unit; Q7, Q12) to remove AF (voice) signals and is applied to the CTCSS decoder inside the CPU (MAIN unit; IC1, pin 58) via the “CTCIN” line to control the volume mute and AF mute switches.
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT
(MAIN UNIT)
The microphone amplifier circuit amplifies audio signals with pre-emphasis characteristics from the microphone to a level needed for the modulation circuit.
AF signals from the internal/external microphone are applied to the microphone amplifier circuit (IC2b) via the microphone mute switch (Q6) and pre-emphasis circuit (R7, C24). The amplified signals are passed through the splatter filter (IC2a) and applied to the modulation circuit in the RF unit via J4 (pin 6) as the MOD signal.
4-2-2 MODULATION CIRCUIT (RF UNIT)
The modulation circuit modulates the VCO oscillating signal (RF signal) using the microphone AF signals.
The filtered audio signals from the MAIN unit are passed through the deviation adjustment pot (R50), and are then applied to the modulation circuit (D4, D5) to modulate trans­mit signals at the VCO circuit (Q6).
The modulated signal is applied to the drive amplifier circuit.
4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS
(RF UNIT)
The amplifier circuit amplifies the VCO oscillating signal to the output power level.
The signal from the buffer amplifiers (Q7, Q203) is passed through the Tx/Rx switching circuit (D2), and are amplified at the pre-drive (Q8) and drive (Q201) amplifiers. The amplified signal is power-amplified at the power amplifier (Q202) to obtain 500 mW of RF power
The amplified transmit signal is passed through the antenna switching circuit (D7) and low-pass filter, and is then applied to the antenna.
4-3 PLL CIRCUITS (RF UNIT)
A PLL circuit provides stable oscillation of the transmit fre­quency and receive 1st LO frequency. The PLL output com­pares the phase of the divided VCO frequency to the refer­ence frequency. The PLL output frequency is controlled by the divided ratio (N-data) of a programmable divider.
The PLL circuit consists of the VCO circuit (Q6). An oscillat­ed signal from the VCO passes through the buffer amplifier (Q7), and is then applied to the PLL IC (IC1, pin19) and prescaled in the PLL IC based on the divided ratio (N-data).
The reference signal is generated at the reference oscillator (X1) and is applied to the PLL IC. The PLL IC detects the out-of-step phase using the reference frequency and out­puts it from pin 13 (IC1). The output signal is passed through the loop filter (R45, C68) and is then applied to the VCO cir­cuit as the lock voltage.
If the oscillated signal drifts, its phase changes from that of the reference frequency, causing a lock voltage change to compensate for the drift in the oscillated frequency.
• PLL circuit
Shift register
Prescaler
Phase detector
Loop
filter
Programmable counter
Programmable divider
X1
21.25 MHz to the FM IF IC
VCO
Buffer
Q7
3 4 5
STB
IC1 (PLL IC)
CK DATA
to transmitter circuit
to 1st mixer circuit
D2
D1
17
16
14
19
Q6, D4, D5
Buffer
Q203
4 - 3
4-4 POWER SUPPLY CIRCUITS
VOLTAGE LINE
4-5 PORT ALLOCATIONS
4-5-1 CPU (MAIN unit; IC1)
LINE
BATT
3V
+3V
R+3
T+3
DESCRIPTION
The voltage from the connected battery cells. Common 3 V converted from the BATT line at
the 3V regulator circuit (IC6). The circuit outputs the voltage regardless of the power ON/OFF condition.
Common 3 V converted from the BATT line at the +3V regulator circuit (Q25, D4).
Receive 3 V cotrolled by the R+3 regulator circuit (Q18) using the “RXV” signal from CPU (IC1).
Transmit 3 V converted from the BATT line at the T+3 regulator circuit (Q27, Q28, Q101, D5) using the “TXV” signal coming from CPU (IC1).
Outputs data signals to the PLL IC (RF unit; IC1).
Outputs strobe signals for the PLL IC (RF unit; IC1).
Outputs control signal for the +3V reg­ulator circuit (MAIN unit; Q25, D4).
Output port for the CTCSS signals. Outputs control signal for the micro-
phone amplifier (IC2).
Low : While microphone amplifier is
ON.
Input port for the CTCSS decode sig­nals.
Input port for squelch level signal. Input ports for the control signal from
the external remote microphone. Input port from the connected battery
pack for low battery indication. Input port for the RSSI signal from the
FM IF IC (RF unit; IC2) to detect receiv­ing signal strength level.
Outputs clock signal to the EEPROM (IC3).
Outputs data signals to the EEPROM (IC3).
Output port for power save function, applied to VCO regurator circuit (RF unit; Q13, Q14, D8, D9).
Outputs the R+3 regulator control sig­nal (Q25, D4).
Outputs the T+3 regulator control sig­nal (Q27, Q28, Q101, D5).
Outputs control signal for LCD back­light.
Low : While LCD backlight is ON.
Outputs internal microphone control signal.
High : While internal PTT switch is
pushed.
Outputs MIC mute signal for RING function.
High : While RING signals are out-
put, etc.
51
52
53
54–56
57
58 59
60
61
62
73
74
75
76
77
78
79
80
PLLDA
PLLST
POWER
CTCO0–
CTCO2
TXMOD
CTCIN
SQLIN
REMIN
BATIN
SENIN
EEPCK
EEPDA
PSC
RXV
TXV
LAMPC
MICSW
MMUTE
Pin Port
Description
number name
Outputs VCO oscillation frequency control signal for Tx/Rx.
Low : While transmitting
Input port for the PTT switch from the external mic jack (MAIN unit; J1).
Low : External PTT switch is ON.
Input port for the internal PTT switch.
Low : While PTT switch is pushed. Input port for the [DOWN] switch. Input port for the [UP] switch. Input port for the [MODE] switch. Input port for the POWER switch.
Low : While POWER switch is
pushed. Outputs beep audio signal. Outputs volume mute switch (Q23)
control signal.
High : While squelched
Outputs control signal for the AF ampli­fier regulator circuit (Q5, Q10, Q11).
High: When squelch is open.
Outputs clock signal to the PLL IC (RF unit; IC1).
4
31
34 35
36 37
38
46
48
49
50
SHIFT
PTT2
PTT1
DOWN
UP
MODE
POWSW
BEEP
RMUTE
AFON
PLLCK
Pin Port
Description
number name
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