Before using this information and the product it supports, be sure to read the general information under
Appendix B, “Notices and Trademarks” on page 43.
First Edition (August 1996)
The following paragraph does not apply to the United Kingdom or any country where such provisions are inconsistent with
local law: INTERNATIONAL BUSINESS MACHINES CORPORATION PROVIDES THIS PUBLICATION “AS IS” WITHOUT
WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Some states do not allow disclaimer of express or implied
warranties in certain transactions, therefore, this statement may not apply to you.
This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information
herein; these changes will be incorporated in new editions of the publication. IBM may make improvements and/or changes in the
product(s) and/or the program(s) described in this publication at any time.
It is possible that this publication may contain reference to, or information about, IBM products (machines and programs),
programming, or services that are not announced in your country. Such references or information must not be construed to mean
that IBM intends to announce such IBM products, programming, or services in your country.
Requests for technical information about IBM products should be made to your IBM reseller or IBM marketing representative.
Copyright International Business Machines Corporation August 1996. All rights reserved.
Note to U.S. Government Users — Documentation related to restricted rights — Use, duplication or disclosure is subject to
restrictions set forth in GSA ADP Schedule Contract with IBM Corp.
29.L1 and L2 Cache.............................................. 30
30.Features of IBM Option Kit 76H0236................................... 30
31.5.25-Inch Diskette Drive Reading, Writing, and Formatting Capabilities............... 33
32.3.5-Inch Diskette Drive Reading, Writing, and Formatting Capabilities................ 33
33.POST Error Messages – PC 100 and PC 300 .............................. 40
34.Beep Codes – PC 100........................................... 42
35.Beep Codes – PC 300........................................... 42
Copyright IBM Corp. August 1996 v
Preface
This
Technical Information Manual
PC 300 (Type 6560). It is intended for developers who want to provide hardware and software products to
operate with these IBM computers and provides a more in-depth view of how the computers work. Users
of this publication should have an understanding of computer architecture and programming concepts.
Related Publications
In addition to this manual, the following IBM publications provide information related to the operation of the
PC 100 and PC 300. To order publications in the U.S. and Puerto Rico, call 1-800-879-2755. In other
countries, contact an IBM reseller or an IBM marketing representative.
Using Your Personal Computer – PC 100
Hardware Maintenance Manual – PC 100
Using Your Personal Computer – PC 300
Installing Options in Your Personal Computer – PC 300
provides information about the IBM PC 100 (Type 6260) and the IBM
1
1
Understanding Your Personal Computer – PC 300
Hardware Maintenance Manual – PC 300
Manual Style
Attention: The term
Use of reserved areas can cause compatibility problems, loss of data, or permanent damage to the
hardware. When the contents of a register are changed, the state of the reserved bits must be preserved.
When possible, read the register first and change only the bits that must be changed.
In this manual, signals are represented in a small, all-capital-letter format (
the signal indicates that the signal is active low. No sign in front of the signal indicates that the signal is
active high.
In this manual, use of the letter “h” indicates a hexadecimal number. Also, when numerical modifiers such
as “K”, “M” and “G“ are used, they typically indicate powers of 2, not powers of 10 (unless expressing hard
disk storage capacity). For example, 1 KB equals 1024 bytes (2
and 1 GB equals 1 073741824 bytes (230).
When expressing storage capacity, MB equals 1000 KB (1024000). The value is determined by counting
the number of sectors and assuming that every two sectors equals 1 KB.
The actual storage capacity available to the user can vary, depending on the operating system and other
system requirements.
reserved
describes certain signals, bits, and registers that should not be changed.
-ACK). A minus sign in front of
10
), 1 MB equals 1 048576 bytes (220),
1
Not available in the U.S. and Puerto Rico.
vi Copyright IBM Corp. August 1996
Chapter 1. System Description
Chapter 1.System Description
Personal Computer Description .......................................... 2
Advanced Power Management (APM) ...................................... 14
Copyright IBM Corp. August 1996 1
Chapter 1. System Description
Personal Computer Description
The IBM PC 100 (Type 6260) and PC 300 (Type 6560) are versatile products designed to provide
state-of-the-art computing power with room for growth in the future. The two computer models are similar
in design, utilizing the same cover, frame assembly, and system board. They differ in the type of BIOS
resident and in the mix of standard features.
The major features of the PC 100 and PC 300 are:
Intel Pentium microprocessor
Up to 128 MB of system memory
Cirrus GD5436 video subsystem
1 MB of video memory with sockets for additional 1 MB
Industry-standard compatibility
ISA/PCI I/O-bus compatibility
ISA/PCI expansion slots
Enhanced EIDE hard disk drive
Bus master-capable EIDE controller
Two 16550-UART serial ports (serial A and serial B)
L2 cache sockets for pluggable SRAMS (256 KB)
Support for advanced power management
EnergyStar compliant
Support for Plug and Play adapters and monitors
Security features
System unit size
– Four expansion slots
– Four drive bays
Note: Several model variations are available for both the PC 100 and the PC 300.
2Technical Information Manual
Chapter 1. System Description
System Overview
Microprocessor
- Coprocessor
- L1 Cache
Processor (Local) Bus - 64-Bit
Data Buffers
Control
(ISA, DMA,
IRQ)
CMOS, Flash
Keyboard,
Mouse Ports
I/O Control
..
Memory
(DRAM)
PCI I/O Bus - 32-Bit
EIDE Control
Hard
Disk Drive,
CD-ROM
ISA I/O Bus - 16-Bit
Serial Ports
Controls
(Memory,
L2 Cache,
PCI)
Video Control,
DRAM
Video
Port
Parallel Port
L2 Cache
(SRAM)
Sockets
Riser Card
(ISA/PCI Slots)
Diskette Drive
Chapter 1. System Description3
System Features
The following figure lists the devices and features of the PC 100 and PC 300 system board. It also
includes some of the options that may be added to these computers.
Figure 1 (Page 1 of 2). System Board Devices, Features, and Options
32-bit address bus, 64-bit data bus
8 KB internal (L1) write-through code cache
8 KB internal (L1) write-back data cache
Superscalar architecture (two execution units)
Math coprocessor function included in the Pentium
Microprocessor is upgradable for future Intel microprocessor technology
External Cache (L2)DIP sockets for user-installable data/tag RAMs
256 KB asynchronous write-back unified (code and data)
Video SubsystemCirrus Logic GD5436 SVGA video controller
Plug and Play monitor support (DDC2)
Advanced Power Management
Local peripheral bus (LPB) interface
64-bit data path width on PCI bus
Integrated DAC
64-bit graphics accelerator
1 MB of 70 ns FP DRAM
Fast Page Mode DRAM
Sockets for additional 1 MB
Bus ArchitectureISA/PCI-bus-compatible I/O expansion slots
Synchronous 25/30/33 MHz PCI bus
50/60/66 MHz processor bus
Integrated L2 cache controller
Flash ROM Subsystem256 KB flash ROM for POST/BIOS
RAM Subsystem8 MB standard DRAM, upgradable to 128 MB
70-ns fast page (FP) or 60-ns extended data output (EDO), non-parity, dynamic
random access memory (DRAM)
Four 72-pin SIMM sockets in two banks
SIMMs (4 MB, 8 MB, 16 MB, or 32 MB)
Matched pairs required in each bank
CMOS RAM Subsystem128-byte CMOS RAM with real-time clock, calendar, and battery
ISA/PCI BridgeISA/PCI interface
Interrupt Controller15 levels of system interrupts
AT bus interrupts are edge triggered
PCI bus interrupts are level sensitive
System TimersChannel 0–System timer
Channel 1–Refresh generation
Channel 2–Tone generation for speaker
Audio SubsystemOn-board Piezo electric beeper
2
Chapter 1. System Description
2
MHz denotes internal clock speed of the microprocessor only; other factors might also affect application performance.
4Technical Information Manual
Chapter 1. System Description
Figure 1 (Page 2 of 2). System Board Devices, Features, and Options
DeviceFeatures
Diskette Drive ControllerController supports up to two internal diskette drives
A 3.5-in. diskette drive (1.44 MB) is standard
A 5.25-in. diskette drive (1.2 MB) is optional
A second 3.5-in. diskette drive (1.44 MB) is optional and requires a 3.5-in.
conversion kit for a 5.25-in. bay
FIFO operations
Keyboard/Auxiliary-Device
Controller
Parallel Port ControllerOne ECP/EPP parallel port
Serial Port ControllerTwo 16550-UART serial ports (Serial A and B)
Hard Disk Drive ControllerController supports four EIDE devices
Power145 watt (115/230 V ac, 50/60 Hz) power supply
SecurityPower-on password
101-key or 104-key keyboard
Keyboard connector
Auxiliary-device (mouse) connector
Supports standard I/O mode, extended capabilities port (ECP) mode, and
enhanced parallel port (EPP) mode
PCI bus-master EIDE interface
Two PCI bus-master channels
One channel for each EIDE connector (primary and secondary)
SCSI hard disk drives require a PCI SCSI adapter
Built-in overload and surge protection
Advanced Power Management
Administrator password
Startup sequence control
Unattended Start mode
Diskette I/O control
Hard disk I/O control
Chapter 1. System Description5
Chapter 1. System Description
System Board
The following is a diagram of the PC 100 and PC 300 system board. Note that the system board for
these computers might differ slightly from the one shown. A diagram of the system board, including switch
and jumper settings, is provided on the underside of the computer cover.
.1/J3 Power connector (5 V)
.2/JP11 Flash jumper
.3/JP21 FDD write protect
.4/JP4 PS/2 mouse enable/disable
.5/J5 Diskette drive connector
.6/JP23 HDD detect
.7/J8 Primary IDE connector
.8/J7 Secondary IDE connector
.9/ Battery
.1ð/J9 Password jumper (CMOS clear)
.11/L2 cache memory sockets
.12/JP22 Burst mode
.13/JP19 CPU voltage
.14/ Processor socket
.15a/J12 Power LED connector
.15b/J12 Hard disk drive LED connector
.16/J13 CPU fan connector
.17/JP17 CPU clock
.18/SIMM connector 1 - Bank 1
.19/SIMM connector 2 - Bank 1
.2ð/SIMM connector 3 - Bank 0
.21/SIMM connector 4 - Bank 0
.22/Tag RAM socket
.23/J6 Video feature connector
.24/JP13 Cache memory size
.25/JP14 CPU bus clock
.26/JP3 On-board VGA
.27/P4 Monitor (display) port
.28/P1 Parallel port
.29/Video memory sockets
.3ð/P2 Serial (B) port
.31/PCI/ISA riser connector
.32/P3 Serial (A) port
.33/J2 Auxiliary device (mouse) port
.34/J1 Keyboard port
3
26
25
24
2323
22
21
20
27
28
29 30
31 3232
15a
1819
15b
33 34
1
2
3
4
5
6
7
8
9
10
11
12
13
141617
Figure 2. System Board Diagram
3
Extended capabilities port/enhanced parallel port (ECP/EPP)
6Technical Information Manual
Chapter 1. System Description
System Address Maps
Memory Map
The first 640 KB of system board RAM is mapped starting at address 0000000h. A 256-byte area and a 1
KB area of this RAM are reserved for BIOS data areas. Memory can be mapped differently if POST
detects an error. See the section about BIOS data areas in the
Computer BIOS Interface Technical Reference
Figure 3. System Memory Map
Address Range
(Decimal)
1024K–131072K100000–8000000127MExtended memory
960K–1023KF0000–FFFFF64KSystem BIOS
944K–959KEC000–EFFFF16KAvailable
936K–943KEA000–EBFFF8KESCD (Plug and Play configuration area)
928K–935KE8000-E9FFF8KAvailable
896K–927KE0000–E7FFF32KBIOS reserved
800K–895KC8000–DFFFF96KAvailable HI DOS memory (open to ISA and PCI bus)
640K–799KA0000–C7FFF160KVideo memory and BIOS
512K–639K80000–9FFFF128KExtended
0K–511K00000–7FFFF512KDOS applications (conventional)
Address Range
(Hex)
for details.
SizeDescription
IBM Personal System/2 and Personal
Input/Output Address Map
The following figures list the system board I/O address maps. Any addresses that are not shown are
reserved.
Figure 4 (Page 1 of 3). I/O Address Map
Address (Hex)Device
0000–000FDMA 1
0020–003FInterrupt controller 1
0040–0043Timer 1
0044–0047Available I/O for ISA/PCI bus
0048–004BTimer 2
004C–005FAvailable I/O for ISA/PCI bus
0060Keyboard controller data byte
0061System Port B
0062–0063Available I/O for ISA/PCI bus
0064Keyboard controller, command and status byte
0065–006FAvailable I/O for ISA/PCI bus
0070, bit 7Enable/disable NMI
0070, bits 6:0Real time clock address
0071Real time clock data
0072–0077Available I/O for ISA/PCI bus
0078Reserved-system board setup
0079Reserved-system board setup
007A–007FAvailable I/O for ISA/PCI bus
0080POST checkpoint register
0080-008FDMA page register
0090–009FAvailable I/O for ISA/PCI bus
00A0–00BFInterrupt controller 2
00C0–00DEDMA 2
00DF–00EFAvailable I/O for ISA/PCI bus
Chapter 1. System Description7
Figure 4 (Page 2 of 3). I/O Address Map
Address (Hex)Device
00F0Coprocessor busy–Clear
00F1Coprocessor reset
00F2–016FAvailable I/O for ISA/PCI bus
0170–0177IDE channel 1
01F0–01F7IDE channel 0
01F8–021FAvailable I/O for ISA/PCI bus
0220–0227SMC FD-37C669, serial port 3 or 4
0228–0277Available I/O for ISA/PCI bus
0278–027FSMC FD-37C669, parallel port 3
0280–02E7Available I/O for ISA/PCI bus
02E8–02EFSMC FD-37C669, serial port 3 or 4
02F0–02F7Available I/O for ISA/PCI bus
02F8–02FFSMC FD-37C669, serial port 2 (system board)
0300–0337Available I/O for ISA/PCI bus
0338–033FSMC FD-37C669, serial port 3 or 4
0340–0375Available I/O for ISA/PCI bus
0376–0377IDE channel 1
0377, bit 7IDE, diskette change
0378–037FSMC FD-37C669, parallel port 2
0380–03B0Available I/O for ISA/PCI bus
03BC–03BESMC FD-37C669, parallel port 1 (system board)
03E0–03E7Available I/O for ISA/PCI bus
03E8–03EFSMC FD-37C669, serial port 3 or 4
03F0–03F5SMC FD-37C669, diskette channel 0
03F6IDE channel 0
03F7, bit 7IDE, diskette change
03F7, bits 6:0IDE channel 0
03F8–03FFSMC FD-37C669, serial port 1 (system board)
0400–0537Available I/O for ISA/PCI bus
0CF8–0CFBPCI configuration address register
0CFC–0CFFPCI configuration data registers
0D00–0E7FAvailable I/O for ISA/PCI bus
0E80–0E87Available I/O for ISA/PCI bus
0E88–0F3FAvailable I/O for ISA/PCI bus
0F40–0F47Available I/O for ISA/PCI bus
0F47–042E7Available I/O for ISA/PCI bus
42E8Cirrus GD5436
42E9–4AE7Available I/O for ISA/PCI bus
4AE8Cirrus GD5436
4AE9–82E7Available I/O for ISA/PCI bus
82E8Cirrus GD5436
82E9–86E7Available I/O for ISA/PCI bus
86E8Cirrus GD5436
86E9–8AE7Available I/O for ISA/PCI bus
8AE8Cirrus GD5436
8AE9–8EE7Available I/O for ISA/PCI bus
8EE8Cirrus GD5436
8EE9–92E7Available I/O for ISA/PCI bus
92E8Cirrus GD5436
92E9–96E7Available I/O for ISA/PCI bus
96E8Cirrus GD5436
96E9–9AE7Available I/O for ISA/PCI bus
9AE8Cirrus GD5436
9AE9–9EE7Available I/O for ISA/PCI bus
9EE8Cirrus GD5436
9EE9–A2E7Available I/O for ISA/PCI bus
A2E8Cirrus GD5436
A2E9–A6E7Available I/O for ISA/PCI bus
A6E8Cirrus GD5436
A6E9–AAE7Available I/O for ISA/PCI bus
AAE8Cirrus GD5436
AAE9–B2E7Available I/O for ISA/PCI bus
B2E8Cirrus GD5436
Chapter 1. System Description
8Technical Information Manual
Chapter 1. System Description
Figure 4 (Page 3 of 3). I/O Address Map
Address (Hex)Device
B2E9–B6E7Available I/O for ISA/PCI bus
B6E8Cirrus GD5436
B6E9–BAE7Available I/O for ISA/PCI bus
BAE8Cirrus GD5436
BAE9–BEE7Available I/O for ISA/PCI bus
BEE8Cirrus GD5436
BEE9–E2E7Available I/O for ISA/PCI bus
E2E8Cirrus GD5436
E2E9Available I/O for ISA/PCI bus
E2EACirrus GD5436
E2EB–FFFFAvailable I/O for ISA/PCI bus
DMA I/O Address Map
Figure 5 (Page 1 of 2). DMA I/O Addresses for Memory Addresses, Word Counts, and Command/Status
Registers