HYNIX HY57V161610DTC-7I, HY57V161610DTC-10I, HY57V161610DTC-55I, HY57V161610DTC-6I Datasheet

HY57V161610D

2 Banks x 512K x 16 Bit Synchronous DRAM

DESCRIPTION

THE Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the Mobile applications
which require low power consumption and industrial temperature range. HY57V161610D is organized as 2banks of
524,288x16.

HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band­width. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline
design is not restricted by a `2N` rule.)

FEATURES

• Single 3.0V to 3.6V power supply

• All device pins are compatible with LVTTL interface

• JEDEC standard 400mil 50pin TSOP-II with 0.8mm
of pin pitch

• All inputs and outputs referenced to positive edge of
system clock

• Data mask function by UDQM/LDQM

• Internal two banks operation

Note1)

ORDERING INFORMATION

Part No. Clock Frequency Organization Interface Package

HY57V161610DTC-55I 183MHz

HY57V161610DTC-6I 166MHz

HY57V161610DTC-7I 143MHz

HY57V161610DTC-10I 100MHz

• Auto refresh and self refresh

• 4096 refresh cycles / 64ms

• Programmable Burst Length and Burst Type

- 1, 2, 4, 8 and Full Page for Sequence Burst

- 1, 2, 4 and 8 for Interleave Burst

• Programmable CAS Latency ; 1, 2, 3 Clocks

2Banks x 512Kbits x 16 LVTTL

400mil

50pin TSOP II

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied

Rev. 0.2/Aug.01

PIN CONFIGURATION

HY57V161610D

PIN DESCRIPTION

VDD

DQ0
DQ1

VSSQ

DQ2
DQ3

VDDQ

DQ4
DQ5

VSSQ

DQ6

DQ7
VDDQ
LDQM

WE
CAS
RAS

CS
A11
A10

A0
A1
A2
A3

VDD

1
2
3
4
5
6
7
8

9
10
11
12

50pin TSOP-II

13

400mil x 825mil

14

0.8mm pin pitch

15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6

A5
A4
VSS

PIN PIN NAME DESCRIPTION

CLK Clock

CKE Clock Enable

The system clock input. All other inputs are referenced to the SDRAM on the
rising edge of CLK.

Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh.

CS Chip Select Command input enable or mask except CLK, CKE and DQM

BA Bank Address Select either one of banks during both RAS and CAS activity.

A0 ~ A10 Address

Row Address Strobe,

RAS, CAS, WE

Column Address Strobe,
Write Enable

Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10

RAS, CAS and WE define the operation.
Refer function truth table for details

LDQM, UDQM Data Input/Output Mask DQM control output buffer in read mode and mask input data in write mode

DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin

V DD/V SS Power Supply/Ground Power supply for internal circuit and input buffer

V DDQ/V SSQ Data Output Power/Ground Power supply for DQ

NC No Connection No connection

Rev. 0.2/Aug.01 2

FUNCTIONAL BLOCK DIAGRAM

1Mx16 Synchronous DRAM

Self Refresh Counter

HY57V161610D

Refresh

Interval Timer

Address[0:10]

CLK

CKE

BA(A11)

CS

RAS

CAS

WE

UDQM

LDQM

Auto/Self Refresh

Precharge
Row Active

Column Active

State Machine

Refresh

Counter

Ref. Addr.[0:11]

Address

Register

Burst Length

Counter

Row Decoder

Row Addr. Latch/Predecoder

Overflow

Sense AMP & I/O gates

512Kx16

Bank 0

Sense AMP & I/O gates

Column Decoder

Column Addr.

Latch & Counter

Column Decoder

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12

Data Input/Output Buffers

DQ13
DQ14
DQ15

512Kx16

Bank 1

Row Addr. Latch/Predecoder

I/O ControlTest ModeMode Register

Rev. 0.2/Aug.01 3

HY57V161610D

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Unit

Ambient Temperature T A - 40 ~ 85 °C

Storage Temperature T STG -55 ~ 125 °C

Voltage on Any Pin relative to V SS VIN , V OUT -1.0 ~ 4.6 V

Voltage on V DD relative to V SS V DD -1.0 ~ 4.6 V

Short Circuit Output Current IOS 50 mA

Power Dissipation P D 1 W

Soldering Temperature·Time T SOLDER 260·10 °C ·Sec

Note : Operation at above absolute maximum rating can adversely affect device reliability.

DC OPERATING CONDITION (TA= -40°C to 85°C )

Parameter Symbol Min Typ. Max Unit Note

Power Supply Voltage V DD , V DDQ 3.0 3.3 3.6 V 1, 2

Input high voltage V IH 2.0 3.0 V DD + 0.3 V 1, 4

Input low voltage V IL -0.5 0 0.8 V 1, 5

Note :

1.All voltages are referenced to V SS = 0V.

2.V DD (min) is 3.15V when HY57V161610DTC-7I operates at CAS latency=2

3.V IH (max) is acceptable 4.6V AC pulse width with ≤ 10ns of duration.

4.V IL (min) is acceptable -1.5V AC pulse width with ≤ 10ns of duration.

AC OPERATING CONDITION (TA= - 40°C to 85°C , V DD=3.0V to 3.6V, V SS=0V)

Parameter Symbol Value Unit Note

AC input high / low level voltage V IH / V IL 2.4/0.4 V

Input timing measurement reference level voltage Vtrip 1.4 V

Input rise / fall time tR / tF 1 ns

Output timing measurement reference level Voutref 1.4 V

Output load capacitance for access time measurement CL 30 pF 1

Note :

1. Output load to measure access times is equivalent to two TTL gates and one capacitance(30pF).
For details, refer to AC/DC output load circuit.

2. V DD (min) is 3.15V when HY57V161610DTC-7I operates at CAS latency=2 and tCK2=8.9ns

Rev. 0.2/Aug.01 4