HYNIX HY51V18163HGJ-5, HY51V18163HGT-6, HY51V18163HGT-7, HY51VS18163HGJ-5, HY51VS18163HGJ-6 Datasheet

HY51V(S)18163HG/HGL

1M x 16Bit EDO DRAM

PRELIMINARY

DESCRIPTION

The HY51V(S)18163HG/HGL is the new generation dynamic RAM organized 1,048,576 words x 16bit. HY51V(S)18163HG/HGL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The HY51V(S)18163HG/HGL offers Extended Data Out PageMode as a high speed access mode. Multiplexed address inputs permit the HY51V(S)18163HG/HGL to be packaged in standard 400mil 42pin SOJ and 44(50) pin TSOP-II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment.

FEATURES

•Extended Data Out Mode capability

•Read-modify-write capability

•Multi-bit parallel test capability

•TTL(3.3V) compatible inputs and outputs

•/RAS only, CAS-before-/RAS, Hidden and self refresh(L-version) capability

•Fast access time and cycle time

•JEDEC standard pinout

•42pin plastic SOJ / 44(50)pin TSOP-II (400mil)

•Single power supply of 3.3V +/- 0.3V

•Battery back up operation(L-version)

•2CAS byte control

Part No	tRAC	tCAC	tRC	tHPC
HY51V(S)18163HG/HGL-5	50ns	13ns	84ns	20ns
HY51V(S)18163HG/HGL-6	60ns	15ns	104ns	25ns
HY51V(S)18163HG/HGL-7	70ns	18ns	124ns	30ns

•Power dissipation

		50ns	60ns	70ns
	Active	684mW	612mW	540mW
	Standby	7.2mW(CMOS level Max)
		0.83mW (L-version : Max)

ORDERING INFORMATION

•	Refresh cycle
	Part No	Ref	Normal	L-part
	HY51V18163HG	1K	16ms
	HY51V18163HGL	1K		128ms

	Part Number	Access Time	Package
HY51V(S)18163HGJ/HG(L)J-5		50ns
HY51V(S)18163HGJ/HG(L)J-6		60ns	400mil 42pin SOJ
HY51V(S)18163HGJ/HG(L)J-7		70ns
HY51V(S)18163HGT/HG(L)T-5		50ns
HY51V(S)18163HGT/HG(L)T-6		60ns	400mil 44(50)pin TSOP-II
HY51V(S)18163HGT/HG(L)T-7		70ns
(S) : Self refresh,	(L) : Low power

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied.

Rev.0.1/Apr.01

HY51V(S)18163HG/HGL

PIN CONFIGURATION

	VCC						VSS					VCC			1		50	VSS
				1		42					I/O0							I/O15
I/O0				2		41	I/O15								2		49
											I/O1							I/O14
I/O1				3		40	I/O14								3		48
											I/O2							I/O13
I/O2							I/O13								4		47
				4		39					I/O3							I/O12
I/O3							I/O12								5		46
				5		38						VCC						VSS
	VCC						VSS								6		45
				6		37					I/O4							I/O11
															7		44
I/O4							I/O11				I/O5							I/O10
				7		36									8		43
I/O5							I/O10				I/O6							I/O9
				8		35									9		42
I/O6							I/O9				I/O7							I/O8
				9		34									10		41
I/O7							I/O8					NC						NC
				10		33									11		40
							NC
	NC			11		32
	NC			12		31	LCAS					NC						NC
															15		36
	WE							UCAS				NC
				13		30									16
																	35	LCAS
	RAS			14		29		OE				WE			17		34		UCAS
	A11			15		28	A9					RAS			18		33		OE
												A11						A9
	A10			16		27	A8								19		32
	A0			17		26	A7					A10			20		31	A8
													A0					A7
	A1						A6								21		30
				18		25
													A1					A6
	A2						A5								22		29
				19		24							A2					A5
	A3						A4								23		28
				20		23							A3		24		27	A4
	VCC			21		22	VSS					VCC			25		26		VSS

42 Pin Plastic SOJ 44(50) Pin Plastic TSOP-II

PIN DESCRIPTION

Pin	Function
/RAS	Row Address Strobe
/UCAS, /LCAS	Column Address Strobe
/WE	Write Enable
/OE	Output Enable
A0-A9	Address Inputs
A0-A9	Refresh Address Inputs
I/O 0- I/O 15	Data Input / Output
Vcc	Power (3.3V)
Vss	Ground
NC	No connection

Rev.0.1/Apr.01

2

HY51V(S)18163HG/HGL

ABSOLUTE MAXIMUM RATINGS

	Parameter	Symbol	Rating	Unit
	Ambient Temperature	TA	0 ~ 70	oC
	Storage Temperature	TSTG	-55 ~ 125	oC
	Voltage on Any Pin relative to Vss	VT	-0.5 ~ Vcc + 0.5	V
			(Max 4.6V)
	Voltage on Vcc relative to Vss	Vcc	-0.5 ~ 4.6	V
	Short Circuit Output Current	IOUT	50	mA
	Power Dissipation	PT	1	W

Note : Operation at or above absolute Maximum Ratings can adversely affect device reliability

Recommended DC OPERATING CONDITIONS (TA=0 to 70 oC)

Parameter	Symbol	Min	Typ.	Max	Unit	Note
Power Supply Voltage	Vcc	3.0	3.3	3.6	V
Input High Voltage	VIH	2.0	-	Vcc + 0.3	V
Input Low Voltage	VIL	-0.3	-	0.8	V

Note : All voltages are referenced to Vss

The supply voltage with all Vcc pins must be on the same level. The supply voltage with all Vss pins must be on the same level

Rev.0.1/Apr.01

3

HY51V(S)18163HG/HGL

Truth Table

/RAS	/LCAS	/UCAS	/WE		/OE	Output		Operation		Notes
H	D	D	D		D	Open		Standby		1 ,3
L	L	H	H		L	Valid	Lower byte
L	H	L	H		L	Valid	Upper byte		Read cycle	1, 3
L	L	L	H		L	Valid	Word
L	L	H	L		D	Open	Lower byte
L	H	L	L		D	Open	Upper byte		Early write cycle	1, 2, 3
L	L	L	L		D	Open	Word
L	L	H	L		H	Undefined	Lower byte
L	H	L	L		H	Undefined	Upper byte		Delayed write cycle	1, 2, 3
L	L	L	L		H	Undefined	Word
L	L	H	H to L		L to H	Valid	Lower byte
L	H	L	H to L		L to H	Valid	Upper byte		Read-modify-write	1, 3
									Cycle
L	L	L	H to L		L to H	Valid	Word
H to L	H	L	D		D	Open	Word
									CBR refresh
H to L	L	H	D		D	Open	Word
									or	1, 3
									Self refresh
H to L	L	L	D		D	Open	Word
									(L-series)
L	H	H	D		D	Open	Word		/RAS only refresh	1, 3
									cycle
L	L	L	H		H	Open		Read cycle		1, 3
							(Output disabled)
Notes :
1. H : High ( inactive) L : Low ( active)					D : H or L
2. tWCS >= 0ns		Early write cycle
twcs	< 0ns	Delayed write cycle

3.Mode is determined by the OR function of the /UCAS and /LCAS (mode is set by earliest of /UCAS and /LCAS active edge and reset by the latest of /UCAS and /LCAS inactive edge), However write operation and output High-Z control are done independently by each /UCAS, /LCAS

ex) if /RAS = H to L, /UCAS = H, /LCAS = L, then /CAS-before-/RAS refresh cycle is selected

Rev.0.1/Apr.01

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