HYNIX HY57V161610DTC-7, HY57V161610DTC-8, HY57V161610DTC-10, HY57V161610DTC-15, HY57V161610DTC-5 Datasheet

HY57V161610D

2 Banks x 512K x 16 Bit Synchronous DRAM

DESCRIPTION

THE Hyundai HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic
applications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16.

HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initi­ated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A
burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a
new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)

FEATURES

• Single 3.0V to 3.6V power supply

• All device pins are compatible with LVTTL interface

• JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin
pitch

• All inputs and outputs referenced to positive edge of system
clock

• Data mask function by UDQM/LDQM

• Internal two banks operation

ORDERING INFORMATION

Part No. Clock Frequency Organization Interface Package

HY57V161610DTC-5 200MHz

HY57V161610DTC-55 183MHz

HY57V161610DTC-6 166MHz

HY57V161610DTC-7 143MHz

HY57V161610DTC-8 125MHz

• Auto refresh and self refresh

• 4096 refresh cycles / 64ms

• Programmable Burst Length and Burst Type

- 1, 2, 4, 8 and Full Page for Sequence Burst

- 1, 2, 4 and 8 for Interleave Burst

• Programmable CAS Latency ; 1, 2, 3 Clocks

2Banks x 512Kbits x 16 LVTTL

400mil

50pin TSOP II

HY57V161610DTC-10 100MHz

HY57V161610DTC-15 66MHz

Note :

DD

1. V

(min) of HY57V161610DTC-5/55 is 3.15V

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for
use of circuits described. No patent licenses are implied

Rev. 4.0/A ug. 02 1

PIN CONFIGURATION

V

V

V

V

V

V

VDDQ

VDDQ
LDQM

LDQM

/CAS

/CAS
/RAS

/RAS

V

V

DD

DD

DQ0

DQ0

DQ1

DQ1

SSQ

SSQ

DQ2

DQ2

DQ3

DQ3

DDQ

DDQ

DQ4

DQ4

DQ5

DQ5

SSQ

SSQ

DQ6

DQ6
DQ7

DQ7

/WE

/WE

/CS

/CS

A11

A11
A10

A10

V

V

DD

DD

A0

A0
A1

A1
A2

A2
A3

A3

1

1
2

2
3

3
4

4
5

5
6

6
7

7
8

8
9

9
10

10
11

11
12

12
13

13
14

14
15

15
16

16
17

17
18

18
19

19
20

20
21

21
22

22
23

23
24

24
25

25

50pin TSOP II

50pin TSOP II

400mil x 825mil

400mil x 825mil

0.8mm pin pitch

0.8mm pin pitch

50

50
49

49
48

48
47

47
46

46
45

45
44

44
43

43
42

42
41

41
40

40
39

39
38

38
37

37
36

36
35

35
34

34
33

33
32

32
31

31
30

30
29

29
28

28

27

27
26

26

V

V

SS

SS

DQ15

DQ15

DQ14

DQ14

VSSQ

VSSQ
DQ13

DQ13

DQ12

DQ12

VDDQ

VDDQ
DQ11

DQ11

DQ10

DQ10

VSSQ

VSSQ
DQ9

DQ9

DQ8

DQ8

VDDQ

VDDQ

NC

NC
UDQM

UDQM
CLK

CLK
CKE

CKE
NC

NC
A9

A9
A8

A8
A7

A7
A6

A6
A5

A5
A4

A4
VSS

VSS

HY57V161610D

PIN DESCRIPTION

PIN PIN NAME DESCRIPTION

CLK Clock

CKE Clock Enable

CS

BA Bank Address Select either one of banks during both RAS and CAS activity.

A0 ~ A10 Address

RAS

, CAS, WE

LDQM, UDQM Data Input/Output Mask DQM control output buffer in read mode and mask input data in write mode

DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin

V

DD/VSS Power Supply/Ground Power supply for internal circuit and input buffer

DDQ/VSSQ

V

NC No Connection No connection

Chip Select Command input enable or mask except CLK, CKE and DQM

Row Address Strobe,
Column Address Strobe, Write
Enable

Data Output Power/Ground Power supply for DQ

The system clock input. All other inputs are referenced to the SDRAM on the rising
edge of CLK.

Controls internal clock signal and when deactivated, the SDRAM will be one of the
states among power down, suspend or self refresh.

Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10

RAS

, CAS and WE define the operation.

Refer function truth table for details

Rev. 4.0/Aug. 02 2

FUNCTIONAL BLOCK DIAGRAM

1Mx16 Synchronous DRAM

Self Refresh Counter

HY57V161610D

Refresh

Interval Timer

Address[0:10]

CLK

CKE

BA(A11)

CS

RAS

CAS

WE

UDQM

LDQM

Column Active

State Machine

Auto/Self Refresh

Precharge

Row Active

Refresh
Counter

Ref. Addr.[0:11]

Address
Register

Burst Length

Counter

Row Decoder

Row Addr. Latch/Predecoder

Overflow

512Kx16

Bank 0

Sense AMP & I/O gates

Column Decoder

Column Addr.

Latch & Counter

Column Decoder

Sense AMP & I/O gates

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11

Data Input/Output Buffers

DQ12
DQ13
DQ14
DQ15

512Kx16

Bank 1

Row Addr. Latch/Predecoder

I/O ControlTest ModeMode Register

Rev. 4.0/Aug. 02 3

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Unit

HY57V161610D

Ambient Temperature T

Storage Temperature T

Voltage on Any Pin relative to V

Voltage on V

DD

relative to V

SS

SS

Short Circuit Output Current I

Power Dissipation P

Soldering Temperature·Time T

A

STG

VIN, V

DD

V

OS

D

SOLDER

OUT

0 ~ 70 °C

-55 ~ 125 °C

-1.0 ~ 4.6 V

-1.0 ~ 4.6 V

50 mA

1W

260·10 °C ·Sec

Note : Operation at above absolute maximum rating can adversely affect device reliability.

DC OPERATING CONDITION

(TA=0°C to 70°C)

Parameter Symbol Min Typ. Max Unit Note

Power Supply Voltage V

Input high voltage V

Input low voltage V

DD

IH

IL

, V

DDQ

3.0 3.3 3.6 V 1, 2, 3

2.0 3.0 VDD + 0.3 V 1, 4

-0.5 0 0.8 V 1, 5

Note :

1.All voltages are referenced to V

2.V

DD(min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2

3.V

DD

(min) of HY57V161610DTC-5/55 is 3.15V

4.V

IH

(max) is acceptable 4.6V AC pulse width with ≤ 10ns of duration.

5.V

IL(min) is acceptable -1.5V AC pulse width with ≤ 10ns of duration.

SS

= 0V.

AC OPERATING CONDITION

(TA=0°C to 70°C, VDD=3.0V to 3.6V, V

SS

=0V)

Parameter Symbol Value Unit Note

AC input high / low level voltage V

IH

IL

/ V

2.4/0.4 V

Input timing measurement reference level voltage Vtrip 1.4 V

Input rise / fall time tR / tF 1 ns

Output timing measurement reference level Voutref 1.4 V

Output load capacitance for access time measurement CL 30 pF 1

Note :

1. Output load to measure access times is equivalent to two TTL gates and one capacitance(30pF).

For details, refer to AC/DC output load circuit.

2. V

DD(min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns

3. V

DD(min) of HY57V161610DTC-5/55 is 3.15V‘

Rev. 4.0/Aug. 02 4