HYNIX HY51V18163HGJ-5, HY51V18163HGT-6, HY51V18163HGT-7, HY51VS18163HGJ-5, HY51VS18163HGJ-6 Datasheet
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HY51V(S)18163HG/HGL
1M x 16Bit EDO DRAM
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.0.1/Apr.01
DESCRIPTION
FEATURES
• Fast access time and cycle time
ORDERING INFORMATION
Part No tRAC tCAC tRC tHPC
HY51V(S)18163HG/HGL-5 50ns 13ns 84ns 20ns
HY51V(S)18163HG/HGL-6 60ns 15ns 104ns 25ns
HY51V(S)18163HG/HGL-7 70ns 18ns 124ns 30ns
50ns 60ns 70ns
Active 684mW 612mW 540mW
Standby
7.2mW(CMOS level Max)
0.83mW (L-version : Max)
Part Number Access Time Package
HY51V(S)18163HGJ/HG(L)J-5
HY51V(S)18163HGJ/HG(L)J-6
HY51V(S)18163HGJ/HG(L)J-7
50ns
60ns
70ns
400mil 42pin SOJ
HY51V(S)18163HGT/HG(L)T-5
HY51V(S)18163HGT/HG(L)T-6
HY51V(S)18163HGT/HG(L)T-7
50ns
60ns
70ns
400mil 44(50)pin TSOP-II
PRELIMINARY
The HY51V(S)18163HG/HGL is the new generation dynamic RAM organized 1,048,576 words x 16bit.
HY51V(S)18163HG/HGL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The HY51V(S)18163HG/HGL offers Extended Data Out PageMode as a high speed access mode. Multiplexed address inputs permit the HY51V(S)18163HG/HGL to be
packaged in standard 400mil 42pin SOJ and 44(50) pin TSOP-II. The package size provides high system
bit densities and is compatible with widely available automated testing and insertion equipment.
• Extended Data Out Mode capability
• Read-modify-write capability
• Multi-bit parallel test capability
• TTL(3.3V) compatible inputs and outputs
• /RAS only, CAS-before-/RAS, Hidden and self
refresh(L-version) capability
• JEDEC standard pinout
• 42pin plastic SOJ / 44(50)pin TSOP-II (400mil)
• Single power supply of 3.3V +/- 0.3V
• Battery back up operation(L-version)
• 2CAS byte control
• Power dissipation
• Refresh cycle
Part No Ref Normal L-part
HY51V18163HG 1K 16ms
HY51V18163HGL 1K 128ms
(S) : Self refresh, (L) : Low power
HY51V(S)18163HG/HGL
Rev.0.1/Apr.01 2
PIN CONFIGURATION
Pin Function
/RAS Row Address Strobe
/UCAS, /LCAS Column Address Strobe
/WE Write Enable
/OE Output Enable
A0-A9 Address Inputs
A0-A9 Refresh Address Inputs
I/O 0- I/O 15 Data Input / Output
Vcc Power (3.3V)
Vss Ground
NC No connection
PIN DESCRIPTION
42
43
44
45
46
40
41
33
30
31
32
27
28
29
26
34
35
36
47
48
49
50
NC
NC
VSS
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
VSS
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS
A9
VSS
I/O15
I/O14
I/O13
I/O12
38
39
40
41
42
I/O11
I/O10
I/O9
I/O8
NC
32
33
34
35
36
VSS
37
LCAS
UCAS
OE
29
30
31
A9
A8
A7
26
27
28
A6
A5
A4
23
24
25
VSS22
11
1
2
3
4
5
7
8
9
10
6
15
16
17
18
19
20
21
22
23
24
25
NC
NC
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
VCC
NC
WE
RAS
A11
A10
A0
A1
V
CC
VCC
A2
A3
VCC
I/O0
I/O1
I/O2
I/O3
1
2
3
4
5
I/O4
I/O5
I/O6
I/O7
NC
7
8
9
10
11
VCC
6
NC
WE
RAS
12
13
14
A11
A10
A0
15
16
17
A1
A2
A3
18
19
20
VCC
21
42 Pin Plastic SOJ 44(50) Pin Plastic TSOP-II
HY51V(S)18163HG/HGL
Rev.0.1/Apr.01 3
ABSOLUTE MAXIMUM RATINGS
Note : Operation at or above absolute Maximum Ratings can adversely affect device reliability
Recommended DC OPERATING CONDITIONS (TA=0 to 70
o
C)
Note : All voltages are referenced to Vss
The supply voltage with all Vcc pins must be on the same level. The supply voltage with all Vss pins must be on the same level
Parameter Symbol Rating Unit
Ambient Temperature TA 0 ~ 70
o
C
Storage Temperature TSTG -55 ~ 125
o
C
Voltage on Any Pin relative to Vss VT
-0.5 ~ Vcc + 0.5
(Max 4.6V)
V
Voltage on Vcc relative to Vss Vcc -0.5 ~ 4.6 V
Short Circuit Output Current IOUT 50 mA
Power Dissipation PT 1 W
Parameter Symbol Min Typ. Max Unit Note
Power Supply Voltage Vcc 3.0 3.3 3.6 V
Input High Voltage VIH 2.0 - Vcc + 0.3 V
Input Low Voltage VIL -0.3 - 0.8 V
HY51V(S)18163HG/HGL
Rev.0.1/Apr.01 4
Truth Table
Notes :
1. H : High ( inactive) L : Low ( active) D : H or L
2. tWCS >= 0ns Early write cycle
twcs < 0ns Delayed write cycle
3. Mode is determined by the OR function of the /UCAS and /LCAS (mode is set by earliest of /UCAS and /LCAS
active edge and reset by the latest of /UCAS and /LCAS inactive edge), However write operation and output
High-Z control are done independently by each /UCAS, /LCAS
ex) if /RAS = H to L, /UCAS = H, /LCAS = L, then /CAS-before-/RAS refresh cycle is selected
/RAS /LCAS /UCAS /WE /OE Output Operation Notes
H
D
D D D Open Standby 1 ,3
L
L
H H L Valid Lower byte
Read cycle 1, 3
L
H
L H L Valid Upper byte
L
L
L H L Valid Word
L
L
H L D Open Lower byte
Early write cycle 1, 2, 3
L
H
L L D Open Upper byte
L
L
L L D Open Word
L
L
H L H Undefined Lower byte
Delayed write cycle 1, 2, 3
L
H
L L H Undefined Upper byte
L
L
L L H Undefined Word
L
L
H H to L L to H Valid Lower byte
Read-modify-write
Cycle
1, 3
L
H
L H to L L to H Valid Upper byte
L
L
L H to L L to H Valid Word
H to L
H
L D D Open Word
CBR refresh
or
Self refresh
(L-series)
1, 3
H to L
L
H D D Open Word
H to L
L
L D D Open Word
L
H
H D D Open Word /RAS only refresh
cycle
1, 3
L
L
L H H Open Read cycle
(Output disabled)
1, 3
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