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This is the first edition of “Programming HP VXI Instruments”
September 1994; First Edition
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Chapter 1
Introduction
This document descri bes the common commands and t he status sy stem used
by VXI instruments. The status system is a group of registers that can be
used to monitor events, such as when an error occurs or when a reading is
available from a s pecified instrumen t in your VXI mainframe. Us e the SCPI
status system commands and IEEE 488.2 common commands described in
Chapter 3 of this document to program the status system.
The common commands are used to read and configure the status byte and
standard event group registers, while the status commands are used to
configure the standard operation status group and questionable data status
group registers. See the individual VXI instrument manuals to determine
how a specific instrument uses the operation status group and the
questionable data status group. If status system commands are not
documented, that instrument does not use the registers.
Other common commands are used for general functionality, macros, and
synchronization.
NoteThis document should be placed with your other VXI instrumentation
documentation.
Introduction 5Chapter 1
Notes:
6Introduction Chapter 1
Programming the Status System
About this Chapter
Chapter 2
This chapter discusses the structure of the status system used in SCPI
instruments and explains how to program status registers. An important
feature of SCPI instruments is that they all implement status regist ers in the
same way. The status system is explained in the following sections:
•General Status Register Model
This section explains the way that status registers are structured in
SCPI instruments. It also contains an example of how bits in the
various registers change with different input conditions.
•Required Status Groups
This section describ es the minimum r equired status registers pre sent in
SCPI instruments. These status registers cover the most frequently
used functions.
General Status Register Model
The generalized status register model shown in Figure 2-1 is the building
block of the SCPI sta tus system. Thi s model consists of a conditio n register,
transition filter, an event register, and an enable register. A set of these
registers is called a status group.
When a status group is implemented in an instrument, it always contai ns all
of the component registers. However, there is not always a corresponding
command to read or write to every register.
Figure 2-1. Generalized Status Register Model
Programming the Status System 7Chapter 2
Condition RegisterThe condition register continuously monitors the hardware and firmware
status of the instrument. There is no latching or buffering for this register;
it is updated in real time. Condition registers are read-only.0
If there is no command to read a particular condition register, it is simply
invisible to you.
Transition FilterThe transi t ion fi lt er specifies which types of bit state changes in the
condition register will set corresponding bits in the event register.
Transition filter bits may be set for positiv e transitions (P TR), negative
transitions (NTR), or both. Positive means a condition bit changes from
0 to 1. Negative means a condition bit changes from 1 to 0. Transition fil ters
are read-write. Transition filters are unaffected by *CLS (clear status) or
queries. They are set to instrument-dependent values at power
on and afte r *RST (reset).
If there are no commands to access a particular transition filter, it has a
fixed setting. This setting is specified in the instrument’s programming
guide or command dictionary. Most of our VXI instruments assign the
transition filter to detect positive transitions only.
Event RegisterThe event register latches transition events from the condition register as
specified by the transition filter. Bits in the event register are latched, and,
once set, they remain set until cleared by a query or *CLS (clear status).
There is no buffering; so while an eve nt bit is set, subsequent events
corresponding to that bit are ignored. Event registers are read-only.
Enable RegisterThe enable register specifies which bits in the event register can gen erate a
summary bit. The instrument logically ANDs corresponding bits in the
event and enable reg isters, and ORs all the resulti ng bits to obtain a summary
bit. Summary bits are, in turn, recor ded in anoth er register, oft en the Status
Byte. Enable registers are read-write. Enable registers are not affected by
*CLS (clear status). Queryin g enable register s does not affec t them. There
is always a command to read and write to the enable r egi ster of a particular
status group.
An Example
Sequence
Figure 2-2 illustr ate s th e response of a single bit posit io n in a typ ic al status
group for various settings. The changing state of the condition in question
is shown at the bot tom of t he figur e. A smal l binar y table shows the state of
the chosen bit in each status register at the selected times T1-T5.
8Programming the Status System Chapter 2
Figure 2-2. Typical Status Bit Changes in a Status Register
Programming the Status System 9Chapter 2
Required Status Groups
All SCPI instruments must implement a minimum set of status groups.
Some instruments contain additional status groups, consistent with the
general status re gister model. The minimum requi red status system is shown
in Figure 2-3.
Figure 2-3. Minimum Required Status Register System
10Programming the Status System Chapter 2
The Standard Operation Status and Questionable Data groups are 16 bits
wide, while Status Byte and Standard Eve nt groups are onl y 8 bits wide. In
all 16 bit groups, the most signif icant bit ( bit 15) is not us ed. Bit 15 always
returns a zero. The comman ds t hat set and query bits in the status r egi sters
all use decimal integers. For example, you send *ESE 4 to set bit 2 of the
Standard Event enable register. Similarly, a response of "8" to the query
*ESE? indicates th at bit 3 is set. The r emainder of this chap ter explains each
status group in detail.
Status ByteAs Figure 2-4 indicates, the Status Byte is used to summarize information
from all the other status groups. The Status Byte differs from the other
groups in the way you read it and how its summary bit is processed.
Figure 2-4. Status Byte Register
The Status Byte can be read using either the *STB? common command or
by doing a SICL ireadstb function call. The ireadstb function reads the
status byte from the device specified.
The Status Byte summary bit actually appears in bit 6 (RQS) of the Status
Byte. When bit 6 is set, it generates an SRQ interrupt. This interrupt is a
low-level HP-IB message that signals the controller that at least one
instrument on the bus requires attention.
There are some subtle differences between *STB? and ireadstb. You can
use either method to read the state of bits 0-5 and bit 7. Bit 6 is treated
differently dependi ng on whether you use *STB? or i readstb. With ireadstb,
bit 6 returns RQS (request for service) which is cleared after the first
ireadstb. *STB? returns the MSS (master state summary). This is the
summary bit of the status byte register. It’s like a condition bit and will
return to zero only when all enabled bits in the status byte are zero. In
general, use ireadstb inside interrupt service routines, not *STB?.
NoteIn an SRQ interrupt service routine, yo u must clear the event register which
caused the SRQ (for example, STATus:QUES:EVEN?,
STATus:OPER:EVEN?, or *ESR?). Failure to do so will prevent future
SRQs from arriving.
Programming the Status System 11Chapter 2
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