The information contained in this document is subject to change without notice.
Hewlett-Packard makes no warranty of any kind with regard to this
material, including, but not limited to, the implied warranties of
merchantability and fitness for a particular purpose.
Hewlett-Packard shall not be liable for errors contained herein or for incidental
or consequential damages in connection with the furnishing, performance, or use
of this material.
Hewlett-Packard assumes no responsibility for the use or reliability of its
software on equipment that is not furnished by Hewlett-Packard.
This document contains proprietary information that is protected by copyright.
All rights are reserved. No part of this document may be photocopied,
reproduced, or translated to another language without the prior written consent
of Hewlett-Packard Company.
Adobe
Microsoft®, Windows® and MS-DOS® are U.S. registered trademarks of
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TM
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in certain jurisdictions.
Microsoft Corporation.
Hewlett-Packard France
Commercial Desktop Computing Division
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France
1997 Hewlett-Packard Company
Preface
This manual is a technical reference and BIOS document for engineers and
technicians providing system level support. It is assumed that the reader
possesses a detailed understanding of AT-compatible microprocessor
functions and digital addressing techniques.
Technical information that is readily available from other sources, such as
manufacturer’s proprietary publications, has not been reproduced.
This manual contains summary information only. For additional reference
material, refer to the bibliography, on the next page.
Conventions
The following conventions are used throughout this manual to identify
specific numeric elements:
Hexadecimal numbers are identified by a lower case h.
❒
For example,
Binary numbers and bit patterns are identified by a lower case b.
❒
For example,
0FFFFFFFh or 32F5h
1101b or 10011011b
iii
Bibliography
HP Vectra VL 6/xxx Series 6 User’s Guide manual (D5040-90001).
❒
HP Vectra VL 6/xxx MT Series 6 User’s Guide manual (D5050-90001).
❒
HP Vectra VL 6/xxx Series 6 Familiarization Guide (D5040-90901).
❒
HP Network Administrator’s Guide (online).
❒
HP Vectra Accessories Service Handbook - 7th edition
❒
(5965-4074).
HP Vectra PC Service Handbook (Volume 1) - 12th edition
❒
(to be announced).
HP Support Assistant CD-ROM (by subscription).
❒
The following Intel® publications provide more detailed information:
Pentium Pro Family Developer’s Manual, Volume 1: Specifications,
❒
Intel, 1996, ISBN 1-55512-259-0
Pentium Pro Family Developer’s Manual, Volume 2: Programmer’s
❒
reference manual, Intel, 1996, ISBN 1-55512-260-4
Pentium Pro Family Developer’s Manual, Volume 3: Operating
❒
System Writer’s Manual, Intel, 1996, ISBN 1-55512-261-2
This manual describes the HP Vectra VL 6/xxx Series 6 PC, and provides
detailed system specifications.
This chapter introduces the external features, and lists the specifications
and characteristic data of the system. It also summarizes the documentation
which is available.
9
Front view
Front view with cover
removed
1 System Overview
Package
Package
activity light
status light
(Multimedia models only)
Hard disk drive
24✕ CD-ROM drive
Flexible disk drive
Rear view
System board switches
Video memory
Processor
VRM
Main memory
Security lock hole
(All icons shown here are for information, and do not necessarily appear on
the PC).
Display
Key boa rd
USB
Mouse
Par al lel
Retaining brackets
Serial A
Serial B
10
Minitower Package
1 System Overview
Package
Front view with cover
removed
Rear view
System board switches
Processor
VRM
Video memory
Main memory
Serial B
Serial A
Par al lel
Mouse
USB
Key boa rd
Voltage selection switch
Display
(All icons shown here are for information, and do not necessarily appear on
the PC).
11
1 System Overview
Specifications and Characteristic Data
Specifications and Characteristic Data
Physical Characteristics
System Processing Unit
DesktopMinitower
Weight9 kg (20 lbs)15 kg (33 lbs)
Dimensions44.6 cm (D) by 43.5 cm (W) by 13.2 cm (H)
17.5 inches by 17.1 inches by 5.2 inches
Footprint0.194 m
2
(2.08 sq ft)0.085 m2 (0.91 sq ft)
44 cm (D) by 19.2 cm (W) by 43.8 cm (H)
17.3 inches by 7.6 inches by 17.2 inches
Keyboard
Flat464 mm (W) by 178 mm (D) by 33 mm (H) (18.3 inches by 7 inches by 1.3 inches)
Standing464 mm (W) by 178 mm (D) by 51 mm (H) (18.3 inches by 7 inches by 2 inches)
with hard disk drive access)
Acoustic noise emission (operating
with flexible disk drive access)
Operating temperature+10°C to +40°C(+50°F to 104° F)
Recommended operating temperature+15°C to +40°C(+59°F to +104°F)
Storage temperature-40°C to +70°C(-40°F to +158°F)
Over temperature shutdown+50°C(+122°F)
Operating humidity15% to 80% (relative)
Storage humidity8% to 80% (relative), non-condensing at 40°C (104°F)
Operating altitude3100 m max(10000 ft max)
Storage altitude4600 m max(15000 ft max)
LwA < 41 dBLpA < 35 dB
LwA < 43 dBLpA < 38 dB
Operating temperature and humidity ranges may vary depending upon the
mass storage devices installed. High humidity levels can cause improper
operation of disk drives. Low humidity levels can aggravate static electricity
problems and cause excessive wear of the disk surface.
0.1 A
Max current at +12 V4.4 A
Max current at -12 V0.5 A0.1 A0.3 A
Max current at +5 Vst
1.
Dependant on operating system and PC configuration
0.05 A
1.5 A0.5 A
——
When the computer is turned off, but left plugged in at the mains, the power
consumption falls below 5 watts, but is not zero. If the computer is
completely unplugged from the mains, the real time clock continues to
operate from the charge stored in the battery. If the computer is left plugged
in, but not turned on, it continues to supply power to the real time clock,
and also keeps the battery recharged. The life-time of rechargeable batteries
is considerably extended by keeping them in a fully charged state.
The battery can be recharged by plugging the computer back in for at least
an hour. It is not necessary to start the computer.
14
1 System Overview
Documentation
Documentation
The table below summarizes the availability of documentation that is
appropriate to the HP Vectra VL 6/xxx Series 6 PCs. Only selected
publications are available on paper. Most are available as viewable files
(which can also be printed) from the HP division support servers, and on
the HP Support Assistant CD-ROM.
Division Support ServerSupport Assistant CD-ROMPaper-based
HP Vectra VL 6/xxx Series 6
User’s Guide
HP Vectra VL 6/xxx Series 6
Familiarization Guide
HP Vectra VL 6/xxx Series 6
Technical Reference Manual
HP Vectra PC Service
Handbook (Vol 1, 12th Edition)
HP Vectra Accessory Service
Handbook (7th Edition)
PDF filePDF file
PDF filePDF fileD5040-90901
PDF filePDF fileno
PDF filePDF fileTo be announced
PDF filePDF file5965-4074
DT
: D5040A
MT
: D5050A
Each PDF file (portable document format) can be viewed on the screen by
opening the file with Acrobat Reader. To print the document, press Ctrl+P
whilst you have the document on the screen. You can use the page-up, pagedown, goto page, search string functions to read the document on the
screen. (Note, though, that for some documents, there is difference
between the page number that is printed on the page, and the page number
that Acrobat Reader indicates, because of the presence of the front matter
pages).
15
1 System Overview
Documentation
Where to Find the Information
The following table summarizes the availability of information within the
HP Vectra VL 6/xxx Series 6 PC documentation set.
Opening the computerFull details
Supported accessoriesSome part number detailsFull PN details
Replacing accessoriesHow to installNew procedures
Configuring devicesConfiguring
Fields and their options
within Setup
TroubleshootingBasicNew symptomsService notesAdvanced
Technical informationBasicDetailedAdvanced
System boardJumpers, switches and
BIOSBasic detailsUpgradingTechnical details
Power-On Self-Test
routines (POST)
Keyboard, mouse, display,
network, printer, power
Finding READ.MEs and online documentation
Warranty information
connectors
Key error codes and
suggestions for corrective
action
comfort
S/w license
agreement
Upgrading the computer
peripherals
Repairing the computer
Familiarization
Guide
Jumpers, switches
and connectors
How to replace
Service
Handbook
Parts list
CPL dates
Jumpers,
switches and
connectors
Technical
Reference
Manual
Key features
System overview
Problem fixes
Key fields
Jumpers, switches
and connectors
Chip-set details
Memory maps
Order of tests
Complete list
16
2
System Board
The next chapter describes the graphics, disk and audio devices which are
supplied with the computer.
This chapter describes the components of the system board, taking in turn
the components of the Processor-Local Bus, the Peripheral Component
Interconnect (PCI) bus and the Industry Standard Architecture (ISA) bus.
17
2 System Board
System Board and Backplane Boards
System Board and Backplane Boards
Most desktop and minitower models are supplied with a Matrox graphics
controller on a PCI board, and do not have the integrated graphics controller
loaded on the system board.
Status Panel
A
A
B
Not Used
B
Power Connector
Memory Slots
C
C
Voltage Regulator Module
3.3 V Connector
342 mm
CD-ROM Connector
Flexible Disk Connector
Display
Hard Disk Connector
(Items shown in grey are
present only on models with
integrated graphics controller)
Graphics
Controller
Chip
VESA Connector
2
✕
Kbd
USB
Mou
Video Memory
Internal Speaker
External Start
Parallel PortSerial Port A
210 mm
Processor Slot
External Speaker Connector
System Board Switches
External Battery Connector
Serial Port B
18
2 System Board
System Board and Backplane Boards
Desktop (front view)
2 ✕ PCI slot (shown in white)
2 ✕ ISA/PCI combination slot
(shown in light grey)
1 ✕ system board slot (shown
in dark grey)
Desktop (rear view)
1 ✕ ISA slot (shown in grey)
PCI Slot #4 (J12)
PCI Slot #3 (J5)
PCI Slot #2 (J11)
PCI Slot #1 (J6)
Minitower (top view)
2 ✕ ISA slot (shown in grey)
2 ✕ PCI slot (shown in white)
2 ✕ ISA/PCI combination slot
(shown in light grey)
1 ✕ system board slot (shown
in dark grey)
PCI Slot #4 (J12)
PCI Slot #3 (J5)
PCI Slot #2 (J11)
PCI Slot #1 (J6)
19
2 System Board
Architectural View
Architectural View
Pentium II
Processor
L2 cache
memory
Processor-Local Bus
(64 bit, 60/66 MHz)
82441 FX
PL/PCI Bridge (PMC)
PL bus
interface
DBX
interface
PCI bus
interface
Memory
controller
Main
memory
82442 FX
Data bus accelerator (DBX)
PMC
interface
DRAM
interface
PCI Bus
(32 bit, 30/33 MHz)
82371 SB
PCI/ISA Bridge (PIIX3)
Interrupt
controller
PCI bus
interface
2✕USB
controller
DMA
controller
ISA bus
interface
2✕IDE
controller
Hard
disk
Serial
EEPROM
Little Ben
(HP ASIC)
ISA Bus
(16 bit, 7.5/8.25 MHz)
20
PL bus
interface
PCI bus
interface
CL5446 or Millennium II
Graphics controller
Keyboard
controller
Par alle l
controller
2✕serial
controller
System
ROM
PC87308
Super I/O
Mouse
controller
ISA bus
interface
FDD
Controller
Flexible
disk
2 System Board
Chip-Set
Chip-Set
The chip-set comprises four chips. These interface between the three main
buses (the Processor-Local bus, the PCI bus and the ISA bus).
•The PMC chip (82441FX) is a combined PL/PCI bridge and
main memory controller.
•The DBX chip (82442FX) is the data bus accelerator, implementing the
datapath between the processor local bus and main memory.
•The PIIX3 chip (82371SB) is a combined PCI/ISA bridge and IDE controller and USB controller.
•The Super I/O chip (37C932) is a combined serial interface and parallel
interface and keyboard controller and mouse controller and flexible
disk drive controller.
PL Bus Interface
PCI Bus Interface
The PMC, PL/PCI Bridge Chip (82441 FX)
This forms the bridge between the Processor Local Bus (PL Bus) and the
PCI Bus.
The PMC chip monitors each cycle that is initiated by the processor, and
forwards those to the PCI bus that are not targeted at the local memory. It
translates PL bus cycles into PCI bus cycles.
The chip supports the SMM mode of the Pentium processor, the CPU stop
clock hardware function, and the keyboard lock function. These are used by
the LittleBen chip, as described on page 34.
Sequential PL-to-PCI memory write cycles are translated into PCI zero wait
state burst cycles. The maximum PCI burst transfer can be between
256 bytes and 4 KB. The chip supports advanced snooping for PCI master
bursting, and provides a pre-fetch mechanism dedicated for IDE read.
The PCI arbiter supports PCI bus arbitration for up to four masters using a
rotating priority mechanism. Its hidden arbitration scheme minimizes
arbitration overhead.
21
2 System Board
Chip-Set
Main Memory Controller
DBX Interface
PMC Interface
PL Bus Interface
Data Path
The main memory controller supports up to 512 MB of dynamic random
access memory (DRAM), arranged in banks of any mixture of memory
capacities, provided that each bank contains a pair of identical single
interline memory modules (SIMMs). With the 32 MB module from HP, the
three banks on these PCs gives a total capacity of 192 MB. With a 64 MB
module from HP, it will give a total capacity of 384 MB.
The DBX chip, described next, is controlled by the PMC chip.
The DBX, Data Bus Accelerator Chip (82442 FX)
The DBX chip implements a 64-bit data path (not interleaved) between the
Processor-Local bus and main memory modules.
This unit takes the data from the Processor Local bus that is to be written to
the memory, and takes the data out to the Processor Local bus that has been
read from the memory.
Storage elements are provided for bidirectional data buffering among the
64-bit PL data bus, the 64/32-bit memory data bus, and the 32-bit PCI
address/data bus.
DRAM Interface
There are three FIFO (first-in first-out) queues, and one read buffer for the
paths between the PL, PCI, and Memory buses. This buffering is used,
partly, to smooth the differences in bandwidths between the three buses,
thereby improving the overall system performance. During bus operations
between the PL, PCI and Memory buses, the chip receives control signals
from the PMC, performs functions such as data latching, data forwarding to
the destination bus, and data assemble and disassemble.
Whilst accesses to the local memory are in progress, whether it be from the
PL or PCI bus, the PMC maintains control of the secondary cache, DRAMs,
and the datapath.
In the case of 66 MHz PL bus operation, memory accesses have a timing
pattern of 5-2-2-2 for a page-hit. This degrades to 8-2-2-2 for a row-miss,
and to 11-2-2-2 for a page-miss. When the banks have been filled in an
arbitrary order, back-to-back burst reads keep to the 5-2-2-2,5-2-2-2 timing
22
2 System Board
Chip-Set
pattern. When the banks have been filled contiguously (bank A, then bank
B, then bank C), back-to-back burst reads are improved to a 5-2-2-2,3-2-2-2
timing pattern.
The controller supports relocation of system management memory. It
supports a read cycle power saving mode, and a CAS before RAS Intelligent Refresh mode of operation, with a CAS# driving current that is
programmable.
The controller is fully configurable for the characteristics of the shadow
RAM (640 KB to 1 MB). It supports concurrent write back.
The PIIX3, PCI/ISA Bridge Chip (82371SB)
This chip is encapsulated in a 208 pin plastic quad flat pack (PQFP)
package.
PCI Bus Interface
ISA Bus Interface
IDE Controller
USB Controller
DMA Controller
This part of the chip is responsible for transferring data between the PCI bus
and the ISA expansion bus. It performs PCI-to-ISA, and ISA-to-PCI bus cycle
translation. It supports the Plug-and-Play mechanism. Data buffers are
provided, to isolate the PCI and ISA buses.
As well as accepting cycles from the PCI bus interface, and translating them
for the ISA bus, the ISA bus interface also requests the PCI master bridge to
generate PCI cycles on behalf of a DMA or ISA master. The ISA bus interface
contains a standard ISA bus controller and data buffering logic. It can
directly support six ISA slots without external data or address buffering.
The PCI master/slave IDE controller, supporting four devices, two on each of
two channels, is described on page 29.
The PCI USB controller, supporting two connectors, is described on page 30.
The seven channel DMA controller incorporates the functionality of two
82C37 DMA controllers. Channels 0 to 3 are for 8-bit DMA devices, while
channels 5 to 7 are for 16-bit devices (see page 67). The channels can be
programmed for any of the four transfer modes: the three active modes
(single, demand, block), can perform three different types of transfer: read,
write and verify. The address generation circuitry supports a 24-bit address
for DMA devices.
23
2 System Board
Chip-Set
Interrupt Controller
Counter / Timer
The sixteen channel interrupt controller incorporates the functionality of
two 82C59 interrupt controllers. The two controllers are cascaded, giving 14
external and two internal interrupt sources (see page 67).
The chip contains a three-channel 82C54 counter/timer. The counters use a
division of the 14.318 MHz OSC input as the clock source.
The SIO, Super I/O Controller (NS 87308)
The Super I/O chip (NS 87308) provides the control for two FDC devices,
two serial ports and one bidirectional multi-mode parallel port.
FunctionLogical device number
Flexible disk controller0 ??
Parallel port controller3 ??
UART1 controller4 ??
UART2 controller5 ??
RTC6 ??
Keyboard controller7 ??
Serial / parallel
communications ports
Mouse controller7 ??
General purpose I/O (GPIO)8 ??
The two 9-pin serial ports (whose pin layouts are depicted on page 55)
support RS-232-C and are buffered by 16550 UARTs, with 16 Byte FIFOs.
They can be programmed as COM1, COM2, COM3, COM4, or disabled.
The 25-pin parallel port (also depicted on page 55) is Centronics
compatible, supporting IEEE 1284. It can be programmed as LPT1, LPT2, or
disabled. It can operate in the following four modes:
Standard mode (PC/XT, PC/AT, and PS/2 compatible).
❒
Bidirectional mode (PC/XT, PC/AT, and PS/2 compatible).