HP VECTRA VE 5/XXX 4 User Manual

Technical Reference Manual
Hardware and BIOS

HP Vectra VE

5/xxx Series 4 PC

Notice

The information contained in this document is subject to change without notice.

Hewlett-Packard makes no warranty of any kind with regard to this
material, including, but not limited to, the implied warranties of
merchantability and fitness for a particular purpose.

Hewlett-Packard shall not be liable for errors contained herein or for incidental
or consequential damages in connection with the furnishing, performance, or use
of this material.

Hewlett-Packard assumes no responsibility for the use or reliability of its
software on equipment that is not furnished by Hewlett-Packard.

This document contains proprietary information that is protected by copyright.
All rights are reserved. No part of this document may be photocopied,
reproduced, or translated to another language without the prior written consent
of Hewlett-Packard Company.

Adobe

Microsoft®, Windows® and MS-DOS® are U.S. registered trademarks of

Pentium® is a U.S. registered trademark of Intel Corporation.

TM

is a trademark of Adobe Systems Incorporated which may be registered

in certain jurisdictions.

Microsoft Corporation.

Hewlett-Packard France
Commercial Desktop Computing Division
38053 Grenoble Cedex 9
France



1997 Hewlett-Packard Company

Preface

This manual is a technical reference and BIOS document for engineers and
technicians providing system level support. It is assumed that the reader
possesses a detailed understanding of AT-compatible microprocessor
functions and digital addressing techniques.

Technical information that is readily available from other sources, such as
manufacturer’s proprietary publications, has not been reproduced.

This manual contains summary information only. For additional reference
material, refer to the bibliography, on the next page.

Conventions

The following conventions are used throughout this manual to identify
specific numeric elements:

Hexadecimal numbers are identified by a lower case h.

❒

For example,

Binary numbers and bit patterns are identified by a lower case b.

❒

For example,

0FFFFFFFh or 32F5h

1101b or 10011011b

iii

Bibliography

HP Vectra VE 5/xxx Series 4 User’s Guide (D5570-90001).

❒

HP Vectra VE 5/xxx Series 4 Familiarization Guide (D5570-90901).

❒

HP Vectra VE 5/xxx Series 4 Online User’s Guide (online).

❒

HP Network Administrator’s Guide (online).

❒

HP Vectra Accessories Service Handbook - 7th edition

❒

(5965-4074).
HP Vectra PC Service Handbook (Volume 1) - 12th edition

❒

(to be announced).
HP Support Assistant CD-ROM (by subscription).

❒

The following Intel® publication provides more detailed information:

Pentium Microprocessor Data Sheet (241595-002)

❒

iv

Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

1 System Overview

Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Where to Find the Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 System Board

System Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Architectural View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chip-Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Bridge Chip (SiS5581) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Super I/O Chip (NS87317) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Devices on the Processor-Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . 24

The Intel Pentium Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Cache Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Main Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Devices on the PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Integrated Drive Electronics (IDE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Universal Serial Bus (USB) Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Devices on the ISA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Super I/O Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DRAFT v

Contents

3 Interface Devices and Mass-Storage Drives

S3 Trio 64V2 Graphics Controller Chip . . . . . . . . . . . . . . . . . . . . . . . . 34

Video Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Available Video Resolutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Audio Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Mass-Storage Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Hard Disk Drives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Flexible Disk Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

CD-ROM Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Connectors and Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4 Summary of the HP/Phoenix BIOS

HP/Phoenix BIOS Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Setup Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Advanced Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Security Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Power Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Power Saving and Ergonometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Desktop Management Interface (DMI) . . . . . . . . . . . . . . . . . . . . . . . . . . 52

HP Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Power-On from Space-Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

HP Off and Soft Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Remote Power-On (RPO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Advanced Power Management (APM) . . . . . . . . . . . . . . . . . . . . . . . . . . 55

BIOS Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

vi DRAFT

Contents

System Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Product Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

HP I/O Port Map (I/O Addresses Used by the System). . . . . . . . . . . . . . 59

5 Power-On Self-Test and Error Messages

Order in Which the Tests are Performed . . . . . . . . . . . . . . . . . . . . . . 66

Error Message Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Beep Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Lights on the Status Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Sonovision ITEP Documentation Project Checklist

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

DRAFT vii

Contents

viii DRAFT

1

System Overview

This manual describes the HP Vectra VE 5/xxx Series 4 PC, and provides
detailed system specifications.

This chapter introduces the external features, and summarizes the
documentation which is available.

9

Front view

Front view with cover
removed

1 System Overview

Package

Package

activity light
status light

(Multimedia models only)

Hard disk drive
24✕ CD-ROM drive
Flexible disk drive

Rear view

Main memory

Processor

Security lock hole

(All icons shown here are for information, and do not necessarily appear on
the PC).

Par al lel

Serial

Retaining brackets

USB

Display

Key boa rd

Mouse

10

1 System Overview

Documentation

Documentation

The table below summarizes the availability of documentation that is
appropriate to the HP Vectra VE 5/xxx Series 4 PC. Most are available as
viewable files (which can also be printed) from the HP division support
servers, and on the HP Support Assistant CD-ROM.

Preloaded on Hard

Disk

HP Vectra VE 5/xxx Series 4
User’s Guide

HP Vectra VE 5/xxx Series 4
Familiarization Guide

HP Vectra VE 5/xxx Series 4
Technical Reference Manual

HP Vectra PC Service
Handbook (Vol 1, 12th Edition)

HP Vectra Accessory Service
Handbook (7th Edition)

HP Vectra VE 5/xxx Series 4
Online User’s Guide

Network Administrators Guide no PDF file PDF file no

no PDF file PDF file D5570-90001

no PDF file PDF file D5570-90901

no PDF file PDF file no

no PDF file PDF file To be announced

no PDF file PDF file 5965-4074

HTML file PDF file PDF file no

Division Support

Server

Support Assistant CD-

ROM

Paper-based

Each PDF file (portable document format) can be viewed on the screen by
opening it with Acrobat Reader. To print the document, press Ctrl+P whilst
you have the document on the screen. You can use the page-up, page-down,
goto page, search string functions to read the document on the screen.
(Note, though, that for some documents there is difference between the
page number that is printed on the page, and the page number that Acrobat
Reader indicates, because of the presence of the front matter pages).

11

1 System Overview

Documentation

Where to Find the Information

The following table summarizes the availability of information within the
HP Vectra VE 5/xxx Series 4 PC documentation set. The user is supplied
with the online documentation preloaded on the PC, and the User’s Guide
(in paper form).

User Documentation Online Documentation Support Documentation

User’s

Guide

Product features

Key features
Exploring
New features
Exploded view
Parts list

Product model numbers

Product range
CPL dates

Setting Up the PC

Connecting cables
Turning on

Finding information

READ.MEs
On-line documentation

Environmental

System overview
Working in comfort x

Formal documents

Sw license agreement
Warranty information

Opening the computer x
Supported accessories

Full PN details
Selected PN details

Replacing accessories

Complete procedures
Selected procedures x x

xx

x
x

x
x

Upgrade

Guide

User Online

Introducing the computer

x

Using the computer

x

Upgrading the computer

Network

Admin.

Guide

Familiar-

ization

Guide

x

Service

Hand-book

x
x

x
x

x

Tech Ref

Manual

x

x

12

1 System Overview

Documentation

User Documentation Online Documentation Support Documentation

User’s

Guide

Upgrade

Guide

User Online

Network

Admin.

Guide

Familiar-

ization

Guide

Service

Hand-book

Configuring devices

Peripherals
Network

x

x

Problem fixes

The Setup program

Key fields x

Repairing the computer

Troubleshooting

Basic

xx
Advanced
New symptoms
Service notes

x

x

Technical information

Basic
Detailed

x

x

Advanced

System board

Jumpers & Switches
Connectors
Replacement

x
x

x
x

x
x

x

Chip-set

BIOS

Basic details

x
Technical details
Memory maps
Upgrading

x

Power-On Self-Test

Key error conditions

xx

Order of tests

Tech Ref

Manual

x

x

x

x
x

x

x
x
x

x

13

1 System Overview

Documentation

14

2

System Board

The next chapter describes the graphics, disk and network devices which
are supplied with the computer.

This chapter describes the components of the system board, taking in turn
the components of the Processor-Local Bus, the Peripheral Component
Interconnect (PCI) bus and the Industry Standard Architecture (ISA) bus.

15

2 System Board

System Board

System Board

System Board Switches

Status Panel
Connector

Ext. Start

280 mm

Flexible Disk Connector

Voltage Regulator

Primary IDE Connector

Secondary IDE Connector
PCI wake-up

connector

NS87317
Super I/O
controller

Power Connector

L2 cache

SiS 5581
PL/PCI bridge,
PCI/ISA bridge,
DRAM controller,
IDE+USB cntlr

1 2 3 4 5 6 7 8 9 10

Socket 7

Pentium Processor

L2 cache

VESA Connector

CR2032

Internal Speaker

External Speaker Connector

C

Ext. Batt.

3.3 V Conn

A

B

DIMM Memory Slots

16

Graphics
Controller

System ROM

Parallel Port Serial Port Display

Chip

2

✕

USB

210 mm

Video Memory

Kbd

Mou

Architectural View

2 System Board

Architectural View

SiS5581

PL/PCI bridge

PCI/ISA bridge

PL bus

interface

Cache

controller

Memory

controller

Data path

PCI bus

interface

2✕USB

controller

2✕IDE

controller

DMA

controller

Interrupt

controller

ISA bus

interface

Level-2

cache

Main

memory

Hard

disk

Serial

EEPROM

Graphics

controller

System

ROM

Pentium

processor

Keyboard
controller

Parallel

controller

2✕serial
controller

NS87317
Super I/O

Mouse

controller

FDD

controller

ISA bus

interface

Processor-Local Bus
(64 bit, 66 MHz)

PCI Bus
(32 bit, 33 MHz)

ISA Bus
(16 bit, 8.25 MHz)

17

2 System Board

Chip-Set

Chip-Set

The chip-set comprises two chips. These interface between the three main
buses (the Processor-Local bus, the PCI bus and the ISA bus).

• The Bridge chip (SiS5581) is a combined PL/PCI bridge and cache

controller and main memory controller and PCI/ISA bridge and IDE
controller and USB controller.

• The Super I/O chip (NS87317) is a combined serial interface and paral-
lel interface and keyboard controller and mouse controller and flexible
disk drive controller.

PL Bus Interface

PCI Bus Interface

Bridge Chip (SiS5581)

The bridges between the Processor Local Bus (PL Bus) and the PCI Bus,
and between the PCI Bus and the ISA Bus, are encapsulated in a 553-pin ball
grid array (BGA) package.

The chip monitors each cycle that is initiated by the processor, and forwards
those to the PCI bus that are not targeted at the local memory. It translates
PL bus cycles into PCI bus cycles.

The chip supports the SMM mode of the Pentium processor, the CPU stop
clock hardware function, and the keyboard lock function.

The chip-set is PCI 2.1 compliant, and provides for PCI Concurrency.
Concurrent data transfers that do not contest for the same resources (such
as processor to memory concurrent with PCI peer to peer, or processor to
ISA device concurrent with PCI device to memory) are allowed to interleave
their transfers.

The PCI arbiter supports PCI bus arbitration for up to four masters using a
rotating priority mechanism. Its hidden arbitration scheme minimizes
arbitration overhead.

ISA Bus Interface

As well as accepting cycles from the PCI bus interface, and translating them
for the ISA bus, the ISA bus interface also requests the PCI master bridge to
generate PCI cycles on behalf of a DMA or ISA master. The ISA bus interface
contains a standard ISA bus controller and data buffering logic, and can

18

support up to three ISA slots without any external buffering.

2 System Board

Chip-Set

Data Path

Level-2 Cache Memory
Controller

Storage elements are provided for bidirectional data buffering among the
64-bit PL data bus, the 64-bit memory data bus, and the 32-bit PCI address/
data bus. This buffering is used, partly, to smooth the differences in
bandwidths between the three buses, thereby improving the overall system
performance.

The Level-2 cache memory controller supports write back direct mapped
pipelined burst static RAM. On the HP Vectra VE 5/xxx Series 4 PC, 256KB
of write back cache memory is implemented as two 32K ✕ 32-bit chips
soldered on the system board. The 8-bit tag allows the lowermost 64 MB of
main memory to be cached (if more than 64 MB of main memory is installed,
accesses to the uppermost regions will be made directly to the main memory
modules, and not via the cache memory mechanism).

The cache memory line width is 32-bytes (256-bits), four times the width of
the Processor-Local data bus. Reads and writes always involve a full cache
line, and so require four back-to-back cycles on the bus. Since they involve
accesses to related addresses, they do not need four independent accesses
to main memory, but can be organized as a pipelined burst. The second,
third and fourth cycles in each burst require less time to complete than the
first, the first cycle having included the addressing phase and memory pre­charge timing. The read and write access timing has the pattern 3-1-1-1.
However, the timing for 64-byte burst reads can be even better than this (3­1-1-1,1-1-1-1 for a back-to-back burst read) provided that the main memory
banks have been filled contiguously.

Main Memory Controller

There are two programmable non-cacheable regions, with an option to
disable local memory in these regions. A 64 KB to 1 MB cache summary is
provided.

The main memory controller supports up to 384 MB of EDO, FPM or
SDRAM double interline memory modules (DIMMs). The HP Vectra VE 5/
xxx Series 4 PC supports three modules of SDRAM (synchronous dynamic
random access memory). With the 64 MB module from HP, this gives a
maximum total capacity of 192 MB.

In the case of 66 MHz PL bus operation, memory accesses have a timing
pattern of 6-1-1-1 for a page-hit. This degrades to 10-1-1-1 for a page-miss.

19

2 System Board

Chip-Set

IDE Controller

USB Controller

DMA Controller

Interrupt Controller

The PCI master/slave IDE controller, supporting four devices, two on each of
two channels, is described on page 26. As well as the traditional five PIO
modes (0 to 4) and three DMA modes (0 to 2), this controller also supports
three Ultra ATA/33, or Ultra DMA, modes (0 to 2), allowing peak transfer
rates up to 33 MB per second.

The PCI USB controller, supporting two connectors, is described on page 28.

The seven channel DMA controller incorporates the functionality of two
82C37 DMA controllers. Channels 0 to 3 are for 8-bit DMA devices, while
channels 5 to 7 are for 16-bit devices (as described on page 60). The
channels can be programmed for any of the four transfer modes: the three
active modes (single, demand, block), can perform three different types of
transfer: read, write and verify. The address generation circuitry can only
support a 24-bit address for DMA devices.

The sixteen channel interrupt controller incorporates the functionality of
two 82C59 interrupt controllers. The two controllers are cascaded, giving 14
external and two internal interrupt sources (as described on page 61).

Counter / Timer

The chip contains a three-channel 82C54 counter/timer. The counters use a
division of the 14.318 MHz OSC input as the clock source.

Super I/O Chip (

The Super I/O chip is contained within a 160-pin PQFP package. It includes
the following features:

• ACPI register set

• Five Power-On/SCI/SMI channels

• Two SMI channels

• Signal line to an external light

• Power-State bit for PIIX4-based designs.

The chip provides the control for the following devices.

Keyboard controller 0

20

NS87317

Function Logical device number

)

2 System Board

Function Logical device number

Mouse controller 1
RTC and Advance power supply controller (APC) 2
Flexible disk controller 3
Parallel port controller 4
UART2 and IR controller 5
UART1 controller 6
General purpose I/O (GPIO) 7
Power management 8

Chip-Set

Serial / parallel
communications ports

FDC

Keyboard and Mouse
Controller

The 9-pin serial port (whose pin layout is depicted on page 46) supports RS­232-C and is buffered by a 16550 UART, with a 16 Byte FIFO. It can be
programmed as COM1, COM2, COM3, COM4, or disabled.

The 25-pin parallel port (also depicted on page 46) is Centronics
compatible, supporting IEEE 1284. It can be programmed as LPT1, LPT2, or
disabled. It can operate the four modes:

Standard mode (PC/XT, PC/AT, and PS/2 compatible).

❒

Bidirectional mode (PC/XT, PC/AT, and PS/2 compatible).

❒

Enhanced mode (enhanced parallel port, EPP, compatible).

❒

High speed mode (MS/HP extended capabilities port, ECP, compatible).

❒

The integrated flexible drive controller (FDC) supports any combination
of two from the following: tape drives, 3.5-inch flexible disk drives, 5.25-inch
flexible disk drives. It is software and register compatible with the 82077AA,
and 100% IBM compatible.

The computer has an 8042-based keyboard and mouse controller. The
connector pin layouts are shown on page 46. The Power-on keyboard is
described on page 29.

RTC

The real-time clock (RTC) is 146818A-compatible. With an accuracy of
20 ppm (parts per million). The configuration RAM is implemented as 256
bytes of CMOS memory.

21

2 System Board

Chip-Set

Serial EEPROM

ACPI Support

General Purpose I/O

This is the non-volatile memory which holds the values for the Setup
program (they are no longer stored in the CMOS memory).

The Advanced Configuration and Power Interface (ACPI) provides a
system-wide approach to system and device power management that allows
the PC to be turned off, and yet remain sufficiently active to respond
immediately to user and network requests.

There are several general purpose I/O pins. Some of these are used to sense
the current settings of system board switches (as described on page 24 and
page 31).

Description GPIO number

Cache-sleep GPIO0
Screen blank GPIO1
Error light GPIO2
MA12 GPIO3
MA13 GPIO4
not connected GPIO5
Low power mode GPIO6
Clear product ID (connected to SW-10, open=1, closed=0) GPIO7
USB fuse GPIO8
IOCHK# GPIO9
Thermal input (OVERTEMP) GPIO10
Fan control (not used) GPIO11
Remote wake up (RWO) GPIO12
Keyboard and mouse lock (keyboard OR mouse IRQ) GPIO13
Pause light GPIO14
Remote power on (RPO) GPIO15
Start key (connected to SW-9, open=1, closed=0) GPIO16
Enable RPO GPIO17
Flash page select GPIO20
Bus core frequency BCF2 (connected to SW-5, always 1) GPIO21
POR# (ExtSMI) GPIO22

22

2 System Board

Description GPIO number

Flash program enable (FLASHLOCK) GPIO23
Backplane ID0 (always 1) GPIO24
Backplane ID1 (always 1) GPIO25
Bus core frequency BCF0 (connected to SW-3, open=1, closed=0) GPIO26
Bus core frequency BCF1 (connected to SW-4, open=1, closed=0) GPIO27
Host bus request detect (60/66 MHz) (connected to SW-1, always 0) GPIO30
Serial EEPROM data GPIO31
FDD write protect (not used) GPIO32
Password enable (connected to SW-7, open=1, closed=0) GPIO33
Clear CMOS (connected to SW-8, open=1, closed=0) GPIO34
Serial EEPROM chip select GPIO35
Serial EEPROM clock GPIO36

Chip-Set

23

2 System Board

Devices on the Processor-Local Bus

Devices on the Processor-Local Bus

The Intel Pentium Microprocessor

The Pentium processor is packaged in a pin-grid-array (PGA), and is
seated on the system board in a zero-insertion-force (ZIF) socket 7. Only
upgrades that are pin compatible with the original processor, manufactured
by Intel, are supported.

P54CS chips working at 166 and 200 MHz require between 3.45 and 3.60 V.
A VRE voltage regulator, integrated on the system board, actively derives
the voltage from the 3.3 V, 5 V and 0 V outlets of the power supply.

Processor Cooling

Bus Frequencies

The processor is cooled by two heat-sinks: one on the processor (as
normal), the other beside the system board. Surplus heat is carried from the
first to the second by a heat pipe.

Since it involves no moving mechanical parts, it is unlikely to fail, and so
involves no new support strategy.

Any thermal contact material between the parts and the heat-sinks must not
be removed or disturbed. The cooling needs of the processor are critical.

The location of the system board switches is shown in the diagram on page

16. Five of these switches (SW-1,2,3,4 and 5) determine the working

frequencies of the PC, as summarized in the table below. The uses of the
other switches are summarized on page 31.

There is a 14.318 MHz crystal oscillator on the system board. This frequency
is multiplied to 66 MHz by a phase locked loop. This is further scaled by an
internal clock multiplier within the processor. For example, the 200 MHz
processor multiplies the 66 MHz system clock by three. Switches 1 and 2, on
the system board switch bank, set the frequency of the Processor-Local bus.
Switches 3 and 4 set the clock multiplier ratio. The PCI bus works,
synchronously, at half the frequency of the PL bus. The ISA bus works,
synchronously, at a quarter of the frequency of the PCI bus.

You will need to change these switches if you exchange or replace the
system board during a repair, so as to match the speed to that of the
processor. The only type of processor upgrade that is supported by HP is to
replace the original processor by the correct Intel Overdrive. You will not
need to change the system board switches when doing this.

24

2 System Board

Devices on the Processor-Local Bus

Switch

Processor

Frequency

166 MHz

200 MHz

233 MHz

266 MHz

1.

1

1

Switch settings if these processor frequencies become available (MMX technology only).

12 34

Closed Open 66 MHz Closed Closed 2.5 : 1

Closed Open 66 MHz Open Closed 3 : 1

Closed Open 66 MHz Open Open 3.5 : 1

Closed Open 66 MHz Closed Open 4 : 1

Local Bus

Frequency

Switch Frequency

Ratio

Processor :

Local Bus

Cache Memory

The computer supports two levels of cache memory, each with a 32-byte line
width. The Level-1 (L1) cache memory is fabricated on the processor chip.
The Level-2 (L2) cache memory is a slower module on the system board.
Each acts as temporary storage for data and instructions from the main
memory. Since the system is likely to use the same, or adjacent, data several
times, it is faster to get it from the on-chip or on-board cache memory than
from the main memory.

The L1 cache memory is divided into two separate banks: an L1 I-cache for
instruction words, and an L1 D-cache for data words. Each has a capacity of
8KB.

The L2 cache memory is controlled by the Bridge chip in the system board
chip-set. On the HP Vectra VE 5/xxx Series 4 PC, 256 KB of direct
mapped, write-back, synchronous pipelined burst, 8.5 ns static random
access memory (SRAM) is integrated on the system board.

Main Memory

There are three main memory module sockets, arranged in three banks
(A to C). One bank is already occupied by the double interline memory
module (DIMM) that contains the 16 MB or 32 MB of memory that is
supplied with the computer.

Different banks can have different capacities (8, 16, 32 or 64 MB). The
banks should be filled in the order A, B, C. By installing a 64 MB DIMM in
every bank, the maximum capacity of 192 MB of main memory can be
attained.

25

2 System Board

Devices on the PCI Bus

Devices on the PCI Bus

PCI Device

PL/PCI bridge

PCI/ISA bridge 1 (01h) 0 26 — — — —

IDE controller

USB controller

Integrated graphics controller

PCI slot #1

PCI slot #2 10 (0Ah) — 21 D A B C

PCI slot #3

PCI slot #4

Device

Number

0 (00h) 0 11 — — — —

13 (0Dh) 0 24 A — — —

7 (07h) — 18 A B C D

6 (06h) — 17 C D A B

12 (0Ch) — 23 B C D A

Function AD[xx]

1 — — — —

2 — — — —

Chip-set Interrupt Connection

INTA INTB INTC INTD

The distribution of the interrupt lines is described more fully on page 62.

Integrated Drive Electronics (IDE)

The IDE controller is implemented as part of the Bridge chip. It is driven
from the PCI bus, and has PCI-Master capability. It supports Ultra ATA (also
known as Ultra DMA), Enhanced IDE (EIDE) and Standard IDE. To use the
Enhanced IDE features the drives must be compliant with Enhanced IDE.

Transfer Rates Versus
Modes of Operation

Up to four IDE devices are supported: two (one master and one slave)
connected to the primary channel, and two (one master and one slave) to
the secondary channel. A cable is supplied that provides a single connector
for one device to one channel.

The controller supports 32-bit Windows I/O transfers. Five PIO modes, three
DMA modes, and three Ultra ATA/33 modes are supported. The five
supported PIO modes allow the following transfer rates.

26

2 System Board

Devices on the PCI Bus

Mode 01234

Cycle time (ns) 600 383 240 180 120

Transfer rate (MB/s) 3.33 5.22 8.33 11.1 16.7

The three DMA modes (for single or double word) allow the following
transfer rates:

Mode 0 1 2

Cycle time (ns) 480 150 120

Transfer rate (MB/s) 4.2 13.3 16.7

The three Ultra ATA/33 modes (also know as Ultra DMA modes) allow the
following peak transfer rates:

Disk Capacity Versus
Modes of Addressing

Mode 0 1 2

Cycle time (ns) 144 75 60

Transfer rate (MB/s) 13.9 26.7 33.3

The amount of addressable space on a hard disk is limited by three factors:
the physical size of the hard disk, the addressing limit of the IDE hardware,
and the addressing limit of the BIOS. By performing a translation, the
Extended-CHS addressing scheme allows larger disk capacities to be
addressed than under CHS.

Cylinders per

Device

CHS 64 16 1024 512 528 M

ECHS 64 256 1024 512 8.4 G

LBA - - 256 M (=2

Heads per

Cylinder

Sectors per Track

28

) 512 137 G

Bytes per

Sector

Bytes per

Device

27

2 System Board

Devices on the PCI Bus

Universal Serial Bus (USB) Controller

The OpenHCI USB controller (USB release 1.0) is implemented as part of
the Bridge chip. It is driven from the PCI bus, and provides support for the
two stacked USB connectors on the back panel. Over-current detection and
protection is provided, but shared between the two ports. The specification
is as follows:

• 12 M bps (bits per second) transfer rate

• Supports up to 127 devices (maximum)

• Isochronous and asynchronous data transfer support

• Up to 5 m per cable segment

• Built in power distribution

• Supports daisy-chaining through a tiered-star, multi-drop topology (up to
6 tiers)

USB works only if the USB interface has been enabled within the HP Setup
program. Currently, only the Microsoft Windows 95 SR 2.1 operating system
provides support for the USB. This operating system is preloaded on the
hard disk of most models of this computer.

28

Devices on the ISA Bus

ISA Device Index Data

2 System Board

Devices on the ISA Bus

Super I/O

X Ben (HP ASIC)

2Eh 2Fh

496h 497h

Super I/O Controller

The Super I/O chip (NS87317) is part of the chip set, and is described on
page 20.

The computer is supplied with a Logitech 2-button mouse, and a keyboard
with the following features:

Space bar power on, to start the computer from the Off state (if

❒

from keyboard

Windows key (next to the keys), which has the same effect as

❒

is enabled in the Setup program).

power on

clicking the “Start” button on the Windows 95 task bar.
Pull-down key (next to the right key), which has the same effect as

❒

clicking the right mouse button.

Serial EEPROM

The computer uses 4 Kbit of Serial EEPROM implemented within a single
512 K✕8-bit ROM chip. Serial EEPROM is ROM in which one byte at a time
can be returned to its unprogrammed state by the application of appropriate
electrical signals. In effect, it can be made to behave like very slow, non­volatile RAM. It is used for storing the tatoo string, the serial number, and
the parameter settings for the Setup program.

When installing a new system board, the Serial EEPROM will have a blank
serial number field. This will be detected automatically by the BIOS, which
will then prompt the user to enter the serial number which is printed on the
identification label on the back of the computer.

29

2 System Board

Devices on the ISA Bus

Flash EEPROM (the System ROM)

The computer uses 256 KB of Flash EEPROM implemented within a single
256 K✕8-bit ROM chip (or in two 128 K✕8-bit chips). Flash EEPROM is
ROM in which the whole memory can be returned to its unprogrammed
state by the application of appropriate electrical signals to its pins. It can
then be reprogrammed with the latest firmware.

The System ROM contains: 64 KB of system BIOS (including the boot code,
the ISA and PCI initialization, RPO, DMI, the Setup program and the Power­On Self-Test routines, plus their error messages); 32 KB of video BIOS;
32 KB of Plug-and-Play code; and 32 KB of power management code. The
functions of these are summarized in Chapters 4 and 5.

Updating the System ROM

The System ROM can be updated with the latest BIOS. This can be
downloaded, as a compressed file, from the HP Electronic Services
(

http://www.hp.com/go/vectrasupport

since the utility which is supplied for a different model cannot be used with
this one. (More information is given in the “Hewlett-Packard Support and
Information Services” chapter in the User’s Guide that was supplied with
the computer).

There are two methods for flashing the BIOS.

Under the first method, the file can be downloaded to the system
administrator’s PC, and then to the target PC. The compressed file can be
executed, causing it to be expanded, creating a number of files, including:

• the Flash EEPROM reprogramming utility programs,

phlash.exe

• the BIOS upgrade file,

• the binary file,

• the batch file,

• a number of

PFMHE102.bin

flash.bat

*.txt

BIOS, and instructions on how to install it.

). You must specify the model of the computer

phlash32.exe

HHxxxx.FUL

and

files, giving information about the new version of the

The

PHLASH32.EXE

file can then be executed from within the Windows

operating system on the target PC.

30

2 System Board

Devices on the ISA Bus

The second method is to copy the above files to a system diskette, to re-boot
the PC from the flexible disk drive, and to run the

PHLASH.EXE

program.

Do not switch off the computer until the system BIOS update procedure has
completed, successfully or not. To do so could cause irrecoverable damage
to the ROM, thereby requiring the replacement of the system board. The
control panel switches are automatically disabled to prevent accidental
interruption of the flash programming process, but this, of course, does not
protect against deliberate or inadvertent removal of the power cord, or
other types of power failure, however caused.

If the flashing process goes wrong, insert a system diskette containing the
new BIOS and its associated files. Close the “clear password” and “clear
CMOS” switches (SW-7 and SW-8) on the system board, reconnect the PC
and turn it on. This forces the PC to re-boot from the flexible disk drive.
Once the recovery program has completed, the BIOS can be flashed by run­ning the

PHLASH.EXE

program. Once completed, return the system board

switches to their original positions.

System Board Switches

Five of the system board switches (whose location is shown on page 16) set
the working frequencies for the computer, as summarized on page 24. The
others set the configuration for the computer, as summarized in the
following table.

Switch Function Default

1-4 - Bus frequencies (see the table on page 24) -

5, 6 Open Not used Open

Open Normal operation

7

Closed Clears User and Administrator passwords

Open Normal operation

8

Closed Clears CMOS (to reload the Setup program defaults)

Open Disables keyboard power-on

9

Closed Normal operation

Open Normal operation

10

Closed Clears product identification field

Open

Open

Closed

Open

31

2 System Board

Devices on the ISA Bus

By setting switch SW8 in the

Closed

position, not only is the configuration
data cleared (in the CMOS memory and the Serial EEPROM), but also all the
Plug-and-Play data that had been saved in the Serial EEPROM. However,
the serial number, the tattooing string, the date and the time are each
retained.

By setting switch SW9 in the

Closed

position, the Power-On Space-Bar

function is enabled. Note, though, that it must also be enabled in the

Power-On Space-Bar

Turning the computer on, with switch SW10 in the

field of the Power Menu in the Setup program.

Closed

position, clears
the product identification field in the BIOS, and causes the computer to
prompt for the new information. By identifying the product correctly (after
replacing a defective system board by a new one), the BIOS is able to tailor
itself for the particular product, and to enable the appropriate features.

Updating the BIOS Before Considering Replacing the System Board

If the computer is faulty, but it starts up correctly, and the fault is not clearly
due to the system board hardware, then it is advisable to check the BIOS
version number. The BIOS version number can be found from the summary
screen, or the Setup program, obtained by pressing or , respectively,
when the computer has just been restarted, as described in Chapter 4.

If it is not the current version of the BIOS, the System ROM should be
flashed with the new version, as described on the previous page. The
computer should then be re-run to see if this has cleared the problem.

32

3

Interface Devices and Mass-Storage Drives

This chapter describes the graphics, mass storage and network devices
which are supplied with the computer. It also summarizes the pin connec­tions on the internal and external connectors.

33

3 Interface Devices and Mass-Storage Drives

S3 Trio 64V2 Graphics Controller Chip

S3 Trio 64V2 Graphics Controller Chip

All models are supplied with a graphics controller chip integrated on the
system board. This 64-bit PCI Ultra VGA graphics controller can be
characterized as follows:

®

• 100% compatible with IBM

• 64-bit video memory access with 2 MB, 50 ns, EDO, video DRAM (this is

not upgradeable since it is already fitted to capacity).

• integrated 24-bit RAMDAC

• fully programmable Pixel Clock Generator up to 170 MHz

VGA display standard

• 60 MHz clock for video memory

• fast linear addressing with full software relocation

• green power saving features

• playback acceleration, continuous interpolation on X, continuous interpo-

lation on Y

• DDC 2B compliant.

Video Modes

Standard and Enhanced Video Graphics Array (VGA) modes are available.
Hardware acceleration of graphical user interface (GUI) operations is
provided, and acceleration for 8, 16 and 32-bit pixel depths.

The table, on the following page, details the standard VGA modes which are
currently implemented in the video BIOS. These modes are supported by
standard BIOS functions. The video BIOS (which is mapped contiguously in
the address range C0000h to C7FFFh) contains all the routines required to
configure and access the graphics subsystem.

34

3 Interface Devices and Mass-Storage Drives

Standard VGA Modes

S3 Trio 64V2 Graphics Controller Chip

Mode No. Standard

00h VGA text 40 x 25 chars b/w 70 31.5 25.175

00h* VGA text 40 x 25 chars b/w 70 31.5 25.175

00h+ VGA text 40 x 25 chars b/w 70 31.5 28.322

01h VGA text 40 x 25 chars 16 70 31.5 25.175

01h* VGA text 40 x 25 chars 16 70 31.5 25.175

01h+ VGA text 40 x 25 chars 16 70 31.5 28.322

02h VGA text 80 x 25 chars b/w 70 31.5 25.175

02h* VGA text 80 x 25 chars b/w 70 31.5 25.175

02h+ VGA text 80 x 25 chars b/w 70 31.5 28.322

03h VGA text 80 x 25 chars 16 70 31.5 25.175

03h* VGA text 80 x 25 chars 16 70 31.5 25.175

03h+ VGA text 80 x 25 chars 16 70 31.5 28.322

04h VGA graphics 320 x 200 4 70 31.5 25.175
05h VGA graphics 320 x 200 4 70 31.5 25.175
06h VGA graphics 640 x 200 2 70 31.5 25.175
07h VGA text 80 x 25 chars b/w 70 31.5 28.322

07h+ VGA text 80 x 25 chars b/w 70 31.5 28.322

0Dh VGA graphics 320 x 200 16 70 31.5 25.175
0Eh VGA graphics 640 x 200 16 70 31.5 25.175
0Fh VGA graphics 640 x 350 b/w 70 31.5 25.175
10h VGA graphics 640 x 350 16 70 31.5 25.175
11h VGA graphics 640 x 480 2 60 31.5 25.175
12h VGA graphics 640 x 480 16 60 31.5 25.175
13h VGA graphics 320 x 200 256 70 31.5 25.175

Interface

Type

Resolution

No. of

Colors

Vertical
Refresh

(Hz)

Horizontal

Refresh

(kHz)

Dot Clock

(MHz)

The extended modes supported by the video BIOS are listed in the table on
the following page.

35

3 Interface Devices and Mass-Storage Drives

S3 Trio 64V2 Graphics Controller Chip

Extended Video Modes

Extended
Mode No.

4Eh 207h graphics 1152 x 864 256 60 55 80.000
4Fh 208h graphics 1280 x 1024 8 60 63.7 110.000
51h 212h graphics 640 x 480 16.7 M 60 31.5 25.000
52h 213h graphics 640 x 400 16.7 M 70 31.5 25.000
54h 10Ah text 132 x 43 chars 16 70 31.5 40.000
55h 109h text 132 x 25 chars 16 70 31.5 40.000
65h 10Dh graphics 320 x 200 32,768 70 12.540
66h 10Eh graphics 320 x 200 65,536 70 12.540
67h 10Fh graphics 320 x 200 16.7 M 70 12.540
68h 100h graphics 640 x 400 256 70 31.5 25.175
69h 101h graphics 640 x 480 256 60 31.5 25.175
69h 101h graphics 640 x 480 256 72 37.9 31.500
69h 101h graphics 640 x 480 256 75 37.5 31.500
69h 101h graphics 640 x 480 256 85 45 36.000
6Ah 102h graphics 800 x 600 16 60 37.9 40.000
6Ah 102h graphics 800 x 600 16 72 48.1 50.000
6Ah 102h graphics 800 x 600 16 75 47.5 49.500
6Ah 102h graphics 800 x 600 16 85 53.6 56.000
6Bh 103h graphics 800 x 600 256 60 37.9 40.000
6Bh 103h graphics 800 x 600 256 72 48.1 50.000
6Bh 103h graphics 800 x 600 256 75 46.8 49.500
6Bh 103h graphics 800 x 600 256 85 53.6 56.000
6Ch 104h graphics 1024 x 768 16 60 48.4 65.000
6Ch 104h graphics 1024 x 768 16 70 56.5 75.000
6Ch 104h graphics 1024 x 768 16 75 60.2 80.000
6Ch 104h graphics 1024 x 768 16 85 68.7 95.000
6Dh 105h graphics 1024 x 768 256 60 48.4 65.000
6Dh 105h graphics 1024 x 768 256 70 56.5 75.000
6Dh 105h graphics 1024 x 768 256 75 60.0 80.000
6Dh 105h graphics 1024 x 768 256 85 68.7 95.000
6Eh 106h graphics 1280 x 1024 16 60 110.000
6Fh 107h graphics 1280 x 1024 256 60 65 55.000
6Fh 107h graphics 1280 x 1024 256 72 77.7 65.000
6Fh 107h graphics 1280 x 1024 256 75 79.5 67.000
70h 110h graphics 640 x 480 32,768 60 31.5 25.175
70h 110h graphics 640 x 480 32,768 72 37.5 31.500
70h 110h graphics 640 x 480 32,768 75 37.5 31.500
70h 110h graphics 640 x 480 32,768 85 45 36.000

VESA

Mode No.

Interface

Type

Resolution

No. of

Colors

Vertical
Refresh

(Hz)

Horizontal

Refresh

(kHz)

Dot Clock

(MHz)

36

3 Interface Devices and Mass-Storage Drives

S3 Trio 64V2 Graphics Controller Chip

Extended
Mode No.

71h 111h graphics 640 x 480 65,536 60 31.5 25.175
71h 111h graphics 640 x 480 65,536 72 37.5 31.500
71h 111h graphics 640 x 480 65,536 75 37.5 31.500
71h 111h graphics 640 x 480 65,536 85 45 36.000
72h 112h graphics 640 x 480 16.7 M 60 31.5 25.175
72h 112h graphics 640 x 480 16.7 M 72 37.9 31.500
72h 112h graphics 640 x 480 16.7 M 75 37.5 31.500
72h 112h graphics 640 x 480 16.7 M 85 45 36.000
73h 113h graphics 800 x 600 32,768 60 37.9 40.000
73h 113h graphics 800 x 600 32,768 72 48.1 50.000
73h 113h graphics 800 x 600 32,768 75 46.8 49.500
73h 113h graphics 800 x 600 32,768 85 53.6 57.000
74h 114h graphics 800 x 600 65,536 60 37.9 40.000
74h 114h graphics 800 x 600 65,536 72 48.1 50.000
74h 114h graphics 800 x 600 65,536 75 46.8 49.500
74h 114h graphics 800 x 600 65,536 85 53.6 57.000
75h 115h graphics 800 x 600 16.7 M 60 37.9 40.000
75h 115h graphics 800 x 600 16.7 M 72 41.8 50.000
75h 115h graphics 800 x 600 16.7 M 75 46.8 49.500
75h 115h graphics 800 x 600 16.7 M 85 53.6 57.000
76h 116h graphics 1024 x 768 32,768 60 48.9 65.000
76h 116h graphics 1024 x 768 32,768 70 56.5 75.000
76h 116h graphics 1024 x 768 32,768 75 60.2 80.000
76h 116h graphics 1024 x 768 32,768 85 68.7 95.000
77h 117h graphics 1024 x 768 65,536 60 48.9 65.000
77h 117h graphics 1024 x 768 65,536 70 56.5 75.000
77h 117h graphics 1024 x 768 65,536 75 60.2 80.000
77h 117h graphics 1024 x 768 65,536 85 68.7 95.000
7Ch 120h graphics 1600 x 1200 256 48.5i 62.00 67.000

VESA

Mode No.

Interface

Type

Resolution

No. of

Colors

Vertical
Refresh

(Hz)

Horizontal

Refresh

(kHz)

Dot Clock

(MHz)

37

3 Interface Devices and Mass-Storage Drives

S3 Trio 64V2 Graphics Controller Chip

Available Video Resolutions

The following table lists the available video resolutions using these drivers.
The available resolutions may be different with later versions of each of
these drivers.

Resolution Number of colors Refresh Rate (Hz)

Windows NT 640 x 480

800 x 600 256, 64K, 16M 60, 72, 75, 85

1024 x 768 256, 64K i43

1280 x 1024 256 i451, 60, 75, 85

1600 x 1200 256 i48

Windows 95 640 x 480

800 x 600 16, 256, 64K, 16M 60, 72, 75, 85

1024 x 768 256, 64K 60, 70, 75, 85

1280 x 1024 256 60, 75, 85

1600 x 1200 256 60

Windows 3.11 640 x 480

800 x 600 256, 32K, 64K, 16M 60, 72, 75, 85

1024 x 768 256, 32K, 64K 60, 70, 75, 85

16
256, 64K, 16M

16
256, 64K, 16M

16
256, 32K, 64K, 16M

60
60, 72, 75, 85

1

, 60, 70, 75, 85

1

, 60

60
60, 72, 75, 85

60
60, 72, 75, 85

1280 x 1024 256 60, 75, 85

1

1600 x 1200 256 i48

1.

Interlaced.

If Video Plug and Play is

Setup

will automatically configure the best refresh rate. For non DDC

enabled

monitors, or when video Plug and Play is
changed in

Setup

.

in

Setup

, and a DDC monitor is detected,

disabled

, refresh rates can be

, 60

The number of colors supported is limited by the graphics board and the
video RAM. The resolution/refresh-rate combination is limited by a
combination of the display, the graphics board, and the video RAM.

38

3 Interface Devices and Mass-Storage Drives

S3 Trio 64V2 Graphics Controller Chip

Connectors

The layout of the pins for the DB15 VGA socket is depicted on page 46.

The Video Electronics Standards Association (VESA) defines a standard
video connector, variously known as the VESA

auxiliary

connector, or

pass-through

connector. This connector (whose
pin names are listed in a table on page 42) is integrated on the system board,
and is connected directly to the pixel data bus and the synchronization
signals.

feature

connector,

The graphics controller supports an output-only VESA
VGA mode. It is disabled by default and must be enabled in the

feature

connector in

Setup

program. Use of the VESA feature connector will disable 1 MB of the video
memory; with access only to the remaining 1 MB of video memory, some of
the video resolutions will not be available.

39

3 Interface Devices and Mass-Storage Drives

Audio Controller

Audio Controller

The Aztech audio interface, supplied on some models in an ISA slot, is
SoundBlaster Pro compatible and can be characterized as follows:

• line-out (stereo) jack: 20 Hz to 20 kHz frequency response, 83 dB signal
to noise ratio, 0.2% total harmonic distortion

• headphones jack: 2 W PMPO per channel, 32Ω load

• speaker connector: 0.2% total harmonic distortion

• line-in (stereo) jack: 15 kΩ, 0 V to 2 V peak-to-peak

• CD audio-in connector: 15 kΩ, 0 V to 2 V peak-to-peak

• microphone input: 600Ω, dynamic, 30 mV to 200 mV peak-to-peak

• MIDI /joystick interface connector: MPU-401 UART compatible

• 8-bit and 16-bit stereo sampling: 5 kHz to 48 kHz

• Integrated OPL3 FM synthesizer: 20 polyphonic voices

• typical electrical current: +5 V (250 mA), +12 V (250 mA), -12 V (50 mA)

Telephone answering device connector

AUX-IN connector

Multimedia control panel

microphone connector

Multimedia control panel connector

The board is compliant with Microsoft PC 95 revised / PC 96 / PC 97. It has a
full duplex codec, and supports a volume control on the front panel.

CD audio connector
Line-In

MIC-In

Line-Out
Speaker-Out
Internal speaker connector

Joystick connector

40

3 Interface Devices and Mass-Storage Drives

Mass-Storage Drives

Mass-Storage Drives

The IDE controller is described on page 26. The flexible disk controller is
described on page 21.

Hard Disk Drives

A 3.5-inch hard disk drive is supplied on an internal shelf in some models.

3.2 GB IDE 2.1 GB IDE 1 GB IDE

HP product number D2677A D2678A D2679A
Manufacturer Quantum Quantum Seagate

Flexible Disk Drives

A 3.5-inch, 1.44 MB bezelless flexible disk drive (D2035-63172) is mounted
vertically on the right hand side of the front panel.

CD-ROM Drives

Most models have a 24✕ Max IDE CD-ROM drive (D4383A) supplied in a

5.25-inch front-access shelf.

24✕ Max IDE

HP product number D4383A
Manufacturer Panasonic
Formatted storage capacity 650 MB

If a disk is still in the drive after power failure or drive failure, the disk can
be reclaimed by inserting a stout wire, such as the end of a straightened
paper-clip, into the small hole at the bottom of the door.

In order to allow correct CD-ROM drive detection by the
leave the device configuration jumper on the rear connector in the cable
select (CS) or master (MA) positions.

Setup

program,

41

3 Interface Devices and Mass-Storage Drives

Connectors and Sockets

Connectors and Sockets

IDE Hard Disk Drive Data Connector Flexible Disk Drive Data Connector

Pin Signal Pin Signal Pin Signal Pin Signal

1 Reset# 2 Ground 1 Ground 2 LDENSEL#
3 HD7 4 HD8 3 Ground 4 Microfloppy
5 HD6 6 HD9 5 Ground 6 EDENSEL
7 HD5 8 HD10 7 Ground 8 INDX#

9 HD4 10 HD11 9 Ground 10 MTEN1#
11 HD3 12 HD12 11 Ground 12 DRSEL0#
13 HD2 14 HD13 13 Ground 14 DRSEL1#
15 HD1 16 HD14 15 Ground 16 DTEN0#
17 HD0 18 HD15 17 Ground 18 DIR#
19 Ground 20 orientation key 19 Ground 20 STP#
21 DMARQ 22 Ground 21 Ground 22 WRDATA#
23 DIOW# 24 Ground 23 Ground 24 WREN#
25 DIOR# 26 Ground 25 Ground 26 TRK0#
27 IORDY 28 SPSYNC:CSEL 27 Ground 28 WRPRDT#
29 DMACK# 30 Ground 29 Ground 30 RDDATA#
31 INTRQ 32 IOCS16# 31 Ground 32 HDSEL1#
33 DA1 34 PDIAG# 33 Ground 34 DSKCHG#
35 DA0 36 DA2
37 CS0# 38 CS1#
39 DASP# 40 Ground

42

Status Panel Connector

Pin Signal Pin Signal

1 LCK_LED_K 2 LCK_LED_A
3 PWR_LED_K 4 PWR_LED_A
5 not connected 6 common
7 Push_On 8 RED_LED_A

9 HDD_LED_K 10 HDD_LED_A
11 _Reset 12 Ground
13 LCK_PUSH2 14 LCK_PUSH2

External Start and Remote Start Connectors

Pin Signal Pin Signal

1 ExternalStart 2 Ground

3 Wake1# 4 Wake2#

5 not connected 6 Wake3#

7 PowerGood 8 not connected

9 Vstandby 10 orientation key

Audio Board Connectors

3 Interface Devices and Mass-Storage Drives

Connectors and Sockets

Telephone Answering Device Connector CD Audio Connector

Pin Signal Pin Signal Pin Signal

1 Analog ground 2 orientation key 1 Ground
3 Line-in 4 Analog ground 2 Left channel
5 Line-out (left) 6 Analog ground 3 Ground
7 Line-out (right) 8 Modem speaker 4 Right channel
9 Analog ground 10 Microphone in

Aux-In Connector Front Panel Connector

Pin Signal Pin Signal Pin Signal

1 Left channel 1 Ground 2 orientation key
2 Ground 3 Headphones left 4 Head return left
3 Ground 5 Headphones right 6 Head return right
4 Right channel 7 Volume low limit 8 Volume DC cntl

9 Volume high limit 10 not used

Int. Speaker Connector Microphone Connector

Pin Signal Pin Signal

1 Power signal out 2nd ring: 3 Signal and power
2 Analog ground 3rd ring: 2 Ground

1st ring: 1 Signal and power

43

3 Interface Devices and Mass-Storage Drives

Connectors and Sockets

PCI Connector

Pin Signal Pin Signal Pin Signal Pin Signal

B1 -12 V A1 TRST# B47 AD[12] A47 AD[11]
B2 TCK A2 +12 V B48 AD[10] A48 Ground
B3 Ground A3 TMS B49 +3.3 V A49 AD[09]
B4 TDO A4 TDI B50 AD[08] A50 C/BE#[0]
B5 +5 V A5 +5 V B51 AD[07] A51 +3.3 V
B6 +5 V A6 INTA# B52 Ground A52 AD[06]
B7 INTB# A7 INTC# B53 AD[05] A53 AD[04]
B8 INTD# A8 +5 V B54 AD[03] A54 Ground

B9 Ground A9 reserved B55 Ground A55 AD[02]
B10 reserved A10 PRSNT# B56 AD[01] A56 AD[00]
B11 +3.3 V A11 reserved B57 +5 V A57 +5 V

orientation key orientation key B58 +5 V A58 +5 V
B12 reserved A12 reserved B59 +5 V A59 +5 V
B13 Ground A13 RESET# B60 ACK64# A60 REQ64#
B14 CLK A14 +3.3 V orientation key orientation key
B15 Ground A15 GNT# B61 reserved A61 Ground
B16 REQ# A16 Ground B62 Ground A62 C/BE#[7]
B17 +3.3 V A17 reserved B63 C/BE#[5] A63 C/BE#[6]
B18 AD[31] A18 AD[30] B64 C/BE#[4] A64 +3.3 V
B19 AD[29] A19 Ground B65 Ground A65 PAR64
B20 Ground A20 AD[28] B66 AD[63] A66 AD[62]
B21 AD[27] A21 AD[26] B67 AD[61] A67 Ground
B22 AD[25] A22 +3.3 V B68 +3.3 V A68 AD[60]
B23 Ground A23 AD[24] B69 AD[59] A69 AD[58]
B24 C/BE#[3] A24 IDSEL B70 AD[57] A70 Ground
B25 AD[23] A25 Ground B71 Ground A71 AD[56]
B26 +3.3 V A26 AD[22] B72 AD[55] A72 AD[54]
B27 AD[21] A27 AD[20] B73 AD[53] A73 +3.3 V
B28 AD[19] A28 Ground B74 Ground A74 AD[52]
B29 Ground A29 AD[18] B75 AD[51] A75 AD[50]
B30 AD[17] A30 AD[16] B76 AD[49] A76 Ground
B31 C/BE#[2] A31 +3.3 V B77 +3.3 V A77 AD[48]
B32 Ground A32 FRAME# B78 AD[47] A78 AD[46]
B33 IRDY# A33 Ground B79 AD[45] A79 Ground
B34 +3.3 V A34 TRDY# B80 Ground A80 AD[44]
B35 DEVSEL# A35 Ground B81 AD[43] A81 AD[42]
B36 Ground A36 STOP# B82 AD[41] A82 +3.3 V
B37 LOCK# A37 +3.3 V B83 Ground A83 AD[40]
B38 PERR# A38 SDONE B84 AD[39] A84 AD[38]
B39 Ground A39 SBO# B85 AD[37] A85 Ground
B40 SERR# A40 Ground B86 +3.3 V A86 AD[36]
B41 +3.3 V A41 C/BE#[1] B87 AD[35] A87 AD[34]
B42 AD[15] A42 PAR B88 AD[33] A88 Ground
B43 +3.3 V A43 +3.3 V B89 Ground A89 AD[32]
B44 +3.3 V A44 +3.3 V B90 reserved A90 reserved
B45 AD[14] A45 +3.3 V B91 reserved A91 Ground
B46 Ground A46 AD[13] B92 Ground A92 reserved

44

16-bit ISA Connector

(8-bit ISA uses the A and B connectors)

Pin Signal Pin Signal

B1 Ground A1 CHCHK#
B2 RESDRV A2 SD7
B3 +5 V A3 SD6
B4 IRQ9 A4 SD5
B5 -5 V A5 SD4
B6 DRQ2 A6 SD3
B7 -12 V A7 SD2
B8 NOWS# A8 SD1

B9 + 12 V A9 SD0
B10 Ground A10 CHRDY
B11 SMWTC# A11 AENx
B12 SMRDC# A12 SA19
B13 IOWC# A13 SA18
B14 IORC# A14 SA17
B15 DEK3# A15 SA16
B16 DRQ3 A16 SA15
B17 DAK1# A17 SA14
B18 DRQ1 A18 SA13
B19 REFRESH# A19 SA12
B20 BCLK A20 SA11
B21 IRQ7 A21 SA10
B22 IRQ6 A22 SA9
B23 IRQ5 A23 SA8
B24 IRQ4 A24 SA7
B25 IRQ3 A25 SA6
B26 DAK2# A26 SA5
B27 TC A27 SA4
B28 BALE A28 SA3
B29 +5 V A29 SA2
B30 OSC A30 SA1
B31 Ground A31 SA0

3 Interface Devices and Mass-Storage Drives

Connectors and Sockets

D1 M16# C1 SBHE#

D2 IO16# C2 LA23

D3 IRQ10 C3 LA22

D4 IRQ11 C4 LA21

D5 IRQ12 C5 LA20

D6 IRQ15 C6 LA19

D7 IRQ14 C7 LA18

D8 DAK0# C8 LA17

D9 DRQ0 C9 MRDC#
D10DAK5# C10MWTC#
D11 DRQ5 C11 SD8
D12DAK6# C12SD9
D13 DRQ6 C13 SD10
D14DAK7# C14SD11
D15 DRQ7 C15 SD12
D16 +5 V C16 SD13
D17 MASTER16# C17 SD14
D18 Ground C18 SD15

45

3 Interface Devices and Mass-Storage Drives

Connectors and Sockets

Socket Pin Layouts

Power Supply Connector for System Board

Pin Signal Pin Signal Pin Signal Pin Signal

1 PwrGood 8 +5 Vstdby 1 Ground 4 +3.3 V supply
2 orientation key 9 +5 V supply 2 Ground 5 +3.3 V supply
3 Remote_On 10 +5 V supply 3 Ground 6 +3.3 V supply
4 Ground 11 +5 V supply
5 Ground 12 -12 V supply
6 Ground 13 -5 V supply
7 +12 V supply USB Connector

Battery Pack Connector 1Vcc

Pin Signal Pin Signal 2 Data —

1 VBATT 3 not connected 3 Data +
2 orientation key 4 Ground 4 Ground

RJ-45 UTP Connector

PS2 Connector for System Board

Pin Signal

VGA Connector

Keyboard and Mouse Connector

Serial Port Connector

46

15-DDC clock

Parallel Port Connector

4

Summary of the HP/Phoenix BIOS

The Setup program and HP/Phoenix BIOS are summarized in this chapter.
The POST routines are described in the next chapter.

47

4 Summary of the HP/Phoenix BIOS

HP/Phoenix BIOS Summary

HP/Phoenix BIOS Summary

The System ROM contains the POST (power-on self-test) routines, and the
BIOS: the System BIOS, video BIOS, network BIOS, and low option ROM.
This chapter, and the following one, give an overview of the following
aspects:

• menu-driven Setup with context-sensitive help (in US English only), de-

scribed next in this chapter.

• The address space, with details of the interrupts used, described at the
end of this chapter.

• The Remote Power-On (RPO), which is the mechanism for turning on the
computer remotely from the network, described later in this chapter.

• The Power-On-Self-Test or POST, which is the sequence of tests the com­puter performs to ensure that the system is functioning correctly, de­scribed in the next chapter.

The system BIOS is identified by a version number of the form

HH.xx.xx

.

The procedure for updating the System ROM firmware is described on page

30.

Press , to run the Setup program, while the initial “Vectra” logo is being
displayed immediately after restarting the PC. Alternatively, press
followed by to view the summary configuration screen, an
example of which is depicted on the next page. By default, this remains on
the screen for 20 seconds, but by pressing once, it can be held on the
screen indefinitely until is pressed. Pressing will cause the
computer to be turned off.

48

4 Summary of the HP/Phoenix BIOS

HP/Phoenix BIOS Summary

Vectra VE/200 — Copyright 1997 Hewlett-Packard — 3.0

Any line of text can be entered here as a ‘tatoo’ for the computer

BIOS version HH.xx.xx PC Serial Number FR54011111

CPU Date Code N/A LAN MAC address 08-0009-85-03-00

System RAM : 32 MB Processor type : Pentium

Bank A : 32 MB (SDRAM) COM1 : 3F8H (Serial)

Bank B : None COM2 : None

Bank C : None COM3 : None

Video RAM : 2 MB COM4 : None

System Cache : 256KB (Pipeline Burst) LPT1 : 378H

Video Device : S3 LPT2 : None

1st IDE Device : HDD 1600 MB LPT3 : None

2nd IDE Device : None Flexible Disk A : 1.44 MB

3rd IDE Device : None Flexible Disk B : None

4th IDE Device : None Display type : Not Available

ISA PnP : Not Installed PCI Slot #1 : Not Installed

PCI Slot #2 : Not Installed

PCI Slot #3 : Not Installed

PCI Slot #4 : Not Installed

<F1> to continue, <F2> to run Setup, <F10> to power off, <F5> to retain

49

4 Summary of the HP/Phoenix BIOS

Setup Program

Setup Program

To run th e Setup program, interrupt the POST by pressing when the
initial “Vectra” logo screen is being displayed, just after restarting the PC.

The band along the top of the screen offers five menus: Main, Advanced,
Security, Power, and Exit. These are selected using the left and right arrow
keys. Each menu is discussed in the following sub-sections. For a more
complete description, see the User’s Guide that was supplied with the PC.

Main Menu

The Main Menu presents the user with a list of fields, such as “System Time”
and “Key auto-repeat speed”. These can be selected using the up and down
arrow keys, and can have their values changed using the and keys.

The “Item-Specific Help” field changes automatically as the user moves the
cursor between the fields. It tells the user what the presently highlighted
field is for, and what the options are.

Some fields are not changeable. Examples include fields that are for
information only, and fields whose contents become “frozen” by the setting
of a value in some other field. Such fields are displayed in a different color,
without the “[” and “]” brackets. When the user moves the cursor with the up
and down arrow keys, these fields are skipped.

Some fields disappear completely when a choice in another field makes their
appearance inappropriate.

Advanced Menu

The Advanced Menu does not have the same structure as the Main Menu
and Power Menu. Instead of presenting a list of fields, it offers the user with
a list of sub-menus. Again, the user steps between the options using the up
and down arrow keys, but presses the key to enter the chosen sub­menu (and the key to go back again when finished).

If access to devices has been disabled in the Security Menu, then the
configuration of those devices on the Advanced Menu becomes frozen:
the field becomes starred, appears in a different color, and cannot be
changed.

50

4 Summary of the HP/Phoenix BIOS

Setup Program

Security Menu

Sub-menus are presented for changing the characteristics and values of the
User Password, the System Administrator Password, the amount of
protection against use of the system’s drives and network connections
(using the Hardware Protection sub-menu), and the amount of protection
against being able to boot from the system’s drives and network connections
(using the Start-Up Center sub-menu).

Locking a device in the Security Menu frees the resources (such as IRQs and
peripheral addresses).

Power Menu

The “Power” menu allows the user to set the standby delay. It also allows the
system administrator to decide whether the network, serial port, mouse, or
space bar are enabled as a means of reactivating the system from Standby
or Suspend. It is also possible to specify whether the network is enabled as
a means of reactivating the system from Off, using the remote power-on
(RPO) facility (as described in the next section of this chapter).

51

4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

Power Saving and Ergonometry

Fully-On Standby Suspend

Processor Normal speed Clock throttled (divided

by 8)

Display Normal operation Blanked (<30 W) Blanked (<5 W typical) Blanked (<5 W typical)

Hard disk drive Normal speed Normal speed Halted Halted

Power consumption 24 W to 41 W

depending on
configuration & activity

Resume events Keyboard, mouse Keyboard

Resume delay Instantaneous A few seconds Boot delay

<30 W (230V, 50 Hz)
<27 W (115V, 60 Hz)

Halted Halted

<26 W (230V, 50 Hz)
<22 W (115V, 60 Hz)

Network (RWU)

<1.6 W (230V, 50 Hz)
<0.5 W (115V, 60 Hz)

Space-bar
Network (RPO)

Off

(but plugged in)

Desktop Management Interface (DMI)

HP TopTOOLS 2 is an integrated, easy-to-use desktop management
application for efficient inventory, configuration, fault and security
management. It is fully DMI compliant. It provides facilities for real-time
monitoring and management of over 300 attributes of the PC (both the local
PC, and remote ones over the network).

HP Lock

HP Lock provides a convenient and dynamic access to the security features
of the PC. Facilities are provided for:

•Passwords

• Lock options (such as screen hiding and screen saving)

• Start-up protection

• Disk drive access (enabled or disabled)

• Communications port access (enabled or disabled)

52

4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

HP Lock uses the dynamic link library

gina.dll

, which is the standard
entry point to the Windows NT security engine. If you use another software
application that also makes use of, or replaces this file (another security
application for example) then it is not recommended to install HP Lock. The

gina.dll

file is not designed to be shared by multiple client applications.

Power-On from Space-Bar

The power-on from the space-bar function is enabled, provided that:

• The computer is connected to a Power-On keyboard (recognizable by the

Power-On icon on the space bar).

• The function has not been disabled by setting SW-9 to

on the system

open

board switches.

• The function has not been disabled in the “Power” menu of the Setup pro-

gram.

HP Off and Soft Power Down

When the user requests the operating system to shutdown, the environment
is cleared, and the computer is powered off.

If the user attempts to turn the PC off at the status panel, the PC logic will
delay the shutting down of the power supply until it is safe to do so. HP Off
protects the user from some types of unintentional data loss, providing a
safe shutdown of running applications and unsaved files.

In the control panel, double-click on the Power icon.

1

Click on the

2

HP Off

tab to select HP Off, or on

Immediate Power Off

to
cancel it.
Select the time-out period, between one and five seconds.

3

The time-out period is the delay during which the power-down command
can be cancelled (whilst the

About to shut down Windows

message is
displayed on the screen). If the user cancels, the computer is returned to
normal operation; otherwise, the computer goes on to check if there are any
unsaved files. If there are, it offers three choices:

(thereby shutting down without saving

changes, followed by shutdown),
the changes), and

cancel

(to return to normal operation).

no

(to saving the unsaved

yes

53

4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

Remote Power-On (RPO)

Remote power-on (RPO) provides a way to turn on the computer from a
communication channel, such as a Network or Modem, using facilities that
have been incorporated in the X-Ben chip and the ExtStart connector. It
allows system administrators, and authorized users, to switch on the
computer from anywhere over an Ethernet network, to perform remote
administration or other tasks, and to return it to Off or Suspend mode
afterwards.

Magic Packet

Magic packet is a standard for remote power-on and remote wake-up. The
standard defines a Magic Packet frame as the computer’s unique Ethernet
Media Access Control (MAC) address (which it has stored in an EEPROM
on the network board), repeated 16 times and encoded in a valid network
packet.

Any Magic Packet-compatible management application (such as HP Open-
View Workgroup Node Manager) can send a Magic Packet frame. An
administrator can do this manually, or can incorporate it into a management
script. The packet travels over any type of Ethernet LAN to the target PC.

The only component not completely turned off in the computer is the net­work chip, which rests in a special low power mode. Power is supplied by a
line called VStandby, on the External Start connector (see the pin layout in
the table on page 42) as long as the power cord is plugged in. The indepen­dent mini power supply provides the power necessary to keep one part of
the network chip ready to receive a wake-up signal. This is the only signal it
can respond to in this state.

The network chip sends a signal over the External Start connector, where it
is received by the special network remote power chip. This in turn switches
on the main power supply.

The PC starts normally from whatever operating system is installed, just as if
the power supply had been switched on from the external power switch.
The display does not itself need to have an RPO function. If a password has
been set, the

Start with keyboard locked

option must be enabled.

Activity within the Setup Program

54

4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

Since the user is not physically present, the level of security must be tighter.
There is a distinction between the user-boot process, and the RPO-boot
process. HP provides all the necessary Setup options to keep users from
interfering with the computer during the remote session.

RPO is available when the POST routines have finished executing. It is
initialized by an SMI signal which is triggered from the mains power button.

A power failure when the computer is in RPO mode will deactivate the RPO
feature. RPO is intended for resource management (such as virus cleaners,
nightly backups, etc.), not for crisis management (thunderstorm recovery,
power failure, etc.).

Advanced Power Management (APM)

The BIOS is APM 1.2 compliant, providing it with facilities for advanced
power management (APM). It supports the following modes: Fully-on,
Standby, Suspend, Hibernation and Off. Of these, APM 1.2 supports
Fully-on, Standby, Suspend and Off, as summarized in the table on page

52.

When the user requests a ShutDown from the operating system, the
environment is first cleared. The BIOS first performs some RPO
initialization, and then proceeds to power down the computer. Any request
to turn off the computer, from the status panel, or from the operating
system, can only be granted if the computer is not locked by the lock bit
(otherwise the power remains on, a red light is illuminated, and the buzzer is
sounded).

RPO defines a variation from the standard Off state. In RPO mode, the main
CPU hardware is off while a RPO function is powered by a power supply
called VStandby. VStandby is active as soon as the computer is plugged in.
RPO hardware can produce a triggering signal which turns on the computer.

The following diagram gives a simplified view of the useful states that the
computer can be in: the three On states (Fully-On, Standby and
Suspend), the RPO state (when the CPU is Off, and the RPO hardware is
powered by VStandby), the Off state (when everything is powered off), and
the state that is caused by power failure or unplugging the computer.

55

4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

56

4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

The following diagram gives a more accurate, more detailed account of the
valid state changes.

If the computer ‘hangs’, the power button on the status panel should be held
‘pressed’ for about 6 seconds. A watch-dog timer will detect that the BIOS is
inactive, and not reloading the timer once every 6 seconds, thereby forcing
the computer to turn itself off without further BIOS acknowledgment.

57

4 Summary of the HP/Phoenix BIOS

BIOS Addresses

BIOS Addresses

This section provides a summary of the main features of the HP system
BIOS. This is software that provides an interface between the computer
hardware and the operating system.

System Memory Map

Any reserved memory that is used by accessory boards must be located in
the area from C8000h to EFFFFh.

0 - 3FFh Interrupt vector table 640 KB: The addresses 0-9FFFFh are

400h - 4FFh BIOS data area

500h - 9EFFFh

collectively known as the Base
memory area

9F000h - 9FFFFh Extended BIOS data area

A0000h - BFFFFh 128 KB: Video memory area

C0000h - C7FFFh 32 KB: Video BIOS area

C8000h - D7FFFh 64 KB: available for accessory boards

(used by the boot ROM, if configured in the

D8000h - EFFFFh 96 KB: available after the POST (for upper memory block, UMB, for example)

F0000h - FFFFFh 64 KB: System BIOS area

100000h - FFFFFFFFh 1 MB plus: Extended memory

Setup

program)

Product Identification

The reserved addresses in the 64 KB BIOS ROM data area, which contain
various product identification and BIOS identification strings, are no longer
accessed directly. Instead, the information is obtained from utilities in the
Desktop Management Interface (DMI).

58

4 Summary of the HP/Phoenix BIOS

BIOS Addresses

HP I/O Port Map (I/O Addresses Used by the System1)

Peripheral devices, accessory devices and system controllers are accessed
via the system I/O space, which is not located in system memory space. The
64 KB of addressable I/O space comprises 8-bit and 16-bit registers (called
I/O ports) located in the various system components. When installing an
accessory board, ensure that the I/O address space selected is in the free
area of the space reserved for accessory boards (100h to 3FFh).

Although the Setup program can be used to change some of the settings, the
following address map is not completely BIOS dependent, but is determined
partly by the operating system. Beware that some of the I/O addresses are
allocated dynamically.

I/O Address Ports Function

0000h - 000Fh DMA controller 1

0020h - 0021h Interrupt controller 1

0040h - 0043h Interval timer 1

0060h, 0064h Keyboard controller

0061h System speaker, or NMI status and control

0070h NMI mask register, RTC and CMOS address

0071h RTC and CMOS data

0081h - 0083h, 008Fh DMA low page register

0092h Alternate reset and A20 Function

00A0h - 00A1h Interrupt controller 2

00C0h - 00DFh DMA controller 2

00EAh - 00EBh Internal port

00F0h - 00FFh Co-processor error

0102h Graphics controller (S3 Trio 64V2)

0170h - 0177h IDE hard disk drive controller secondary channel

01F0h - 01F7h IDE hard disk drive controller primary channel

1. If configured (legacy resources only).

59

4 Summary of the HP/Phoenix BIOS

BIOS Addresses

I/O Address Ports Function

0278h - 027Fh Parallel port 2

0279h IO read data port for ISA Plug and Play enumerator

02E8h - 02EFh Serial port 4 (available if not used)

02F8h - 02FFh Serial port 2 (available if not used)

0370h - 0371h Super I/O controller

0372h - 0375h Secondary flexible disk drive controller

0376h IDE hard disk drive controller secondary channel

0377h Secondary flexible disk drive controller

0378h - 037Ah Parallel port 1 (available if not used)

03B0h - 03DFh Graphics controller (S3 Trio 64V2)

03E8h - 03EFh Serial port 3

03F0h - 03F5h Primary flexible disk drive controller

03F6h IDE hard disk drive controller primary channel

03F7h Primary flexible disk drive controller

03F8h - 03FFh Serial port 1

0678h - 067Bh Parallel port 2 if ECP mode is selected

0778h - 077Bh Parallel port 1 if ECP mode is selected

0CF8h - 0CFFh Configuration registers for PCI devices

DMA Channel Controllers

Only “I/O-to-memory” and “memory-to-I/O” transfers are allowed.
“I/O-to-I/O” and “memory-to-memory” transfers are disallowed by the
hardware configuration.

The system controller supports seven DMA channels, each with a page
register used to extend the addressing range of the channel to 16 MB. The
following table summarizes how the DMA channels are allocated.

60

4 Summary of the HP/Phoenix BIOS

First DMA controller (used for 8-bit transfers)

Channel Function

0 Available

1 ECP mode for parallel port (available if not used)

2 Flexible disk controller

3 ECP mode for parallel port (available if not used)

Second DMA controller (used for 16-bit transfers)

Channel Function

4 Cascade from first DMA controller

BIOS Addresses

5 Available

6 Available

7 Available

Interrupt Controllers

The system has two 8259A compatible interrupt controllers. They are
arranged as a master interrupt controller and a slave that is cascaded
through the master.

The following table shows how the master and slave controllers are con­nected. The Interrupt Requests (IRQ) are numbered sequentially, starting
with the master controller, and followed by the slave.

IRQ (Interrupt Vector) Interrupt Request Description

IRQ0(08h) System timer
IRQ1(09h) Keyboard controller
IRQ2(0Ah) Slave IRQ Cascade connection from INTC2 (Interrupt Controller 2)

IRQ8(70h) Real Time Clock
IRQ9(71h) Available

61

4 Summary of the HP/Phoenix BIOS

BIOS Addresses

IRQ10(72h) Available
IRQ11(73h) Reserved (used by the DHCP)
IRQ12(74h) Mouse
IRQ13(75h) Co-processor
IRQ14(76h) IDE controller

IRQ15(77h) Secondary IDE (available if not used)
IRQ3(0Bh) Serial Port 2, Serial Port 4 (available if not used)
IRQ4(0Ch) Serial Port 1, Serial Port 3 (available if not used)
IRQ5(0Dh) Parallel Port 2 (available if not used)
IRQ6(0Eh) Flexible Disk Controller
IRQ7(0Fh) Parallel Port 1 (available if not used)

Using the Setup program:

• IRQ4 can be made available by disabling serial ports 1 and 3.

• IRQ5 can be made available by disabling the parallel port 2.

• IRQ7 can be made available by disabling parallel ports 1 and 2.
The IDE controller (device 04h, function 01h) is configured in legacy mode,

and uses IRQ 14 (IRQ 15 for the secondary channel).

PCI Interrupt Request Lines

PCI devices generate interrupt requests using up to four PCI interrupt
request lines (INTA#, INTB#, INTC#, and INTD#).

When a PCI device makes an interrupt request, the request is re-directed to
the system interrupt controller. The interrupt request will be re-directed to
one of the IRQ lines made available for PCI devices.

The PCI interrupt lines A, B, C and D are spread across the four inputs of
the interrupt router (which is part of the PCI/ISA bridge, in the Bridge
chip). Since most PCI devices are single-function, this allows for an even
distribution of the lines. The distribution is shown in the following diagram.

62

4 Summary of the HP/Phoenix BIOS

BIOS Addresses

Integrated

graphics

A

Slot 1

ABCD

PCI interrupts are then mapped into ISA interrupts inside the Bridge chip,
by configuring registers 60h through 63h.

7 Routing of interrupts: when enabled, this bit routes the PCI interrupt signal to the PC-

6:4 Reserved: read as 000

3:0 IRQx# Routing Bits: these bits specify which IRQ signal to generate.

Slot 2

ABCD

Slot 3

ABCD

Slot 4

ABCD

Bit Description

compatible interrupt signal specified in bits[3:0]. At reset, this bit is disabled (set to 1)

Possible values are: 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15.

A
B

PCI/ISA
Bridge

C
D

63

4 Summary of the HP/Phoenix BIOS

BIOS Addresses

64

5

Power-On Self-Test and Error Messages

This chapter describes the Power-On Self-Test (POST) routines, which are
contained in the System BIOS, the error messages that can result, and the
suggestions for corrective action.

65

5 Power-On Self-Test and Error Messages

Order in Which the Tests are Performed

Order in Which the Tests are Performed

Each time the system is powered on, or a reset is performed, the POST is
executed. The POST process verifies the basic functionality of the system
components and initializes certain system parameters.

The POST starts by displaying a graphic screen with the initial “Vectra” logo
when the PC is restarted. If the POST detects an error, the error message is
displayed inside a view system errors screen, in which the error message
utility (EMU) not only displays the error diagnosis, but the suggestions for
corrective action (see page 69 for a brief summary). Error codes are no
longer displayed.

Devices, such as memory and newly installed hard disks, are configured
automatically. The user is not requested to confirm the change. Newly
removed hard disks are detected, and the user is prompted to confirm the
new configuration by pressing . Note, though, that the POST does not
detect when a hard disk drive has been otherwise changed.

During the POST, the BIOS and other ROM data is copied into high-speed
shadow RAM. The shadow RAM is addressed at the same physical location
as the original ROM in a manner which is completely transparent to
applications. It therefore appears to behave as very fast ROM. This
technique provides faster access to the system BIOS firmware.

The following table lists the POST routines in the order in which they are
executed (from the shadow RAM). If the POST is initiated by a soft reset

and , the RAM tests are not executed and shadow RAM is

Delete

not cleared. In all other respects, the POST executes in the same way
following power-on or a soft reset.

Test Description

System BIOS Tests

LED Test

System ROM (BIOS) Test

RAM Refresh Timer Test

Interrupt RAM Test

Tests the LEDs on the status panel.

Calculates an 8-bit checksum. Test failure causes the boot process to abort.

Tests the RAM refresh timer circuitry. Test failure causes the boot process
to abort.

Checks the first 64 KB of system RAM used to store data corresponding to
various system interrupt vector addresses. Test failures cause the boot
process to abort.

66

Shadow the System ROM BIOS

Load CMOS Memory

CMOS RAM Test

CPU Cache Memory Test

Initialize the Graphics Controller

8042 Self-Test

Timer 0/Timer 2 Test

DMA Subsystem Test

Interrupt Controller Test

Real-Time Clock Test

RAM Address Line

Independence Test

Size Extended Memory

Real-Mode Memory Test (First

640KB)

Shadow RAM Test

5 Power-On Self-Test and Error Messages

Order in Which the Tests are Performed

Tests the system ROM BIOS and shadows it. Failure to shadow the ROM
BIOS will cause an error code to display. The boot process will continue, but
the system will execute from ROM. This test is not performed after a soft
reset (using and ).

Delete

Checks the serial EEPROM and returns an error code if it has been
corrupted. Copies the contents of the EEPROM into CMOS RAM.

Checks the CMOS RAM for start-up power loss, verifies the CMOS RAM
checksums. Test failure causes error codes to display.

Tests the processor’s internal level-one cache RAM. Test failure causes an
error code to display and the boot process to abort.

Video Tests

Initializes the graphics subsystem, tests the video shadow RAM, and
shadows the video BIOS. A failure causes an error code to display, but the
boot process continues.

System Board Tests

Downloads the 8042 and invokes the 8042 internal self-test. A failure
causes an error code to display.

Tests Timer 0 and Timer 2. Test failure causes an error code to display.

Checks the DMA controller registers. Test failure causes an error code to
display.

Tests the Interrupt masks, the master controller interrupt path (by forcing
an IRQ0), and the industry-standard slave controller (by forcing an IRQ8).
Test failure causes an error code to display.

Checks the real-time clock registers and performs a test that ensures that
the clock is running. Test failure causes an error code to display.

Memory Tests

Verifies the address independence of real-mode RAM (no address lines stuck
together). Test failure causes an error code to display.

Sizes and clears the protected mode (extended) memory and writes the
value into CMOS bytes 30h and 31h. If the system fails to switch to
protected mode, an error code is displayed.

Read/write test on real-mode RAM. (This test is
using and ). The test checks each block of

Delete

not

done during a reset

system RAM to determine how much is present. Test failure of a 64 KB
block of memory causes an error code to display, and the test is aborted.

Tests shadow RAM in 64 KB segments (except for segments beginning at
A000h, B000h, and F000h). If they are

not

being used, segments C000h,

D000h and E000h are tested. Test failure causes an error code to display.

67

5 Power-On Self-Test and Error Messages

Order in Which the Tests are Performed

Protected Mode RAM Test

(Extended RAM)

Keyboard Test

Mouse Test

Network Test

Flexible Disk Controller

Subsystem Test

Internal Numeric Coprocessor

Test

Parallel Port Test

Serial Port Test

Hard Disk Controller Subsystem

Test

System Generation

Plug and Play
Configuration

Tests protected RAM in 64 KB segments above 1 MB. (This test is
during a reset using and ). Test failure causes an

Delete

not

done

error code to display.

Keyboard / Mouse Tests

Invokes a built-in keyboard self-test of the keyboard’s microprocessor and
tests for the presence of a keyboard and for stuck keyboard keys. Test
failure causes an error code to display.

If a mouse is present, invokes a built-in mouse self-test of the mouse’s
microprocessor and for stuck mouse buttons. Test failure causes an error
code to display.

If the network board is present, invokes a built-in self-test. Test failure
causes an error code to display.

Tests of Flexible Disk Controller

Tests for proper operation of the flexible disk controller. Test failure causes
an error code to display.

Coprocessor Tests

Checks for proper operation of the numeric coprocessor part of the
processor. Test failure causes an error code to display.

Communication Port Tests

Tests the integrated parallel port registers, as well as any other parallel
ports. Test failure causes an error code to display.

Tests the integrated serial port registers, as well as any other serial ports.
Test failure causes an error code to display.

Hard Disk Drive Tests

Tests for proper operation of the hard disk controller. Test failure causes an
error code to display. The test does not detect hard disk replacement or
changes in the size of the hard disk.

System Configuration Tests

Initiation of the system generation (SYSGEN) process, which compares the
configuration information stored in the CMOS memory with the actual
system. If a discrepancy is found, an error code will be displayed.

Configures any Plug and Play device detected:
❒ All PCI devices will be configured for use.

68

5 Power-On Self-Test and Error Messages

Error Message Summary

Error Message Summary

The POST section of the HP BIOS no longer displays numeric error codes
(such as 910B) but gives a self-explanatory, descriptive diagnosis, and a list
of suggestions for corrective action. The following table summarizes the
most significant of the problems that can be reported.

Message Explanation or Suggestions for Corrective Action

Operating system not found Check whether the disk drive is connected.

Setup

.

Security

If it is connected, check that it is detected by POST
Check that your boot device is enabled on the
menu.
If the problem persists, check that the boot device contains the
operating system.

Missing operating system If you have configured the hard disk user parameters, check that

they are correct. Otherwise, use the hard disk “Auto” parameters.

Failure fixed disk
(preceded by a 30” time-out)

System battery is dead You may get this message if the computer is disconnected for a

Keyboard error Check that the keyboard is connected.
Resource Allocation Conflict -PCI

device 0079 on system board
Video Plug and Play interrupted or

failed. Re-enable in Setup and try again
System CMOS checksum bad - run

Setup
No message, system “hangs” after

POST
Other An error message may be displayed and the computer may “hang”

Check that the hard disk is connected.
Check that the hard disk is detected in POST.
Check that boot on the hard disk drive is enabled in

few days. When you Power-on the computer, run
the configuration information. The message should no longer be
displayed. Should the problem persist, replace the battery.

Clear CMOS.

You may have powered your computer Off/On too quickly and the
computer turned off Video plug and play as a protection.

CMOS contents have changed between 2 power-on sessions. Run

Setup

for configuration.

Check that the main memory modules are correctly set in their
sockets.

for 20 seconds and then beep. The POST is probably checking for a
mass storage device which it cannot find and the computer is in
Timeout Mode. After Timeout, run
configuration.

Setup

to check the

Setup

Setup

.

to update

69

5 Power-On Self-Test and Error Messages

Beep Codes

Beep Codes

If a terminal error occurs during POST, the system issues a beep code before
attempting to display the error. Beep codes are useful for identifying the
error when the system is unable to display the error message.

Beep Pattern

Beep

Code

1

Numeric

Code

Description

- 1 B4h This does not indicate an error. There is one short beep before
system startup.

—

- - 02 98h Video configuration failure or option ROMs check-sum failure

—

- - - - - - - 0223 16h BIOS ROM check-sum failure

—

- - - —

—

- - - —

—

- - -

—

- - - - - - - - - - 0343 2Eh RAM failure on data bits in low byte of memory bus

—

- - - - —

- - —

- - - - - - - —

—

- - — - - - - 02022 Continuous beeps. Keyboard error

—

- - -

- - - - —

—

0300 20h DRAM refresh test failure
0303 22h 8742 Keyboard controller test failure
0340 2Ch RAM failure

0400 30h RAM failure on data bits in high byte of memory bus

- - - - - 2023 46h ROM copyright notice check failure
2230 58h Unexpected interrupts test failure

1.

Where digits 1, 2, 3, 4 represent the number of short beeps, and 0

represents the occurrence of a single long beep.

Lights on the Status Panel

When the computer is first powered on, the power-on light on the status
panel illuminates yellow for about a second before changing to green. This
change of color is caused by the execution of an instruction early in the
System BIOS code.

If the light remains at yellow, therefore, it indicates a failure of the processor
or the System ROM in the instruction-fetch process. Check that the
processor is correctly seated in its socket.

70